Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-01-24 | clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag | Tejas Patel | 1 | -5/+31 |
2020-01-24 | clk: zynqmp: Fix divider calculation | Rajan Vaja | 1 | -0/+46 |
2020-01-24 | clk: zynqmp: Add support for get max divider | Rajan Vaja | 1 | -0/+36 |
2019-04-11 | clk: zynqmp: fix check for fractional clock | Michael Tretter | 1 | -3/+6 |
2019-04-11 | clk: zynqmp: do not export zynqmp_clk_register_* functions | Michael Tretter | 1 | -1/+0 |
2019-04-11 | drivers: clk: zynqmp: Allow zero divisor value | Rajan Vaja | 1 | -0/+7 |
2018-10-09 | drivers: clk: Add ZynqMP clock driver | Jolly Shah | 1 | -0/+217 |