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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c
AgeCommit message (Expand)AuthorFilesLines
2021-06-09drm/i915/adl_p: CDCLK crawl support for ADLStanislav Lisovskiy1-9/+63
2021-06-08drm/i915: Disable PSR around cdclk changesVille Syrjälä1-0/+13
2021-05-15drm/i915/display/adl_p: Implement Wa_22011320316José Roberto de Souza1-1/+20
2021-05-15drm/i915: Move intel_modeset_all_pipes()Ville Syrjälä1-38/+0
2021-05-15drm/i915/adl_p: Add cdclk support for ADL-PAnusha Srivatsa1-13/+28
2021-05-05drm/i915: Use intel_de_wait_for_*() in cnl+ cdclk programmingVille Syrjälä1-6/+4
2021-05-05drm/i915: Use intel_de_rmw() in bxt/glk/cnl+ cdclk programmingVille Syrjälä1-10/+4
2021-05-05drm/i915: Use intel_de_rmw() in skl cdclk programmingVille Syrjälä1-14/+11
2021-05-05drm/i915: Use intel_de_rmw() in bdw cdclk programmingVille Syrjälä1-11/+6
2021-05-05drm/i915: Extract some helpers to compute cdclk register valuesVille Syrjälä1-98/+88
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2021-04-14drm/i915/display: rename display version macrosLucas De Marchi1-9/+9
2021-04-14drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper1-16/+18
2021-03-24drm/i915/display: Simplify GLK display version testsMatt Roper1-12/+14
2021-03-24drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper1-29/+29
2021-03-24drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGEMatt Roper1-2/+2
2021-02-05drm/i915: Index min_{cdclk,voltage_level}[] with pipeVille Syrjälä1-4/+4
2021-02-02drm/i915: Remove references to struct drm_device.pdevThomas Zimmermann1-7/+7
2020-12-04drm/i915: Add intel_atomic_add_affected_planes()Ville Syrjälä1-2/+1
2020-12-01drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()Jani Nikula1-2/+2
2020-10-16drm/i915/rkl: Add new cdclk tableMatt Roper1-1/+31
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay1-2/+2
2020-10-07drm/i915/dg1: Initialize RAWCLK properlyMatt Roper1-1/+15
2020-09-17drm/i915: Nuke force_min_cdclk_changedVille Syrjälä1-1/+1
2020-09-08Merge tag 'v5.9-rc4' into drm-nextDave Airlie1-5/+5
2020-08-24treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-5/+5
2020-08-17drm/i915: Make i830 .get_cdclk() assignment less confusingVille Syrjälä1-4/+5
2020-08-17drm/i915: Fix some whitespaceVille Syrjälä1-1/+1
2020-07-03drm/i915/tgl: Clamp min_cdclk to max_cdclk_freq to unblock 8KStanislav Lisovskiy1-2/+9
2020-06-08Revert "drm/i915: Remove unneeded hack now for CDCLK"Stanislav Lisovskiy1-0/+12
2020-06-04drm/i915: Fix wrong CDCLK adjustment changesStanislav Lisovskiy1-8/+11
2020-05-22drm/i915: Fix includes and local vars orderStanislav Lisovskiy1-1/+2
2020-05-22drm/i915: Remove unneeded hack now for CDCLKStanislav Lisovskiy1-12/+0
2020-05-22drm/i915: Adjust CDCLK accordingly to our DBuf bw needsStanislav Lisovskiy1-4/+24
2020-05-19drm/i915: Read out hrawclk on all gen3+ platformsVille Syrjälä1-24/+40
2020-05-19drm/i915: Document our lackluster FSB frequency readoutVille Syrjälä1-1/+10
2020-05-19drm/i915: Fix 400 MHz FSB readout on elkVille Syrjälä1-2/+7
2020-03-09drm/i915: Lock gmbus/aux mutexes while changing cdclkVille Syrjälä1-0/+22
2020-02-23drm/i915/display/cdclk: Make WARN* drm specific where drm_priv ptr is availablePankaj Bharadiya1-36/+48
2020-02-19drm/i915: Read rawclk_freq earlierChris Wilson1-9/+10
2020-02-11drm/i915: Fix the docs for intel_set_cdclk_post_plane_update()Ville Syrjälä1-1/+1
2020-02-10drm/i915/tgl: Update cdclk voltage level settingsMatt Roper1-1/+18
2020-01-31drm/i915: Store active_pipes bitmask in cdclk stateVille Syrjälä1-9/+11
2020-01-31drm/i915: Convert cdclk to global stateVille Syrjälä1-83/+109
2020-01-31drm/i915: Introduce better global state handlingVille Syrjälä1-4/+4
2020-01-31drm/i915: s/init_cdclk/init_cdclk_hw/Ville Syrjälä1-12/+12
2020-01-31drm/i915: swap() the entire cdclk stateVille Syrjälä1-15/+3
2020-01-31drm/i915: Extract intel_cdclk_stateVille Syrjälä1-77/+91
2020-01-31drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling conventionVille Syrjälä1-22/+22
2020-01-31drm/i915: s/cdclk_state/cdclk_config/Ville Syrjälä1-211/+215
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