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path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-24drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper1-52/+52
2021-03-19drm/i915: Split intel_ddi_encoder_reset() from intel_dp_encoder_reset()Ville Syrjälä1-1/+10
2021-03-18drm/i915/bios: add intel_bios_encoder_data to encoder, use for iboostJani Nikula1-4/+5
2021-03-18drm/i915/bios: start using intel_bios_encoder_data for Type-C USB and TBTJani Nikula1-2/+2
2021-03-18drm/i915/bios: start using the intel_bios_encoder_data directlyJani Nikula1-3/+12
2021-03-11drm/i915: Tolerate bogus DPLL selectionVille Syrjälä1-4/+13
2021-03-08drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platformsVille Syrjälä1-1/+1
2021-03-08drm/i915: Add encoder->is_clock_enabled()Ville Syrjälä1-2/+121
2021-03-08drm/i915: Move DDI clock readout to encoder->get_config()Ville Syrjälä1-23/+298
2021-03-05drm/i915: Move pipe enable/disable tracepoints to intel_crtc_vblank_{on,off}()Ville Syrjälä1-2/+0
2021-03-04drm/i915/edp: enable eDP MSO during link trainingJani Nikula1-0/+37
2021-03-04drm/i915/mso: add splitter state readout for platforms that support itJani Nikula1-0/+41
2021-02-16drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routingVille Syrjälä1-19/+19
2021-02-16drm/i915: Relocate icl_sanitize_encoder_pll_mapping()Ville Syrjälä1-56/+56
2021-02-16drm/i915: Use .disable_clock() for pll sanitationVille Syrjälä1-90/+2
2021-02-16drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,disable}_clock()Ville Syrjälä1-29/+62
2021-02-16drm/i915: Extract _cnl_ddi_{enable,disable}_clock()Ville Syrjälä1-64/+44
2021-02-16drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()Ville Syrjälä1-0/+6
2021-02-16drm/i915: Sprinkle a few missing locks around shared DDI clock registersVille Syrjälä1-0/+8
2021-02-16drm/i915: Use intel_de_rmw() for DDI clock routingVille Syrjälä1-49/+28
2021-02-16drm/i915: Extract icl+ .{enable,disable}_clock() vfuncsVille Syrjälä1-58/+99
2021-02-16drm/i915: Convert DG1 over to .{enable,disable}_clock()Ville Syrjälä1-22/+21
2021-02-16drm/i195: Extract cnl_ddi_{enable,disable}_clock()Ville Syrjälä1-20/+42
2021-02-16drm/i915: Extract skl_ddi_{enable,disable}_clock()Ville Syrjälä1-15/+38
2021-02-16drm/i915: Extract hsw_ddi_{enable,disable}_clock()Ville Syrjälä1-6/+26
2021-02-16drm/i915: Introduce .{enable,disable}_clock() encoder vfuncsVille Syrjälä1-6/+23
2021-02-16drm/i915: Use intel_ddi_clk_select() for FDIVille Syrjälä1-3/+3
2021-02-13drm/i915/gen9_bc: Introduce HPD pin mappings for TGP PCH + CML combosLyude Paul1-0/+10
2021-02-11drm/i915/display: Handle lane polarity for DDI portUma Shankar1-0/+3
2021-02-08drm/i915: refactor skylake scaler code into new file.Dave Airlie1-0/+1
2021-02-08drm/i915: migrate skl planes code new file (v5)Dave Airlie1-0/+1
2021-02-05drm/i915: migrate hsw fdi code to new file.Dave Airlie1-144/+7
2021-02-05drm/i915: refactor ddi translations into a separate file (v2)Dave Airlie1-1405/+12
2021-02-02Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.or...Jani Nikula1-21/+41
2021-01-30drm/i915: Don't check tc_mode unless dealing with a TC PHYVille Syrjälä1-1/+3
2021-01-30drm/i915: Move HDMI vswing programming to the right placeVille Syrjälä1-15/+15
2021-01-30drm/i915: Power up combo PHY lanes for for HDMI as wellVille Syrjälä1-0/+2
2021-01-30drm/i915: Extract intel_ddi_power_up_lanes()Ville Syrjälä1-16/+19
2021-01-30drm/i915: Skip vswing programming for TBTVille Syrjälä1-0/+6
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup1-21/+41
2021-01-26drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare1-0/+19
2021-01-26drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare1-0/+2
2021-01-26drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare1-0/+3
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä1-13/+10
2021-01-21drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä1-4/+3
2021-01-19drm/i915: Fix the PHY compliance test vs. hotplug mishapVille Syrjälä1-0/+8
2021-01-14drm/i915/pps: rename intel_edp_panel_* to intel_pps_*Jani Nikula1-4/+4
2021-01-14drm/i915/pps: abstract panel power sequencer from intel_dp.cJani Nikula1-0/+1
2021-01-13drm/i915/hdcp: Encapsulate hdcp_port_data to dig_portAnshuman Gupta1-0/+2
2021-01-13drm/i915/hdcp: HDCP stream encryption supportAnshuman Gupta1-5/+5
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