summaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/octeon/cvmx-pow-defs.h
blob: 474dd544314be5a91347404ccdb2e1bedbb099a1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
 * Copyright (c) 2003-2012 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

#ifndef __CVMX_POW_DEFS_H__
#define __CVMX_POW_DEFS_H__

#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)

#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)

union cvmx_pow_bist_stat {
	uint64_t u64;
	struct cvmx_pow_bist_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t pp:16;
		uint64_t reserved_0_15:16;
#else
		uint64_t reserved_0_15:16;
		uint64_t pp:16;
		uint64_t reserved_32_63:32;
#endif
	} s;
	struct cvmx_pow_bist_stat_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_17_63:47;
		uint64_t pp:1;
		uint64_t reserved_9_15:7;
		uint64_t cam:1;
		uint64_t nbt1:1;
		uint64_t nbt0:1;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t nbr1:1;
		uint64_t nbr0:1;
		uint64_t pend:1;
		uint64_t adr:1;
#else
		uint64_t adr:1;
		uint64_t pend:1;
		uint64_t nbr0:1;
		uint64_t nbr1:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt0:1;
		uint64_t nbt1:1;
		uint64_t cam:1;
		uint64_t reserved_9_15:7;
		uint64_t pp:1;
		uint64_t reserved_17_63:47;
#endif
	} cn30xx;
	struct cvmx_pow_bist_stat_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_18_63:46;
		uint64_t pp:2;
		uint64_t reserved_9_15:7;
		uint64_t cam:1;
		uint64_t nbt1:1;
		uint64_t nbt0:1;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t nbr1:1;
		uint64_t nbr0:1;
		uint64_t pend:1;
		uint64_t adr:1;
#else
		uint64_t adr:1;
		uint64_t pend:1;
		uint64_t nbr0:1;
		uint64_t nbr1:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt0:1;
		uint64_t nbt1:1;
		uint64_t cam:1;
		uint64_t reserved_9_15:7;
		uint64_t pp:2;
		uint64_t reserved_18_63:46;
#endif
	} cn31xx;
	struct cvmx_pow_bist_stat_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t pp:16;
		uint64_t reserved_10_15:6;
		uint64_t cam:1;
		uint64_t nbt:1;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t nbr1:1;
		uint64_t nbr0:1;
		uint64_t pend1:1;
		uint64_t pend0:1;
		uint64_t adr1:1;
		uint64_t adr0:1;
#else
		uint64_t adr0:1;
		uint64_t adr1:1;
		uint64_t pend0:1;
		uint64_t pend1:1;
		uint64_t nbr0:1;
		uint64_t nbr1:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt:1;
		uint64_t cam:1;
		uint64_t reserved_10_15:6;
		uint64_t pp:16;
		uint64_t reserved_32_63:32;
#endif
	} cn38xx;
	struct cvmx_pow_bist_stat_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_20_63:44;
		uint64_t pp:4;
		uint64_t reserved_9_15:7;
		uint64_t cam:1;
		uint64_t nbt1:1;
		uint64_t nbt0:1;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t nbr1:1;
		uint64_t nbr0:1;
		uint64_t pend:1;
		uint64_t adr:1;
#else
		uint64_t adr:1;
		uint64_t pend:1;
		uint64_t nbr0:1;
		uint64_t nbr1:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt0:1;
		uint64_t nbt1:1;
		uint64_t cam:1;
		uint64_t reserved_9_15:7;
		uint64_t pp:4;
		uint64_t reserved_20_63:44;
#endif
	} cn52xx;
	struct cvmx_pow_bist_stat_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_28_63:36;
		uint64_t pp:12;
		uint64_t reserved_10_15:6;
		uint64_t cam:1;
		uint64_t nbt:1;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t nbr1:1;
		uint64_t nbr0:1;
		uint64_t pend1:1;
		uint64_t pend0:1;
		uint64_t adr1:1;
		uint64_t adr0:1;
#else
		uint64_t adr0:1;
		uint64_t adr1:1;
		uint64_t pend0:1;
		uint64_t pend1:1;
		uint64_t nbr0:1;
		uint64_t nbr1:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt:1;
		uint64_t cam:1;
		uint64_t reserved_10_15:6;
		uint64_t pp:12;
		uint64_t reserved_28_63:36;
#endif
	} cn56xx;
	struct cvmx_pow_bist_stat_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_20_63:44;
		uint64_t pp:4;
		uint64_t reserved_12_15:4;
		uint64_t cam:1;
		uint64_t nbr:3;
		uint64_t nbt:4;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t pend:1;
		uint64_t adr:1;
#else
		uint64_t adr:1;
		uint64_t pend:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt:4;
		uint64_t nbr:3;
		uint64_t cam:1;
		uint64_t reserved_12_15:4;
		uint64_t pp:4;
		uint64_t reserved_20_63:44;
#endif
	} cn61xx;
	struct cvmx_pow_bist_stat_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_22_63:42;
		uint64_t pp:6;
		uint64_t reserved_12_15:4;
		uint64_t cam:1;
		uint64_t nbr:3;
		uint64_t nbt:4;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t pend:1;
		uint64_t adr:1;
#else
		uint64_t adr:1;
		uint64_t pend:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt:4;
		uint64_t nbr:3;
		uint64_t cam:1;
		uint64_t reserved_12_15:4;
		uint64_t pp:6;
		uint64_t reserved_22_63:42;
#endif
	} cn63xx;
	struct cvmx_pow_bist_stat_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_26_63:38;
		uint64_t pp:10;
		uint64_t reserved_12_15:4;
		uint64_t cam:1;
		uint64_t nbr:3;
		uint64_t nbt:4;
		uint64_t index:1;
		uint64_t fidx:1;
		uint64_t pend:1;
		uint64_t adr:1;
#else
		uint64_t adr:1;
		uint64_t pend:1;
		uint64_t fidx:1;
		uint64_t index:1;
		uint64_t nbt:4;
		uint64_t nbr:3;
		uint64_t cam:1;
		uint64_t reserved_12_15:4;
		uint64_t pp:10;
		uint64_t reserved_26_63:38;
#endif
	} cn66xx;
};

union cvmx_pow_ds_pc {
	uint64_t u64;
	struct cvmx_pow_ds_pc_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t ds_pc:32;
#else
		uint64_t ds_pc:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_ecc_err {
	uint64_t u64;
	struct cvmx_pow_ecc_err_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_45_63:19;
		uint64_t iop_ie:13;
		uint64_t reserved_29_31:3;
		uint64_t iop:13;
		uint64_t reserved_14_15:2;
		uint64_t rpe_ie:1;
		uint64_t rpe:1;
		uint64_t reserved_9_11:3;
		uint64_t syn:5;
		uint64_t dbe_ie:1;
		uint64_t sbe_ie:1;
		uint64_t dbe:1;
		uint64_t sbe:1;
#else
		uint64_t sbe:1;
		uint64_t dbe:1;
		uint64_t sbe_ie:1;
		uint64_t dbe_ie:1;
		uint64_t syn:5;
		uint64_t reserved_9_11:3;
		uint64_t rpe:1;
		uint64_t rpe_ie:1;
		uint64_t reserved_14_15:2;
		uint64_t iop:13;
		uint64_t reserved_29_31:3;
		uint64_t iop_ie:13;
		uint64_t reserved_45_63:19;
#endif
	} s;
	struct cvmx_pow_ecc_err_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_14_63:50;
		uint64_t rpe_ie:1;
		uint64_t rpe:1;
		uint64_t reserved_9_11:3;
		uint64_t syn:5;
		uint64_t dbe_ie:1;
		uint64_t sbe_ie:1;
		uint64_t dbe:1;
		uint64_t sbe:1;
#else
		uint64_t sbe:1;
		uint64_t dbe:1;
		uint64_t sbe_ie:1;
		uint64_t dbe_ie:1;
		uint64_t syn:5;
		uint64_t reserved_9_11:3;
		uint64_t rpe:1;
		uint64_t rpe_ie:1;
		uint64_t reserved_14_63:50;
#endif
	} cn31xx;
};

union cvmx_pow_int_ctl {
	uint64_t u64;
	struct cvmx_pow_int_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_6_63:58;
		uint64_t pfr_dis:1;
		uint64_t nbr_thr:5;
#else
		uint64_t nbr_thr:5;
		uint64_t pfr_dis:1;
		uint64_t reserved_6_63:58;
#endif
	} s;
};

union cvmx_pow_iq_cntx {
	uint64_t u64;
	struct cvmx_pow_iq_cntx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t iq_cnt:32;
#else
		uint64_t iq_cnt:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_iq_com_cnt {
	uint64_t u64;
	struct cvmx_pow_iq_com_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t iq_cnt:32;
#else
		uint64_t iq_cnt:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_iq_int {
	uint64_t u64;
	struct cvmx_pow_iq_int_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_8_63:56;
		uint64_t iq_int:8;
#else
		uint64_t iq_int:8;
		uint64_t reserved_8_63:56;
#endif
	} s;
};

union cvmx_pow_iq_int_en {
	uint64_t u64;
	struct cvmx_pow_iq_int_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_8_63:56;
		uint64_t int_en:8;
#else
		uint64_t int_en:8;
		uint64_t reserved_8_63:56;
#endif
	} s;
};

union cvmx_pow_iq_thrx {
	uint64_t u64;
	struct cvmx_pow_iq_thrx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t iq_thr:32;
#else
		uint64_t iq_thr:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_nos_cnt {
	uint64_t u64;
	struct cvmx_pow_nos_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_12_63:52;
		uint64_t nos_cnt:12;
#else
		uint64_t nos_cnt:12;
		uint64_t reserved_12_63:52;
#endif
	} s;
	struct cvmx_pow_nos_cnt_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t nos_cnt:7;
#else
		uint64_t nos_cnt:7;
		uint64_t reserved_7_63:57;
#endif
	} cn30xx;
	struct cvmx_pow_nos_cnt_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_9_63:55;
		uint64_t nos_cnt:9;
#else
		uint64_t nos_cnt:9;
		uint64_t reserved_9_63:55;
#endif
	} cn31xx;
	struct cvmx_pow_nos_cnt_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_10_63:54;
		uint64_t nos_cnt:10;
#else
		uint64_t nos_cnt:10;
		uint64_t reserved_10_63:54;
#endif
	} cn52xx;
	struct cvmx_pow_nos_cnt_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_11_63:53;
		uint64_t nos_cnt:11;
#else
		uint64_t nos_cnt:11;
		uint64_t reserved_11_63:53;
#endif
	} cn63xx;
};

union cvmx_pow_nw_tim {
	uint64_t u64;
	struct cvmx_pow_nw_tim_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_10_63:54;
		uint64_t nw_tim:10;
#else
		uint64_t nw_tim:10;
		uint64_t reserved_10_63:54;
#endif
	} s;
};

union cvmx_pow_pf_rst_msk {
	uint64_t u64;
	struct cvmx_pow_pf_rst_msk_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_8_63:56;
		uint64_t rst_msk:8;
#else
		uint64_t rst_msk:8;
		uint64_t reserved_8_63:56;
#endif
	} s;
};

union cvmx_pow_pp_grp_mskx {
	uint64_t u64;
	struct cvmx_pow_pp_grp_mskx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_48_63:16;
		uint64_t qos7_pri:4;
		uint64_t qos6_pri:4;
		uint64_t qos5_pri:4;
		uint64_t qos4_pri:4;
		uint64_t qos3_pri:4;
		uint64_t qos2_pri:4;
		uint64_t qos1_pri:4;
		uint64_t qos0_pri:4;
		uint64_t grp_msk:16;
#else
		uint64_t grp_msk:16;
		uint64_t qos0_pri:4;
		uint64_t qos1_pri:4;
		uint64_t qos2_pri:4;
		uint64_t qos3_pri:4;
		uint64_t qos4_pri:4;
		uint64_t qos5_pri:4;
		uint64_t qos6_pri:4;
		uint64_t qos7_pri:4;
		uint64_t reserved_48_63:16;
#endif
	} s;
	struct cvmx_pow_pp_grp_mskx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t grp_msk:16;
#else
		uint64_t grp_msk:16;
		uint64_t reserved_16_63:48;
#endif
	} cn30xx;
};

union cvmx_pow_qos_rndx {
	uint64_t u64;
	struct cvmx_pow_qos_rndx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t rnd_p3:8;
		uint64_t rnd_p2:8;
		uint64_t rnd_p1:8;
		uint64_t rnd:8;
#else
		uint64_t rnd:8;
		uint64_t rnd_p1:8;
		uint64_t rnd_p2:8;
		uint64_t rnd_p3:8;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_qos_thrx {
	uint64_t u64;
	struct cvmx_pow_qos_thrx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_60_63:4;
		uint64_t des_cnt:12;
		uint64_t buf_cnt:12;
		uint64_t free_cnt:12;
		uint64_t reserved_23_23:1;
		uint64_t max_thr:11;
		uint64_t reserved_11_11:1;
		uint64_t min_thr:11;
#else
		uint64_t min_thr:11;
		uint64_t reserved_11_11:1;
		uint64_t max_thr:11;
		uint64_t reserved_23_23:1;
		uint64_t free_cnt:12;
		uint64_t buf_cnt:12;
		uint64_t des_cnt:12;
		uint64_t reserved_60_63:4;
#endif
	} s;
	struct cvmx_pow_qos_thrx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_55_63:9;
		uint64_t des_cnt:7;
		uint64_t reserved_43_47:5;
		uint64_t buf_cnt:7;
		uint64_t reserved_31_35:5;
		uint64_t free_cnt:7;
		uint64_t reserved_18_23:6;
		uint64_t max_thr:6;
		uint64_t reserved_6_11:6;
		uint64_t min_thr:6;
#else
		uint64_t min_thr:6;
		uint64_t reserved_6_11:6;
		uint64_t max_thr:6;
		uint64_t reserved_18_23:6;
		uint64_t free_cnt:7;
		uint64_t reserved_31_35:5;
		uint64_t buf_cnt:7;
		uint64_t reserved_43_47:5;
		uint64_t des_cnt:7;
		uint64_t reserved_55_63:9;
#endif
	} cn30xx;
	struct cvmx_pow_qos_thrx_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_57_63:7;
		uint64_t des_cnt:9;
		uint64_t reserved_45_47:3;
		uint64_t buf_cnt:9;
		uint64_t reserved_33_35:3;
		uint64_t free_cnt:9;
		uint64_t reserved_20_23:4;
		uint64_t max_thr:8;
		uint64_t reserved_8_11:4;
		uint64_t min_thr:8;
#else
		uint64_t min_thr:8;
		uint64_t reserved_8_11:4;
		uint64_t max_thr:8;
		uint64_t reserved_20_23:4;
		uint64_t free_cnt:9;
		uint64_t reserved_33_35:3;
		uint64_t buf_cnt:9;
		uint64_t reserved_45_47:3;
		uint64_t des_cnt:9;
		uint64_t reserved_57_63:7;
#endif
	} cn31xx;
	struct cvmx_pow_qos_thrx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_58_63:6;
		uint64_t des_cnt:10;
		uint64_t reserved_46_47:2;
		uint64_t buf_cnt:10;
		uint64_t reserved_34_35:2;
		uint64_t free_cnt:10;
		uint64_t reserved_21_23:3;
		uint64_t max_thr:9;
		uint64_t reserved_9_11:3;
		uint64_t min_thr:9;
#else
		uint64_t min_thr:9;
		uint64_t reserved_9_11:3;
		uint64_t max_thr:9;
		uint64_t reserved_21_23:3;
		uint64_t free_cnt:10;
		uint64_t reserved_34_35:2;
		uint64_t buf_cnt:10;
		uint64_t reserved_46_47:2;
		uint64_t des_cnt:10;
		uint64_t reserved_58_63:6;
#endif
	} cn52xx;
	struct cvmx_pow_qos_thrx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_59_63:5;
		uint64_t des_cnt:11;
		uint64_t reserved_47_47:1;
		uint64_t buf_cnt:11;
		uint64_t reserved_35_35:1;
		uint64_t free_cnt:11;
		uint64_t reserved_22_23:2;
		uint64_t max_thr:10;
		uint64_t reserved_10_11:2;
		uint64_t min_thr:10;
#else
		uint64_t min_thr:10;
		uint64_t reserved_10_11:2;
		uint64_t max_thr:10;
		uint64_t reserved_22_23:2;
		uint64_t free_cnt:11;
		uint64_t reserved_35_35:1;
		uint64_t buf_cnt:11;
		uint64_t reserved_47_47:1;
		uint64_t des_cnt:11;
		uint64_t reserved_59_63:5;
#endif
	} cn63xx;
};

union cvmx_pow_ts_pc {
	uint64_t u64;
	struct cvmx_pow_ts_pc_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t ts_pc:32;
#else
		uint64_t ts_pc:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_wa_com_pc {
	uint64_t u64;
	struct cvmx_pow_wa_com_pc_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t wa_pc:32;
#else
		uint64_t wa_pc:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_wa_pcx {
	uint64_t u64;
	struct cvmx_pow_wa_pcx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t wa_pc:32;
#else
		uint64_t wa_pc:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_wq_int {
	uint64_t u64;
	struct cvmx_pow_wq_int_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t iq_dis:16;
		uint64_t wq_int:16;
#else
		uint64_t wq_int:16;
		uint64_t iq_dis:16;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_pow_wq_int_cntx {
	uint64_t u64;
	struct cvmx_pow_wq_int_cntx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_28_63:36;
		uint64_t tc_cnt:4;
		uint64_t ds_cnt:12;
		uint64_t iq_cnt:12;
#else
		uint64_t iq_cnt:12;
		uint64_t ds_cnt:12;
		uint64_t tc_cnt:4;
		uint64_t reserved_28_63:36;
#endif
	} s;
	struct cvmx_pow_wq_int_cntx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_28_63:36;
		uint64_t tc_cnt:4;
		uint64_t reserved_19_23:5;
		uint64_t ds_cnt:7;
		uint64_t reserved_7_11:5;
		uint64_t iq_cnt:7;
#else
		uint64_t iq_cnt:7;
		uint64_t reserved_7_11:5;
		uint64_t ds_cnt:7;
		uint64_t reserved_19_23:5;
		uint64_t tc_cnt:4;
		uint64_t reserved_28_63:36;
#endif
	} cn30xx;
	struct cvmx_pow_wq_int_cntx_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_28_63:36;
		uint64_t tc_cnt:4;
		uint64_t reserved_21_23:3;
		uint64_t ds_cnt:9;
		uint64_t reserved_9_11:3;
		uint64_t iq_cnt:9;
#else
		uint64_t iq_cnt:9;
		uint64_t reserved_9_11:3;
		uint64_t ds_cnt:9;
		uint64_t reserved_21_23:3;
		uint64_t tc_cnt:4;
		uint64_t reserved_28_63:36;
#endif
	} cn31xx;
	struct cvmx_pow_wq_int_cntx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_28_63:36;
		uint64_t tc_cnt:4;
		uint64_t reserved_22_23:2;
		uint64_t ds_cnt:10;
		uint64_t reserved_10_11:2;
		uint64_t iq_cnt:10;
#else
		uint64_t iq_cnt:10;
		uint64_t reserved_10_11:2;
		uint64_t ds_cnt:10;
		uint64_t reserved_22_23:2;
		uint64_t tc_cnt:4;
		uint64_t reserved_28_63:36;
#endif
	} cn52xx;
	struct cvmx_pow_wq_int_cntx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_28_63:36;
		uint64_t tc_cnt:4;
		uint64_t reserved_23_23:1;
		uint64_t ds_cnt:11;
		uint64_t reserved_11_11:1;
		uint64_t iq_cnt:11;
#else
		uint64_t iq_cnt:11;
		uint64_t reserved_11_11:1;
		uint64_t ds_cnt:11;
		uint64_t reserved_23_23:1;
		uint64_t tc_cnt:4;
		uint64_t reserved_28_63:36;
#endif
	} cn63xx;
};

union cvmx_pow_wq_int_pc {
	uint64_t u64;
	struct cvmx_pow_wq_int_pc_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_60_63:4;
		uint64_t pc:28;
		uint64_t reserved_28_31:4;
		uint64_t pc_thr:20;
		uint64_t reserved_0_7:8;
#else
		uint64_t reserved_0_7:8;
		uint64_t pc_thr:20;
		uint64_t reserved_28_31:4;
		uint64_t pc:28;
		uint64_t reserved_60_63:4;
#endif
	} s;
};

union cvmx_pow_wq_int_thrx {
	uint64_t u64;
	struct cvmx_pow_wq_int_thrx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_29_63:35;
		uint64_t tc_en:1;
		uint64_t tc_thr:4;
		uint64_t reserved_23_23:1;
		uint64_t ds_thr:11;
		uint64_t reserved_11_11:1;
		uint64_t iq_thr:11;
#else
		uint64_t iq_thr:11;
		uint64_t reserved_11_11:1;
		uint64_t ds_thr:11;
		uint64_t reserved_23_23:1;
		uint64_t tc_thr:4;
		uint64_t tc_en:1;
		uint64_t reserved_29_63:35;
#endif
	} s;
	struct cvmx_pow_wq_int_thrx_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_29_63:35;
		uint64_t tc_en:1;
		uint64_t tc_thr:4;
		uint64_t reserved_18_23:6;
		uint64_t ds_thr:6;
		uint64_t reserved_6_11:6;
		uint64_t iq_thr:6;
#else
		uint64_t iq_thr:6;
		uint64_t reserved_6_11:6;
		uint64_t ds_thr:6;
		uint64_t reserved_18_23:6;
		uint64_t tc_thr:4;
		uint64_t tc_en:1;
		uint64_t reserved_29_63:35;
#endif
	} cn30xx;
	struct cvmx_pow_wq_int_thrx_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_29_63:35;
		uint64_t tc_en:1;
		uint64_t tc_thr:4;
		uint64_t reserved_20_23:4;
		uint64_t ds_thr:8;
		uint64_t reserved_8_11:4;
		uint64_t iq_thr:8;
#else
		uint64_t iq_thr:8;
		uint64_t reserved_8_11:4;
		uint64_t ds_thr:8;
		uint64_t reserved_20_23:4;
		uint64_t tc_thr:4;
		uint64_t tc_en:1;
		uint64_t reserved_29_63:35;
#endif
	} cn31xx;
	struct cvmx_pow_wq_int_thrx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_29_63:35;
		uint64_t tc_en:1;
		uint64_t tc_thr:4;
		uint64_t reserved_21_23:3;
		uint64_t ds_thr:9;
		uint64_t reserved_9_11:3;
		uint64_t iq_thr:9;
#else
		uint64_t iq_thr:9;
		uint64_t reserved_9_11:3;
		uint64_t ds_thr:9;
		uint64_t reserved_21_23:3;
		uint64_t tc_thr:4;
		uint64_t tc_en:1;
		uint64_t reserved_29_63:35;
#endif
	} cn52xx;
	struct cvmx_pow_wq_int_thrx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_29_63:35;
		uint64_t tc_en:1;
		uint64_t tc_thr:4;
		uint64_t reserved_22_23:2;
		uint64_t ds_thr:10;
		uint64_t reserved_10_11:2;
		uint64_t iq_thr:10;
#else
		uint64_t iq_thr:10;
		uint64_t reserved_10_11:2;
		uint64_t ds_thr:10;
		uint64_t reserved_22_23:2;
		uint64_t tc_thr:4;
		uint64_t tc_en:1;
		uint64_t reserved_29_63:35;
#endif
	} cn63xx;
};

union cvmx_pow_ws_pcx {
	uint64_t u64;
	struct cvmx_pow_ws_pcx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t ws_pc:32;
#else
		uint64_t ws_pc:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_sso_wq_int_thrx {
	uint64_t u64;
	struct {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_33_63:31;
		uint64_t tc_en:1;
		uint64_t tc_thr:4;
		uint64_t reserved_26_27:2;
		uint64_t ds_thr:12;
		uint64_t reserved_12_13:2;
		uint64_t iq_thr:12;
#else
		uint64_t iq_thr:12;
		uint64_t reserved_12_13:2;
		uint64_t ds_thr:12;
		uint64_t reserved_26_27:2;
		uint64_t tc_thr:4;
		uint64_t tc_en:1;
		uint64_t reserved_33_63:31;
#endif
	} s;
};

#endif