diff options
| author | Chanh Nguyen <chanh@os.amperecomputing.com> | 2021-03-10 06:18:49 +0300 |
|---|---|---|
| committer | Thang Q. Nguyen <thang@os.amperecomputing.com> | 2021-03-10 08:19:26 +0300 |
| commit | d86e51f28ccc85de4dfd75299282e0d7e57d5b22 (patch) | |
| tree | 8167deec744c24c24c913e29f500935d39526755 /meta-ampere | |
| parent | 53b6d9969b2f2be1f462cd454d6e32d07715a9cf (diff) | |
| download | openbmc-d86e51f28ccc85de4dfd75299282e0d7e57d5b22.tar.xz | |
meta-ampere:u-boot: Enable SPI master mode by default
The Mt.Jade board designs pin strap, which is shared with an OCP pin.
This causes the pin strap to have the wrong value if the OCP adapter
is plugged and the system is off which consequently disables the SPI
master mode. This makes OpenBMC fail to probe the Host SPI Flash.
Change to set SPI master mode enabled by default, not base on the
pin strap value, so Host SPI NOR can always be probed.
Tested:
1. Plug Mellanox OCP card into the OCP1 header.
2. Do AC power board and check if SPI Flash driver
can probe without error like
"aspeed-smc 1e630000.spi: Error applying setting, reverse things back"
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Change-Id: Ie36557d8e1580f8a6b59b24ac47557d59af653c5
Diffstat (limited to 'meta-ampere')
| -rw-r--r-- | meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch | 33 | ||||
| -rw-r--r-- | meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend | 1 |
2 files changed, 34 insertions, 0 deletions
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch new file mode 100644 index 000000000..0dd736fba --- /dev/null +++ b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch @@ -0,0 +1,33 @@ +From 0bf84de2a9db749bd61064cd47b96ef457725f54 Mon Sep 17 00:00:00 2001 +From: Chanh Nguyen <chanh@os.amperecomputing.com> +Date: Wed, 10 Mar 2021 00:02:17 +0700 +Subject: [PATCH] aspeed: Enable SPI master mode + +Currently, some systems design the strap pin, +which was shared pin with another function. +That makes the board strapping does not reflect the intended use of the system. + +This patch will enable SPI master mode by default. + +Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> +--- + board/aspeed/ast-g5/ast-g5.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index 9e27bce0f5..ed83d65136 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -125,6 +125,9 @@ int board_late_init(void) + update_bootargs_cmd("resetreason", value); + } + ++ /* enable SPI master */ ++ ast_scu_spi_master(1); ++ + return 0; + } + #endif +-- +2.17.1 + diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index 4f882dcee..0febf924d 100644 --- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -5,4 +5,5 @@ SRC_URI += " \ file://0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch \ file://0003-aspeed-support-passing-system-reset-status-to-kernel.patch \ file://0004-aspeed-add-gpio-support.patch \ + file://0005-aspeed-Enable-SPI-master-mode.patch \ " |