Update to internal 0.26

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

9 files changed, 296 insertions, 65 deletions

diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch
index 3a15830f7..4e6ebb5ad 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch
@@ -1,24 +1,24 @@
-From 538ebb0466d1063963e0d3a489b98c5fb8b62fb2 Mon Sep 17 00:00:00 2001
+From 122fa6153479d026a06c27512f3c7024a1515c63 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Fri, 3 Jan 2020 15:14:09 -0800
 Subject: [PATCH] AST2600: Adjust default GPIO settings
 
 - Disabled GPIOC3 to prevent unexpected host failures.
-- Fixed GPIOC5, GPIOG6, GPIOI0~7 and GPIOL6~7 directions and
+- Fixed GPIOC5, GPIOD4, GPIOG6, GPIOI0~7 and GPIOL6~7 directions and
   default values.
 - Disabled internal pull-down of GPIOB6.
 - Disabled HBLED.
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- board/aspeed/ast2600_intel/intel.c | 55 ++++++++++++++++++++++++++++++
- 1 file changed, 55 insertions(+)
+ board/aspeed/ast2600_intel/intel.c | 65 ++++++++++++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
 
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index d1ac8651ac6c..fc4745a11585 100644
+index d1ac8651ac6c..7c9e78f8c005 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
-@@ -162,6 +162,59 @@ static void sgpio_init(void)
+@@ -162,6 +162,69 @@ static void sgpio_init(void)
  	       SCU_BASE | SCU_414);
  }
  
@@ -69,6 +69,16 @@ index d1ac8651ac6c..fc4745a11585 100644
 +	writel(readl(AST_GPIO_BASE | GPIO_004) & ~GPIO_C5,
 +	       AST_GPIO_BASE | GPIO_004);
 +
++	/*
++	 * Set GPIOD4 as an output with value low explicitly to set the
++	 * default SPD mux path to CPU and DIMMs.
++	 */
++#define GPIO_D4			BIT(28)
++	writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_D4,
++	       AST_GPIO_BASE | GPIO_004);
++	writel(readl(AST_GPIO_BASE | GPIO_000) & ~GPIO_D4,
++	       AST_GPIO_BASE | GPIO_000);
++
 +	/* GPIO G6 is also an open-drain output so set it as an input. */
 +#define GPIO_G6			BIT(22)
 +	writel(readl(AST_GPIO_BASE | GPIO_024) & ~GPIO_G6,
@@ -78,7 +88,7 @@ index d1ac8651ac6c..fc4745a11585 100644
  static void timer_handler(void *regs)
  {
  	printf("+");
-@@ -175,6 +228,8 @@ int board_early_init_f(void)
+@@ -175,6 +238,8 @@ int board_early_init_f(void)
  	 * I am not sure if it actually does anything... */
  	arch_interrupt_init_early();
  
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch
index 34d8b1abb..720d165c5 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch
@@ -1,4 +1,4 @@
-From c438edace30a3408c827faaae2d5004fe5ae010d Mon Sep 17 00:00:00 2001
+From fd0768e6a63a25fdc87596036a5cbf82a88a1eb6 Mon Sep 17 00:00:00 2001
 From: arun-pm <arun.p.m@linux.intel.com>
 Date: Fri, 29 Nov 2019 00:19:09 +0530
 Subject: [PATCH] SPI Quad IO Mode
@@ -12,13 +12,12 @@ Note:- Removed n25q00 Quad I/O support for the time being due to clock issue
  drivers/mtd/spi/spi-nor-ids.c  |  7 ++++++-
  drivers/spi/aspeed_spi.c       | 18 +++++++++++++++++-
  3 files changed, 25 insertions(+), 6 deletions(-)
- mode change 100755 => 100644 drivers/spi/aspeed_spi.c
 
 diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts
-index d16581c5811d..ab78b516b6a3 100644
+index 9a15e204f83b..1f14753056ee 100644
 --- a/arch/arm/dts/ast2600-intel.dts
 +++ b/arch/arm/dts/ast2600-intel.dts
-@@ -101,16 +101,14 @@
+@@ -120,16 +120,14 @@
  
  &fmc {
  	status = "okay";
@@ -38,7 +37,7 @@ index d16581c5811d..ab78b516b6a3 100644
  };
  
 diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
-index ad733e71988b..257ab472305c 100644
+index 3b0a910d3fca..d6b949170570 100644
 --- a/drivers/mtd/spi/spi-nor-ids.c
 +++ b/drivers/mtd/spi/spi-nor-ids.c
 @@ -164,7 +164,12 @@ const struct flash_info spi_nor_ids[] = {
@@ -56,22 +55,20 @@ index ad733e71988b..257ab472305c 100644
  	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
  #endif
 diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c
-old mode 100755
-new mode 100644
-index c7b998fadfde..930b18443a48
+index 18d4c2fa098e..6efb8c4e3c65 100644
 --- a/drivers/spi/aspeed_spi.c
 +++ b/drivers/spi/aspeed_spi.c
-@@ -16,6 +16,9 @@
- #include <linux/ioport.h>
+@@ -17,6 +17,9 @@
  
  #define ASPEED_SPI_MAX_CS		3
+ #define FLASH_CALIBRATION_LEN   0x400
 +#define AST2600A0		0x05000303
 +#define AST2600A0_MAX_FREQ	40000000
 +#define AST_MAX_FREQ		100000000
  
  struct aspeed_spi_regs {
  	u32 conf;			/* 0x00 CE Type Setting */
-@@ -1011,6 +1014,19 @@ static int aspeed_spi_bind(struct udevice *bus)
+@@ -1037,6 +1040,19 @@ static int aspeed_spi_bind(struct udevice *bus)
  	return 0;
  }
  
@@ -91,7 +88,7 @@ index c7b998fadfde..930b18443a48
  static int aspeed_spi_probe(struct udevice *bus)
  {
  	struct resource res_regs, res_ahb;
-@@ -1041,7 +1057,7 @@ static int aspeed_spi_probe(struct udevice *bus)
+@@ -1067,7 +1083,7 @@ static int aspeed_spi_probe(struct udevice *bus)
  	clk_free(&hclk);
  
  	priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
@@ -101,5 +98,5 @@ index c7b998fadfde..930b18443a48
  	priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS);
  
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
index e8ffb4e72..2a2d1054a 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
@@ -1,4 +1,4 @@
-From ddf356e738ab147775bf49a3a4fae179c0dde9ef Mon Sep 17 00:00:00 2001
+From 6f9d529b616ce84271ccd2584b9bcd8d13ab57de Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 29 Jan 2020 14:55:44 -0800
 Subject: [PATCH] ast2600: Override OTP strap settings
@@ -8,24 +8,24 @@ Also, this commit disables SoC debug interface.
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- arch/arm/mach-aspeed/ast2600/platform.S | 26 +++++++++++++++++++++++---
+ arch/arm/mach-aspeed/ast2600/platform.S | 26 ++++++++++++++++++++++---
  1 file changed, 23 insertions(+), 3 deletions(-)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index d107ed80a835..eb3cb2f38cb6 100644
+index f193c66cd04b..997670b66bdc 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -45,7 +45,9 @@
+@@ -44,7 +44,9 @@
+ #define AST_SCU_HPLL_PARAM		(AST_SCU_BASE + 0x200)
  #define AST_SCU_HPLL_PARAM_EXT		(AST_SCU_BASE + 0x204)
- #define AST_SCU_MFP_CTRL15		(AST_SCU_BASE + 0x454)
  #define AST_SCU_HW_STRAP1		(AST_SCU_BASE + 0x500)
 +#define AST_SCU_HW_STRAP1_CLR		(AST_SCU_BASE + 0x504)
  #define AST_SCU_HW_STRAP2		(AST_SCU_BASE + 0x510)
 +#define AST_SCU_HW_STRAP2_CLR		(AST_SCU_BASE + 0x514)
- #define AST_SCU_CA7_CTRL		(AST_SCU_BASE + 0x800)
- #define AST_SCU_CA7_AXI_PREFETCH_START	(AST_SCU_BASE + 0x808)
- #define AST_SCU_CA7_AXI_PREFETCH_END	(AST_SCU_BASE + 0x80C)
-@@ -146,6 +148,26 @@ do_primary_core_setup:
+ #define AST_SCU_CA7_PARITY_CHK		(AST_SCU_BASE + 0x820)
+ #define AST_SCU_CA7_PARITY_CLR		(AST_SCU_BASE + 0x824)
+ #define AST_SCU_MMIO_DEC_SET		(AST_SCU_BASE + 0xC24)
+@@ -173,6 +175,26 @@ do_primary_core_setup:
  	/* unlock system control unit */
  	scu_unlock
  
@@ -52,8 +52,8 @@ index d107ed80a835..eb3cb2f38cb6 100644
  	/* identify AST2600 A0/A1 */
  	ldr	r0, =AST_SCU_REV_ID
  	ldr	r0, [r0]
-@@ -241,19 +263,17 @@ wait_lock:
- 	ldr	r1, =AST_FMC_CE0_CTRL
+@@ -262,19 +284,17 @@ skip_fill_wip_bit:
+ 	ldr	r1, =AST_FMC_WDT1_CTRL_MODE
  	str	r0, [r1]
  
 -#if 0
@@ -71,8 +71,8 @@ index d107ed80a835..eb3cb2f38cb6 100644
  	str     r1, [r0]
 -#endif
  
- 	/* Strongest LADESPID Driving Strngth */
- 	ldr	r0, =AST_SCU_MFP_CTRL15
+ 	/* relocate mailbox insn. for cpuN polling SMP go signal */
+ 	adrl	r0, mailbox_insn
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch
index 259afc619..f47092eaa 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch
@@ -1,4 +1,4 @@
-From 363cb4a59bd21708465ad46553a098615abea1dd Mon Sep 17 00:00:00 2001
+From f1bfa10fefa992c7032e0c32647543bb2a8dc90f Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Tue, 31 Mar 2020 13:28:31 -0700
 Subject: [PATCH] AST2600: Disable DMA arbitration options on MAC1 and MAC2
@@ -17,10 +17,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 18 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index eb3cb2f38cb6..0316e5364b78 100644
+index 997670b66bdc..6b447845fe26 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -60,6 +60,12 @@
+@@ -57,6 +57,12 @@
  #define AST_FMC_WDT1_CTRL_MODE	(AST_FMC_BASE + 0x060)
  #define AST_FMC_WDT2_CTRL_MODE	(AST_FMC_BASE + 0x064)
  
@@ -33,10 +33,10 @@ index eb3cb2f38cb6..0316e5364b78 100644
  #define AST_GPIO_BASE		(0x1E780000)
  #define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
  
-@@ -228,6 +234,18 @@ wait_lock:
- 	orr	r1, #0x40
- 	str	r1, [r0]
+@@ -229,6 +235,18 @@ wait_lock:
+ 	b 1f
  
+ 0:
 +	/* disable DMA arbitration on MAC1 (A1 bug) */
 +	ldr	r0, =AST_MAC1_CTRL2
 +	ldr	r1, [r0]
@@ -49,9 +49,9 @@ index eb3cb2f38cb6..0316e5364b78 100644
 +	orr	r1, #0x18000000
 +	str	r1, [r0]
 +
- 1:
- 	/* release display port reset */
- 	ldr	r0, =AST_SCU_SYSRST_CTRL_CLR
+ 	/* LPC/eSPI mode selection (A1 only) */
+ 	ldr	r0, =AST_GPIOYZ_DATA_VALUE
+ 	ldr	r0, [r0]
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch
index 2ae8978e6..da69791ea 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch
@@ -1,4 +1,4 @@
-From 28f797376ec5d9bf62a12a6c91686588cf73d09a Mon Sep 17 00:00:00 2001
+From 1333a1ff082cbaec4a44cefaf84d1bcc03ba1510 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Thu, 18 Jun 2020 15:08:57 -0700
 Subject: [PATCH] Add a workaround to cover VGA memory size bug in A0
@@ -13,10 +13,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 17 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index 0316e5364b78..d881ba8565f2 100644
+index 6b447845fe26..55b867ff1b17 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -183,6 +183,12 @@ do_primary_core_setup:
+@@ -210,6 +210,12 @@ do_primary_core_setup:
  
  	bne	0f
  
@@ -29,10 +29,10 @@ index 0316e5364b78..d881ba8565f2 100644
  	/* tune up CPU clocks (A0 only) */
  	ldr	r0, =AST_SCU_HW_STRAP1
  	ldr	r1, [r0]
-@@ -234,6 +240,17 @@ wait_lock:
- 	orr	r1, #0x40
- 	str	r1, [r0]
+@@ -235,6 +241,17 @@ wait_lock:
+ 	b 1f
  
+ 0:
 +	/* set VGA memory size to 16MB (A1 only) */
 +	ldr	r0, =AST_SCU_HW_STRAP1_CLR
 +	movw	r1, #0x4000
@@ -48,5 +48,5 @@ index 0316e5364b78..d881ba8565f2 100644
  	ldr	r0, =AST_MAC1_CTRL2
  	ldr	r1, [r0]
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch
index e7af35ff8..ea7650f8b 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch
@@ -1,4 +1,4 @@
-From fa401cd64965d506ddeb94fd47eb694a8f2a3862 Mon Sep 17 00:00:00 2001
+From a56e138569ce7b37285d4c2f2b4ef4082ab2a283 Mon Sep 17 00:00:00 2001
 From: Suryakanth Sekar <suryakanth.sekar@linux.intel.com>
 Date: Thu, 18 Jun 2020 05:32:48 +0530
 Subject: [PATCH] Apply WDT1-2 reset mask to reset needed controller
@@ -20,8 +20,12 @@ De-coupling LPC controller will make sure BIOS serial port access
 is not disturbed.
 And also Reset mask is updated not to reset the following
 additionally on the default mask setting.
+eSPI controller reset causes system console lost connection, when
+BMC reset.
+
 1. LPC controller
 2. PWM controller
+3. eSPI controller
 
 Quick Step to reproduce:
  Stop the BMC in uboot and add below bootcmd command
@@ -51,15 +55,16 @@ Tested:
 
 Signed-off-by: Suryakanth Sekar <suryakanth.sekar@linux.intel.com>
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
+Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 ---
- arch/arm/mach-aspeed/ast2600/platform.S | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
+ arch/arm/mach-aspeed/ast2600/platform.S | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index d881ba8565f2..c77640138653 100644
+index 55b867ff1b17..cd8a57edd76b 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -66,6 +66,14 @@
+@@ -63,6 +63,14 @@
  #define AST_MAC2_BASE		(0x1E680000)
  #define AST_MAC2_CTRL2		(AST_MAC2_BASE + 0x058)
  
@@ -74,25 +79,27 @@ index d881ba8565f2..c77640138653 100644
  #define AST_GPIO_BASE		(0x1E780000)
  #define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
  
-@@ -264,6 +272,18 @@ wait_lock:
+@@ -277,6 +285,20 @@ wait_lock:
  	str	r1, [r0]
  
  1:
-+	/* disable LPC and PWM resets on WDT1 reset */
++	/* disable eSPI, LPC and PWM resets on WDT1 reset */
 +	ldr	r0, =AST_WDT1_RESET_MASK2
 +	ldr	r1, [r0]
-+	bic	r1, #0x2800
++	ldr	r2, =0x04002800
++	bic	r1, r2
 +	str	r1, [r0]
 +
-+	/* disable LPC and PWM resets on WDT2 reset */
++	/* disable eSPI, LPC and PWM resets on WDT2 reset */
 +	ldr	r0, =AST_WDT2_RESET_MASK2
 +	ldr	r1, [r0]
-+	bic	r1, #0x2800
++	ldr	r2, =0x04002800
++	bic	r1, r2
 +	str	r1, [r0]
 +
- 	/* release display port reset */
- 	ldr	r0, =AST_SCU_SYSRST_CTRL_CLR
- 	movw	r1, #0x0000
+ 	/* MMIO decode setting */
+ 	ldr	r0, =AST_SCU_MMIO_DEC_SET
+ 	mov	r1, #0x2000
 -- 
 2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch
new file mode 100644
index 000000000..d5093bba6
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch
@@ -0,0 +1,88 @@
+From c4aebdd00365539dc155e88ee4f6b88cccdccd8f Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Wed, 16 Sep 2020 13:25:36 -0700
+Subject: [PATCH] Add WDT to u-boot to cover booting failures
+
+This commit enables WDT2 before loading kernel image to make BMC
+reset to cover booting failures. If BMC meet any failure or if
+systemd can't initiate watchdog timer service properly, BMC will
+be reset by this watchdog. In case if u-boot meets a kernel image
+decoding issue, this watchdog will be immediately disabled and BMC
+will stay in u-boot console.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/intel.c | 23 ++++++++++++++++++++++-
+ common/bootm_os.c                  | 11 +++++++++++
+ 2 files changed, 33 insertions(+), 1 deletion(-)
+
+diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
+index 807202295757..af2af9786926 100644
+--- a/board/aspeed/ast2600_intel/intel.c
++++ b/board/aspeed/ast2600_intel/intel.c
+@@ -474,12 +474,33 @@ void board_init(void)
+ */
+ 
+ #ifdef CONFIG_WATCHDOG
+-/* watchdog stuff */
++#define WDT2_BASE			0x1e785040
++#define WDT_COUNTER_STATUS		0x00
++#define WDT_COUNTER_RELOAD_VALUE	0x04
++#define WDT_COUNTER_RESTART_CTRL	0x08
++#define  WDT_RESTART_VALUE		0x4755
++#define WDT_CTRL			0x0c
++#define  WDT_RST_BY_SOC_RST		BIT(4)
++#define  WDT_SYS_RESET			BIT(1)
++#define  WDT_ENABLE			BIT(0)
++#define WDT_TIMEOUT_DEFAULT		0x6000000 /* ~100 seconds */
++
+ void watchdog_init(void)
+ {
++	writel(0, WDT2_BASE + WDT_CTRL);
++	writel(WDT_TIMEOUT_DEFAULT, WDT2_BASE + WDT_COUNTER_RELOAD_VALUE);
++	writel(WDT_RESTART_VALUE, WDT2_BASE + WDT_COUNTER_RESTART_CTRL);
++	writel(WDT_RST_BY_SOC_RST | WDT_SYS_RESET | WDT_ENABLE,
++	       WDT2_BASE + WDT_CTRL);
+ }
+ 
+ void watchdog_reset(void)
+ {
++	writel(WDT_RESTART_VALUE, WDT2_BASE + WDT_COUNTER_RESTART_CTRL);
++}
++
++void watchdog_disable(void)
++{
++	writel(0, WDT2_BASE + WDT_CTRL);
+ }
+ #endif
+diff --git a/common/bootm_os.c b/common/bootm_os.c
+index 855c471c28e6..05836e76c8e8 100644
+--- a/common/bootm_os.c
++++ b/common/bootm_os.c
+@@ -511,12 +511,23 @@ __weak void board_preboot_os(void)
+ 	/* please define board specific board_preboot_os() */
+ }
+ 
++#ifdef CONFIG_WATCHDOG
++extern void watchdog_init(void);
++extern void watchdog_disable(void);
++#endif
++
+ int boot_selected_os(int argc, char * const argv[], int state,
+ 		     bootm_headers_t *images, boot_os_fn *boot_fn)
+ {
+ 	arch_preboot_os();
+ 	board_preboot_os();
++#ifdef CONFIG_WATCHDOG
++	watchdog_init();
++#endif
+ 	boot_fn(state, argc, argv, images);
++#ifdef CONFIG_WATCHDOG
++	watchdog_disable();
++#endif
+ 
+ 	/* Stand-alone may return when 'autostart' is 'no' */
+ 	if (images->os.type == IH_TYPE_STANDALONE ||
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0024-fix-SUS_WARN-handling-logic.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0024-fix-SUS_WARN-handling-logic.patch
new file mode 100644
index 000000000..e8562a184
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0024-fix-SUS_WARN-handling-logic.patch
@@ -0,0 +1,128 @@
+From e9a8a79453e23c86e7b086b1e752876c99bcf0b3 Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
+Date: Tue, 20 Oct 2020 15:49:26 -0700
+Subject: [PATCH] fix SUS_WARN handling logic
+
+This commit fixes SUS_WARN handling as dual-edge detection mode
+to support deepsx entry event properly.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
+---
+ board/aspeed/ast2600_intel/ast-espi.c | 62 ++++++++++++++-------------
+ 1 file changed, 32 insertions(+), 30 deletions(-)
+
+diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c
+index a8b389f159ef..51fcc836cc6a 100644
+--- a/board/aspeed/ast2600_intel/ast-espi.c
++++ b/board/aspeed/ast2600_intel/ast-espi.c
+@@ -148,9 +148,9 @@ static void espi_irq_handler(void *cookie)
+ {
+ 	uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008);
+ 
+-	DBG_ESPI("espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x,\
+-		ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x,\
+-		ESPI12c=0X%x, irq_status=0x%x\n",
++	DBG_ESPI("espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x, "
++		 "ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x, "
++		 "ESPI12c=0X%x, irq_status=0x%x\n",
+ 		readl(AST_ESPI_BASE + ESPI008),
+ 		readl(AST_ESPI_BASE + ESPI00C),
+ 		readl(AST_ESPI_BASE + ESPI100),
+@@ -165,21 +165,23 @@ static void espi_irq_handler(void *cookie)
+ 		DBG_ESPI("sys_status : 0x%08X\n", sys_status);
+ 		if (sys_status & AST_ESPI_HOST_RST_WARN) {
+ 			DBG_ESPI("HOST_RST_WARN evt: 0x%08X\n", sys_event);
+-			if (sys_event & AST_ESPI_HOST_RST_WARN) {
+-				uint32_t v = readl(AST_ESPI_BASE + ESPI098) |
+-					     AST_ESPI_HOST_RST_ACK;
+-				writel(v, AST_ESPI_BASE + ESPI098);
+-				DBG_ESPI("HOST_RST_WARN sent ack\n");
+-			}
++			uint32_t v = readl(AST_ESPI_BASE + ESPI098);
++			if (sys_event & AST_ESPI_HOST_RST_WARN)
++				v |= AST_ESPI_HOST_RST_ACK;
++			else
++				v &= ~AST_ESPI_HOST_RST_ACK;
++			writel(v, AST_ESPI_BASE + ESPI098);
++			DBG_ESPI("HOST_RST_WARN sent ack\n");
+ 		}
+ 		if (sys_status & AST_ESPI_OOB_RST_WARN) {
+ 			DBG_ESPI("OOB_RST_WARN evt: 0x%08X\n", sys_event);
+-			if (sys_event & AST_ESPI_OOB_RST_WARN) {
+-				uint32_t v = readl(AST_ESPI_BASE + ESPI098) |
+-					     AST_ESPI_OOB_RST_ACK;
+-				writel(v, AST_ESPI_BASE + ESPI098);
+-				DBG_ESPI("OOB_RST_WARN sent ack\n");
+-			}
++			uint32_t v = readl(AST_ESPI_BASE + ESPI098);
++			if (sys_event & AST_ESPI_OOB_RST_WARN)
++				v |= AST_ESPI_OOB_RST_ACK;
++			else
++				v &= ~AST_ESPI_OOB_RST_ACK;
++			writel(v, AST_ESPI_BASE + ESPI098);
++			DBG_ESPI("OOB_RST_WARN sent ack\n");
+ 		}
+ 		if (sys_status & AST_ESPI_PLTRSTN) {
+ 			DBG_ESPI("PLTRSTN: %c, evt: 0x%08X\n",
+@@ -196,12 +198,13 @@ static void espi_irq_handler(void *cookie)
+ 		DBG_ESPI("sys1_status : 0x%08X\n", sys1_status);
+ 		if (sys1_status & AST_ESPI_SUS_WARN) {
+ 			DBG_ESPI("SUS WARN evt: 0x%08X\n", sys1_event);
+-			if (sys1_event & AST_ESPI_SUS_WARN) {
+-				uint32_t v = readl(AST_ESPI_BASE + ESPI104) |
+-					     AST_ESPI_SUS_ACK;
+-				writel(v, AST_ESPI_BASE + ESPI104);
+-				DBG_ESPI("SUS_WARN sent ack\n");
+-			}
++			uint32_t v = readl(AST_ESPI_BASE + ESPI104);
++			if (sys1_event & AST_ESPI_SUS_WARN)
++				v |= AST_ESPI_SUS_ACK;
++			else
++				v &= ~AST_ESPI_SUS_ACK;
++			writel(v, AST_ESPI_BASE + ESPI104);
++			DBG_ESPI("SUS_WARN sent ack\n");
+ 		}
+ 		writel(sys1_status, AST_ESPI_BASE + ESPI12C); /* clear status */
+ 	}
+@@ -219,9 +222,9 @@ static void espi_irq_handler(void *cookie)
+ 
+ 	writel(irq_status, AST_ESPI_BASE + ESPI008); /* clear irq_status */
+ 
+-	DBG_ESPI("end espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x,\
+-		ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x,\
+-		ESPI12c=0X%x, irq_status=0X%x\n",
++	DBG_ESPI("end espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x, "
++		 "ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x, "
++		 "ESPI12c=0X%x, irq_status=0X%x\n",
+ 		readl(AST_ESPI_BASE + ESPI008),
+ 		readl(AST_ESPI_BASE + ESPI00C),
+ 		readl(AST_ESPI_BASE + ESPI100),
+@@ -232,6 +235,7 @@ static void espi_irq_handler(void *cookie)
+ 
+ static void espi_configure_irq(void)
+ {
++	/* Dual-edge setting for HOST_RST_WARN and OOB_RST_WARN */
+ 	writel(0, AST_ESPI_BASE + ESPI110);
+ 	writel(0, AST_ESPI_BASE + ESPI114);
+ 	writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN |
+@@ -239,13 +243,11 @@ static void espi_configure_irq(void)
+ 	writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN |
+ 	       AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI094);
+ 
+-	writel(AST_ESPI_SUS_WARN,
+-	       AST_ESPI_BASE + ESPI120); /* int type 0 susp warn */
++	/* Dual-edge setting for SUS_WARN */
++	writel(0, AST_ESPI_BASE + ESPI120);
+ 	writel(0, AST_ESPI_BASE + ESPI124);
+-	writel(0, AST_ESPI_BASE + ESPI128);
+-	writel(AST_ESPI_SUS_WARN,
+-	       AST_ESPI_BASE +
+-			ESPI100); /* Enable sysev1 ints for susp warn */
++	writel(AST_ESPI_SUS_WARN, AST_ESPI_BASE + ESPI128);
++	writel(AST_ESPI_SUS_WARN, AST_ESPI_BASE + ESPI100);
+ 
+ 	writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV |
+ 	       AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C);
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
index d16227937..1ac02608b 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
@@ -21,9 +21,10 @@ CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=n
 CONFIG_CMD_MTDPARTS=n
 CONFIG_EFI_PARTITION=n
+CONFIG_EFI_LOADER=n
 CONFIG_USB=n
 CONFIG_DM_USB=n
 CONFIG_USB_EHCI_HCD=n
 CONFIG_USB_STORAGE=n
 CONFIG_NETCONSOLE=n
-CONFIG_CMD_NFS=n
\ No newline at end of file
+CONFIG_CMD_NFS=n