Update to internal 0.63

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

21 files changed, 929 insertions, 350 deletions

diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch
index 0705ab3de..d1ccc278a 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch
@@ -1,4 +1,4 @@
-From 041ad6cfc3d379c8e4fd271e7f9e3d8ea6ee61ac Mon Sep 17 00:00:00 2001
+From 45d1a40a3fc5fa97c92e59fc36fd98eb047a9bd1 Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@intel.com>
 Date: Thu, 24 Oct 2019 14:06:33 -0700
 Subject: [PATCH] Add ast2600-intel as a new board
@@ -7,83 +7,45 @@ Signed-off-by: Vernon Mauery <vernon.mauery@intel.com>
 Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- arch/arm/dts/Makefile                  |   3 +-
- arch/arm/dts/ast2600-intel.dts         | 197 ++++++++++++
+ arch/arm/dts/ast2600-intel.dts         | 202 ++++---------
  arch/arm/lib/interrupts.c              |   5 +
- arch/arm/mach-aspeed/ast2600/Kconfig   |   8 +
- board/aspeed/ast2600_intel/Kconfig     |  13 +
- board/aspeed/ast2600_intel/Makefile    |   4 +
+ arch/arm/mach-aspeed/ast2600/Kconfig   |   4 +-
+ board/aspeed/ast2600_intel/Makefile    |   3 +
  board/aspeed/ast2600_intel/ast-espi.c  | 292 ++++++++++++++++++
  board/aspeed/ast2600_intel/ast-irq.c   | 399 +++++++++++++++++++++++++
  board/aspeed/ast2600_intel/ast-irq.h   |   8 +
  board/aspeed/ast2600_intel/ast-timer.c |  59 ++++
- board/aspeed/ast2600_intel/intel.c     | 192 ++++++++++++
+ board/aspeed/ast2600_intel/intel.c     | 346 ++++++++++-----------
  cmd/Kconfig                            |   2 +-
  common/autoboot.c                      |  10 +
  configs/ast2600_openbmc_defconfig      |   2 +-
- 14 files changed, 1191 insertions(+), 3 deletions(-)
- mode change 100755 => 100644 arch/arm/dts/Makefile
- create mode 100644 arch/arm/dts/ast2600-intel.dts
- create mode 100644 board/aspeed/ast2600_intel/Kconfig
- create mode 100644 board/aspeed/ast2600_intel/Makefile
+ 12 files changed, 998 insertions(+), 334 deletions(-)
  create mode 100644 board/aspeed/ast2600_intel/ast-espi.c
  create mode 100644 board/aspeed/ast2600_intel/ast-irq.c
  create mode 100644 board/aspeed/ast2600_intel/ast-irq.h
  create mode 100644 board/aspeed/ast2600_intel/ast-timer.c
- create mode 100644 board/aspeed/ast2600_intel/intel.c
- mode change 100755 => 100644 configs/ast2600_openbmc_defconfig
 
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-old mode 100755
-new mode 100644
-index 786042cd8340..df844065cd4f
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -684,7 +684,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
- 	ast2600-fpga.dtb \
- 	ast2600-rainier.dtb \
- 	ast2600-slt.dtb \
--	ast2600-tacoma.dtb
-+	ast2600-tacoma.dtb \
-+	ast2600-intel.dtb
- 
- dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
- 
 diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts
-new file mode 100644
-index 000000000000..9a15e204f83b
---- /dev/null
+index c76547cd6352..e6197831cf02 100644
+--- a/arch/arm/dts/ast2600-intel.dts
 +++ b/arch/arm/dts/ast2600-intel.dts
-@@ -0,0 +1,197 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+// Copyright (c) 2019-2020 Intel Corporation
-+/dts-v1/;
-+
-+#include "ast2600-u-boot.dtsi"
-+
-+/ {
-+	memory {
-+		device_type = "memory";
-+		reg = <0x80000000 0x40000000>;
-+	};
-+
-+	chosen {
-+		stdout-path = &uart5;
-+	};
-+
-+	aliases {
-+		spi0 = &fmc;
-+		ethernet1 = &mac1;
-+	};
-+
-+	cpus {
-+		cpu@0 {
-+			clock-frequency = <800000000>;
-+		};
-+		cpu@1 {
-+			clock-frequency = <800000000>;
-+		};
-+	};
+@@ -1,10 +1,11 @@
+ // SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) 2019-2021 Intel Corporation
+ /dts-v1/;
+ 
+ #include "ast2600-u-boot.dtsi"
+ 
+ / {
+-	model = "AST2600 Intel EGS server board";
++	model = "Intel server board with AST2600 as the BMC";
+ 	compatible = "aspeed,ast2600-intel", "aspeed,ast2600";
+ 
+ 	memory {
+@@ -37,6 +38,42 @@
+ 			clock-frequency = <1200000000>;
+ 		};
+ 	};
 +
 +	system-leds {
 +		compatible = "gpio-leds";
@@ -120,139 +82,246 @@ index 000000000000..9a15e204f83b
 +
 +&uart2 {
 +	status = "okay";
-+};
-+
-+&uart5 {
-+	u-boot,dm-pre-reloc;
-+	status = "okay";
-+};
-+
-+&sdrammc {
-+	clock-frequency = <400000000>;
-+};
-+
-+&wdt1 {
+ };
+ 
+ &uart5 {
+@@ -49,22 +86,24 @@
+ };
+ 
+ &wdt1 {
 +	u-boot,dm-pre-reloc;
-+	status = "okay";
-+};
-+
-+&wdt2 {
+ 	status = "okay";
+ };
+ 
+ &wdt2 {
 +	u-boot,dm-pre-reloc;
-+	status = "okay";
-+};
-+
-+&wdt3 {
+ 	status = "okay";
+ };
+ 
+ &wdt3 {
 +	u-boot,dm-pre-reloc;
-+	status = "okay";
-+};
-+
-+&mdio {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	ethphy1: ethernet-phy@1 {
-+		reg = <0>;
-+	};
-+
-+	ethphy2: ethernet-phy@2 {
-+		reg = <0>;
-+	};
-+
-+	ethphy3: ethernet-phy@3 {
-+		reg = <0>;
-+	};
-+
-+	ethphy4: ethernet-phy@4 {
-+		reg = <0>;
-+	};
-+};
-+
-+&mac1 {
-+	status = "okay";
-+	phy-mode = "rgmii";
-+	phy-handle = <&ethphy2>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mac2link_default &pinctrl_mdio2_default>;
-+};
-+
-+&fmc {
-+	status = "okay";
+ 	status = "okay";
+ };
+ 
+ &mdio {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <	&pinctrl_mdio1_default &pinctrl_mdio2_default
+-			&pinctrl_mdio3_default &pinctrl_mdio4_default>;
++	pinctrl-0 = <&pinctrl_mdio2_default>;
+ 	#address-cells = <1>;
+ 	#size-cells = <0>;
+ 	ethphy0: ethernet-phy@0 {
+@@ -84,14 +123,6 @@
+ 	};
+ };
+ 
+-&mac0 {
+-	status = "okay";
+-	phy-mode = "rgmii";
+-	phy-handle = <&ethphy0>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_rgmii1_default>;
+-};
+-
+ &mac1 {
+ 	status = "okay";
+ 	phy-mode = "rgmii";
+@@ -100,146 +131,30 @@
+ 	pinctrl-0 = <&pinctrl_rgmii2_default>;
+ };
+ 
+-&mac2 {
+-	status = "okay";
+-	phy-mode = "rgmii";
+-	phy-handle = <&ethphy2>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_rgmii3_default>;
+-};
+-
+-&mac3 {
+-	status = "okay";
+-	phy-mode = "rgmii";
+-	phy-handle = <&ethphy3>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_rgmii4_default>;
+-};
+-
+ &fmc {
+ 	status = "okay";
+-
 +#if 0
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_fmcquad_default>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_fmcquad_default>;
+-
+-	flash@0 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-
+-	flash@1 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-
+-	flash@2 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-};
+-
+-&spi1 {
+-	status = "okay";
+-
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
+-			&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
+-			&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
+-
+-	flash@0 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-
+-	flash@1 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-};
+-
+-&spi2 {
+-	status = "okay";
+-
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
+-			&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
+-
 +#endif
-+	flash@0 {
-+		compatible = "spi-flash", "sst,w25q256";
-+		status = "okay";
+ 	flash@0 {
+ 		compatible = "spi-flash", "sst,w25q256";
+ 		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-
+-	flash@1 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
+-	};
+-
+-	flash@2 {
+-		compatible = "spi-flash", "sst,w25q256";
+-		status = "okay";
+-		spi-max-frequency = <50000000>;
+-		spi-tx-bus-width = <4>;
+-		spi-rx-bus-width = <4>;
 +		spi-max-frequency = <40000000>;
 +		spi-tx-bus-width = <2>;
 +		spi-rx-bus-width = <2>;
-+	};
-+};
-+
-+&emmc_slot0 {
-+	status = "okay";
-+	bus-width = <4>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_emmc_default>;
-+};
-+
-+&i2c4 {
-+	status = "okay";
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_i2c5_default>;
-+};
-+
-+&i2c5 {
-+	status = "okay";
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_i2c6_default>;
-+};
-+
-+&i2c6 {
-+	status = "okay";
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_i2c7_default>;
-+};
-+
-+&i2c7 {
-+	status = "okay";
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_i2c8_default>;
-+};
-+
-+&i2c8 {
-+	status = "okay";
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_i2c9_default>;
-+};
-+
+ 	};
+ };
+ 
+ &emmc {
+-	u-boot,dm-pre-reloc;
+ 	timing-phase = <0x700ff>;
+ };
+ 
+ &emmc_slot0 {
+-	u-boot,dm-pre-reloc;
+ 	status = "okay";
+ 	bus-width = <4>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_emmc_default>;
+-	sdhci-drive-type = <1>;
+-};
+-
+-&sdhci {
+-	timing-phase = <0xc6ffff>;
+-};
+-
+-&sdhci_slot0 {
+-	status = "okay";
+-	bus-width = <4>;
+-	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+-	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_sd1_default>;
+-	sdhci-drive-type = <1>;
+-};
+-
+-&sdhci_slot1 {
+-	status = "okay";
+-	bus-width = <4>;
+-	pwr-gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+-	pwr-sw-gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_sd2_default>;
+-	sdhci-drive-type = <1>;
+ };
+ 
+ &i2c4 {
+@@ -277,29 +192,32 @@
+ 	pinctrl-0 = <&pinctrl_i2c9_default>;
+ };
+ 
+-&pcie_bridge1 {
 +&i2c9 {
-+	status = "okay";
-+
+ 	status = "okay";
+-};
+ 
+-&h2x {
+-	status = "okay";
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&pinctrl_i2c10_default>;
-+};
-+
+ };
+ 
+-#if 0
+-&fsim0 {
 +&i2c12 {
-+	status = "okay";
+ 	status = "okay";
 +
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&pinctrl_i2c13_default>;
-+};
-+
+ };
+ 
+-&fsim1 {
 +&i2c13 {
-+	status = "okay";
+ 	status = "okay";
 +
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&pinctrl_i2c14_default>;
-+};
-\ No newline at end of file
+ };
+-#endif
+ 
+-&ehci1 {
++&pcie_bridge1 {
+ 	status = "okay";
+ };
+ 
+-&display_port {
++&h2x {
+ 	status = "okay";
+ };
+ 
 diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
 index ee775ce5d264..8c985532afb4 100644
 --- a/arch/arm/lib/interrupts.c
@@ -288,54 +357,26 @@ index ee775ce5d264..8c985532afb4 100644
  {
  	efi_restore_gd();
 diff --git a/arch/arm/mach-aspeed/ast2600/Kconfig b/arch/arm/mach-aspeed/ast2600/Kconfig
-index 6258b337bc3d..ffcb110c3ae3 100644
+index fcdc425de59d..0900d22366d3 100644
 --- a/arch/arm/mach-aspeed/ast2600/Kconfig
 +++ b/arch/arm/mach-aspeed/ast2600/Kconfig
-@@ -32,10 +32,18 @@ config TARGET_SLT_AST2600
+@@ -35,8 +35,8 @@ config TARGET_AST2600_INTEL
+ 	bool "AST2600-INTEL"
+ 	depends on ASPEED_AST2600
  	help
- 	  SLT-AST2600 is Aspeed SLT board for AST2600 chip.
- 
-+config TARGET_AST2600_INTEL
-+	bool "AST2600-INTEL"
-+	depends on ASPEED_AST2600
-+	help
+-	  AST2600-INTEL is an Intel Eagle Stream CRB with
+-	  AST2600 as the BMC.
 +	  AST2600-INTEL is an Intel server board with the AST2600
 +	  as the BMC.
-+
- endchoice
  
- source "board/aspeed/evb_ast2600/Kconfig"
- source "board/aspeed/fpga_ast2600/Kconfig"
- source "board/aspeed/slt_ast2600/Kconfig"
-+source "board/aspeed/ast2600_intel/Kconfig"
+ endchoice
  
- endif
-diff --git a/board/aspeed/ast2600_intel/Kconfig b/board/aspeed/ast2600_intel/Kconfig
-new file mode 100644
-index 000000000000..b841dab60c76
---- /dev/null
-+++ b/board/aspeed/ast2600_intel/Kconfig
-@@ -0,0 +1,13 @@
-+if TARGET_AST2600_INTEL
-+
-+config SYS_BOARD
-+	default "ast2600_intel"
-+
-+config SYS_VENDOR
-+	default "aspeed"
-+
-+config SYS_CONFIG_NAME
-+	string "board configuration name"
-+	default "ast2600_intel"
-+
-+endif
 diff --git a/board/aspeed/ast2600_intel/Makefile b/board/aspeed/ast2600_intel/Makefile
-new file mode 100644
-index 000000000000..37d2f0064f38
---- /dev/null
+index 1f9fcc73c719..37d2f0064f38 100644
+--- a/board/aspeed/ast2600_intel/Makefile
 +++ b/board/aspeed/ast2600_intel/Makefile
-@@ -0,0 +1,4 @@
-+obj-y += intel.o
+@@ -1 +1,4 @@
+ obj-y += intel.o
 +obj-y += ast-espi.o
 +obj-y += ast-irq.o
 +obj-y += ast-timer.o
@@ -1122,19 +1163,87 @@ index 000000000000..cf8c69aba5d3
 +	writel(tctrl, AST_TIMER_BASE + TIMER_CONTROL);
 +}
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-new file mode 100644
-index 000000000000..4a40a050c3da
---- /dev/null
+index be6dc49a3bc7..092ff8b5c095 100644
+--- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
-@@ -0,0 +1,192 @@
+@@ -1,222 +1,192 @@
+-// SPDX-License-Identifier: GPL-2.0+
+-/*
+- * Copyright (C) ASPEED Technology Inc.
+- */
 +// SPDX-License-Identifier: GPL-2.0
-+// Copyright (c) 2019-2020, Intel Corporation.
++// Copyright (c) 2019-2021, Intel Corporation.
 +
 +/* Intel customizations of Das U-Boot */
-+#include <common.h>
+ #include <common.h>
 +#include <asm/gpio.h>
-+#include <asm/io.h>
-+
+ #include <asm/io.h>
+ 
+-/* SCU registers */
+-#define SCU_BASE	0x1e6e2000
+-#define SCU_PINMUX4	(SCU_BASE + 0x410)
+-#define   SCU_PINMUX4_RGMII3TXD1	BIT(19)
+-#define SCU_PINMUX5	(SCU_BASE + 0x414)
+-#define   SCU_PINMUX5_SGPMI		BIT(27)
+-#define   SCU_PINMUX5_SGPMO		BIT(26)
+-#define   SCU_PINMUX5_SGPMLD		BIT(25)
+-#define   SCU_PINMUX5_SGPMCK		BIT(24)
+-#define SCU_GPIO_PD0	(SCU_BASE + 0x610)
+-#define SCU_GPIO_PD0_B6			BIT(14)
+-#define SCU_PINMUX27	(SCU_BASE + 0x69c)
+-#define   SCU_PINMUX27_HBLED_EN		BIT(31)
+-
+-/* eSPI registers */
+-#define ESPI_BASE		0x1e6ee000
+-#define ESPI_CTRL		(ESPI_BASE + 0x0)
+-#define ESPI_INT_EN		(ESPI_BASE + 0xc)
+-#define ESPI_CTRL2		(ESPI_BASE + 0x80)
+-#define ESPI_SYSEVT_INT_EN	(ESPI_BASE + 0x94)
+-#define ESPI_SYSEVT1_INT_EN	(ESPI_BASE + 0x100)
+-#define ESPI_SYSEVT_INT_T0	(ESPI_BASE + 0x110)
+-#define ESPI_SYSEVT_INT_T1	(ESPI_BASE + 0x114)
+-#define ESPI_SYSEVT1_INT_T0	(ESPI_BASE + 0x120)
+-
+-/* LPC registers */
+-#define LPC_BASE	0x1e789000
+-#define LPC_HICR5	(LPC_BASE + 0x80)
+-#define   LPC_HICR5_SIO80HGPIO_EN	BIT(31)
+-#define   LPC_HICR5_80HGPIO_EN		BIT(30)
+-#define   LPC_HICR5_80HGPIO_SEL_MASK	GENMASK(28, 24)
+-#define   LPC_HICR5_80HGPIO_SEL_SHIFT	24
+-#define   LPC_HICR5_SNP0_INT_EN		BIT(1)
+-#define   LPC_HICR5_SNP0_EN		BIT(0)
+-#define LPC_HICR6	(LPC_BASE + 0x84)
+-#define   LPC_HICR6_STS_SNP1		BIT(1)
+-#define   LPC_HICR6_STS_SNP0		BIT(0)
+-#define LPC_SNPWADR	(LPC_BASE + 0x90)
+-#define   LPC_SNPWADR_SNP0_MASK		GENMASK(15, 0)
+-#define   LPC_SNPWADR_SNP0_SHIFT	0
+-#define LPC_HICRB	(LPC_BASE + 0x100)
+-#define   LPC_HICRB_80HSGPIO_EN		BIT(13)
+-
+-/* GPIO/SGPIO registers */
+-#define GPIO_BASE	0x1e780000
+-#define GPIO_ABCD_VAL	(GPIO_BASE + 0x0)
+-#define GPIO_ABCD_VAL_D4		BIT(28)
+-#define GPIO_ABCD_VAL_C5		BIT(21)
+-#define GPIO_ABCD_VAL_C3		BIT(19)
+-#define GPIO_ABCD_DIR	(GPIO_BASE + 0x4)
+-#define GPIO_ABCD_DIR_D4		BIT(28)
+-#define GPIO_ABCD_DIR_C5		BIT(21)
+-#define GPIO_ABCD_DIR_C3		BIT(19)
+-#define GPIO_EFGH_DIR	(GPIO_BASE + 0x24)
+-#define GPIO_EFGH_DIR_G6		BIT(22)
+-#define SGPIO_M1_CONF	(GPIO_BASE + 0x554)
+-#define   SGPIO_M1_CONF_CLKDIV_MASK	GENMASK(31, 16)
+-#define   SGPIO_M1_CONF_CLKDIV_SHIFT	16
+-#define   SGPIO_M1_PINS_MASK		GENMASK(10, 6)
+-#define   SGPIO_M1_PINS_SHIFT		6
+-#define   SPGIO_M1_EN			BIT(0)
+-
+-#define LPC_HICR5_UNKVAL_MASK		0x1FFF0000	/* bits with unknown values on reset */
+-
+-static void snoop_init(void)
 +/* use GPIOC0 on intel boards */
 +#define FFUJ_GPIO "gpio@1e78000016"
 +
@@ -1183,14 +1292,15 @@ index 000000000000..4a40a050c3da
 +#define SCU_4bc_PASSTHRU2_MASK	GENMASK(29, 28)
 +
 +static void gpio_passthru_init(void)
-+{
+ {
+-	u32 val;
 +	writel(readl(SCU_BASE | SCU_4bc) |
 +	       SCU_4bc_PASSTHRU0_MASK | SCU_4bc_PASSTHRU1_MASK,
 +	       SCU_BASE | SCU_4bc);
 +	writel(readl(SCU_BASE | SCU_418) | SCU_418_PBIO_MASK,
 +	       SCU_BASE | SCU_418);
 +}
-+
+ 
 +#define AST_LPC_BASE 0x1e789000
 +#define LPC_SNOOP_ADDR 0x80
 +#define HICR5 0x080   /* Host Interface Control Register 5 */
@@ -1218,52 +1328,166 @@ index 000000000000..4a40a050c3da
 +{
 +	uint32_t value;
 +	/* enable port80h snoop and sgpio */
-+	/* set lpc snoop #0 to port 0x80 */
+ 	/* set lpc snoop #0 to port 0x80 */
+-	val = readl(LPC_SNPWADR) & 0xffff0000;
+-	val |= ((0x80 << LPC_SNPWADR_SNP0_SHIFT) &
+-		LPC_SNPWADR_SNP0_MASK);
+-	writel(val, LPC_SNPWADR);
 +	value = readl(AST_LPC_BASE + SNPWADR) & 0xffff0000;
 +	writel(value | LPC_SNOOP_ADDR, AST_LPC_BASE + SNPWADR);
-+
-+	/* clear interrupt status */
+ 
+ 	/* clear interrupt status */
+-	val = readl(LPC_HICR6);
+-	val |= (LPC_HICR6_STS_SNP0 |
+-		LPC_HICR6_STS_SNP1);
+-	writel(val, LPC_HICR6);
 +	value = readl(AST_LPC_BASE + HICR6);
 +	value |= HICR6_STR_SNP0W | HICR6_STR_SNP1W;
 +	writel(value, AST_LPC_BASE + HICR6);
-+
-+	/* enable lpc snoop #0 and SIOGIO */
+ 
+ 	/* enable lpc snoop #0 and SIOGIO */
+-	val = readl(LPC_HICR5);
+-	val |= (LPC_HICR5_SIO80HGPIO_EN |
+-		LPC_HICR5_SNP0_EN);
+-	writel(val, LPC_HICR5);
 +	value = readl(AST_LPC_BASE + HICR5) & ~(HICR5_UNKVAL_MASK);
 +	value |= HICR5_EN_SIOGIO | HICR5_EN_SNP0W;
 +	writel(value, AST_LPC_BASE + HICR5);
-+
-+	/* enable port80h snoop on SGPIO */
+ 
+ 	/* enable port80h snoop on SGPIO */
+-	val = readl(LPC_HICRB);
+-	val |= LPC_HICRB_80HSGPIO_EN;
+-	writel(val, LPC_HICRB);
 +	value = readl(AST_LPC_BASE + HICRB) | HICRB_EN80HSGIO;
 +	writel(value, AST_LPC_BASE + HICRB);
-+}
-+
+ }
+ 
 +#define AST_GPIO_BASE		0x1e780000
 +
-+static void sgpio_init(void)
-+{
-+#define SGPIO_CLK_DIV(N)	((N) << 16)
-+#define SGPIO_BYTES(N)		((N) << 6)
-+#define SGPIO_ENABLE		1
+ static void sgpio_init(void)
+ {
+ #define SGPIO_CLK_DIV(N)	((N) << 16)
+ #define SGPIO_BYTES(N)		((N) << 6)
+ #define SGPIO_ENABLE		1
 +#define GPIO554			0x554
 +#define SCU_414			0x414 /* Multi-function Pin Control #5 */
-+#define SCU_414_SGPM_MASK	GENMASK(27, 24)
-+
+ #define SCU_414_SGPM_MASK	GENMASK(27, 24)
+ 
 +	uint32_t value;
-+	/* set the sgpio clock to pclk/(2*(5+1)) or ~2 MHz */
+ 	/* set the sgpio clock to pclk/(2*(5+1)) or ~2 MHz */
+-	u32 val;
+-
+-	val = ((256 << SGPIO_M1_CONF_CLKDIV_SHIFT) & SGPIO_M1_CONF_CLKDIV_MASK) |
+-	      ((10 << SGPIO_M1_PINS_SHIFT) & SGPIO_M1_PINS_MASK) |
+-	      SPGIO_M1_EN;
+-	writel(val, SGPIO_M1_CONF);
+-
+-	val = readl(SCU_PINMUX5);
+-	val |= (SCU_PINMUX5_SGPMI  |
+-		SCU_PINMUX5_SGPMO  |
+-		SCU_PINMUX5_SGPMLD |
+-		SCU_PINMUX5_SGPMCK);
+-	writel(val, SCU_PINMUX5);
 +	value = SGPIO_CLK_DIV(256) | SGPIO_BYTES(10) | SGPIO_ENABLE;
 +	writel(value, AST_GPIO_BASE + GPIO554);
 +	writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK,
 +	       SCU_BASE | SCU_414);
-+}
-+
+ }
+ 
+-static void gpio_init(void)
 +static void timer_handler(void *regs)
-+{
+ {
+-	/* Default setting of Y23 pad in AST2600 A1 is HBLED so disable it. */
+-	writel(readl(SCU_PINMUX27) & ~SCU_PINMUX27_HBLED_EN,
+-	       SCU_PINMUX27);
+-
+-	/*
+-	 * Set GPIOC3 as an output with value high explicitly since it doesn't
+-	 * have an external pull up. It uses direct register access because
+-	 * it's called from board_early_init_f().
+-	 */
+-	writel(readl(SCU_PINMUX4) & ~SCU_PINMUX4_RGMII3TXD1,
+-	       SCU_PINMUX4);
+-	writel(readl(GPIO_ABCD_DIR) | GPIO_ABCD_DIR_C3,
+-	       GPIO_ABCD_DIR);
+-	writel(readl(GPIO_ABCD_VAL) | GPIO_ABCD_VAL_C3,
+-	       GPIO_ABCD_VAL);
+-
+-	writel(readl(SCU_GPIO_PD0) | SCU_GPIO_PD0_B6, SCU_GPIO_PD0);
+-
+-	/*
+-	 * GPIO C5 has a connection between BMC(3.3v) and CPU(1.0v) so if we
+-	 * set it as an logic high output, it will be clipped by a protection
+-	 * circuit in the CPU and eventually the signal will be detected as
+-	 * logic low. So we leave this GPIO as an input so that the signal
+-	 * can be pulled up by a CPU internal resister. The signal will be
+-	 * 1.0v logic high resultingy.
+-	 */
+-	writel(readl(GPIO_ABCD_DIR) & ~GPIO_ABCD_DIR_C5,
+-	       GPIO_ABCD_DIR);
+-
+-	/*
+-	 * Set GPIOD4 as an output with value low explicitly to set the
+-	 * default SPD mux path to CPU and DIMMs.
+-	 */
+-	writel(readl(GPIO_ABCD_DIR) | GPIO_ABCD_DIR_D4,
+-	       GPIO_ABCD_DIR);
+-	writel(readl(GPIO_ABCD_VAL) & ~GPIO_ABCD_VAL_D4,
+-	       GPIO_ABCD_VAL);
+-
+-	/* GPIO G6 is also an open-drain output so set it as an input. */
+-	writel(readl(GPIO_EFGH_DIR) & ~GPIO_EFGH_DIR_G6,
+-	       GPIO_EFGH_DIR);
 +	printf("+");
-+}
-+
+ }
+ 
+-static void espi_init(void)
 +extern int arch_interrupt_init_early(void);
 +int board_early_init_f(void)
-+{
+ {
+-	u32 reg;
+-
+-	/*
+-	 * Aspeed STRONGLY NOT recommend to use eSPI early init.
+-	 *
+-	 * This eSPI early init sequence merely set OOB_FREE. It
+-	 * is NOT able to actually handle OOB requests from PCH.
+-	 *
+-	 * During the power on stage, PCH keep waiting OOB_FREE
+-	 * to continue its booting. In general, OOB_FREE is set
+-	 * when BMC firmware is ready. That is, the eSPI kernel
+-	 * driver is mounted and ready to serve eSPI. However,
+-	 * it means that PCH must wait until BMC kernel ready.
+-	 *
+-	 * For customers that request PCH booting as soon as
+-	 * possible. You may use this early init to set OOB_FREE
+-	 * to prevent PCH from blocking by OOB_FREE before BMC
+-	 * kernel ready.
+-	 *
+-	 * If you are not sure what you are doing, DO NOT use it.
+-	 */
+-	reg = readl(ESPI_CTRL);
+-	reg |= 0xef;
+-	writel(reg, ESPI_CTRL);
+-
+-	writel(0x0, ESPI_SYSEVT_INT_T0);
+-	writel(0x0, ESPI_SYSEVT_INT_T1);
+-
+-	reg = readl(ESPI_INT_EN);
+-	reg |= 0x80000000;
+-	writel(reg, ESPI_INT_EN);
+-
+-	writel(0xffffffff, ESPI_SYSEVT_INT_EN);
+-	writel(0x1, ESPI_SYSEVT1_INT_EN);
+-	writel(0x1, ESPI_SYSEVT1_INT_T0);
+-
+-	reg = readl(ESPI_CTRL2);
+-	reg |= 0x50;
+-	writel(reg, ESPI_CTRL2);
+-
+-	reg = readl(ESPI_CTRL);
+-	reg |= 0x10;
+-	writel(reg, ESPI_CTRL);
 +	/* This is called before relocation; beware! */
 +	/* initialize running timer? timer_init is next in the list but
 +	 * I am not sure if it actually does anything... */
@@ -1277,8 +1501,9 @@ index 000000000000..4a40a050c3da
 +
 +	/* TODO: is it too late to enforce HW security registers? */
 +	return 0;
-+}
-+
+ }
+ 
+-int board_early_init_f(void)
 +extern void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler);
 +int board_early_init_r(void)
 +{
@@ -1290,11 +1515,14 @@ index 000000000000..4a40a050c3da
 +
 +extern void espi_init(void);
 +int board_late_init(void)
-+{
-+	espi_init();
+ {
+-	snoop_init();
+-	gpio_init();
+-	sgpio_init();
+ 	espi_init();
 +
-+	return 0;
-+}
+ 	return 0;
+ }
 +
 +/* aspeed/board.c defines these functions
 +int arch_early_init_r(void)
@@ -1358,12 +1586,10 @@ index 94133eaeda78..5e69000b848b 100644
  		abort = __abortboot(bootdelay);
  
 diff --git a/configs/ast2600_openbmc_defconfig b/configs/ast2600_openbmc_defconfig
-old mode 100755
-new mode 100644
-index 2e2df2e3a235..77c39d848312
+index 179e3b005768..90735feec921 100644
 --- a/configs/ast2600_openbmc_defconfig
 +++ b/configs/ast2600_openbmc_defconfig
-@@ -13,7 +13,7 @@ CONFIG_FIT=y
+@@ -35,7 +35,7 @@ CONFIG_FIT=y
  CONFIG_USE_BOOTARGS=y
  CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
  CONFIG_USE_BOOTCOMMAND=y
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch
index a036b91fc..c56fd872d 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch
@@ -1,4 +1,4 @@
-From fdb55afe15fdbba33782d01a77bbf994470f40b4 Mon Sep 17 00:00:00 2001
+From 665675336251d1daac56ce80d0490a8f71d13411 Mon Sep 17 00:00:00 2001
 From: Kuiying Wang <kuiying.wang@intel.com>
 Date: Thu, 12 Dec 2019 12:54:18 +0800
 Subject: [PATCH] ast2600: intel-layout-environment-addr
@@ -38,10 +38,10 @@ index 472987d5d52f..434c0df45c85 100644
  	env_set_hex("fdtcontroladdr",
  		    (unsigned long)map_to_sysmem(gd->fdt_blob));
 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
-index 8718b50f9ebe..70590067dbcf 100644
+index 8f404570b1fb..183a7a502e9c 100644
 --- a/include/configs/aspeed-common.h
 +++ b/include/configs/aspeed-common.h
-@@ -73,9 +73,18 @@
+@@ -67,9 +67,18 @@
  #endif
  
  #ifndef CONFIG_ENV_OFFSET
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch
index 612a104b5..6e44691f8 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch
@@ -1,4 +1,4 @@
-From ddd0ebfaf667f2fd36ed2f8d2d8456dbc6acdaa8 Mon Sep 17 00:00:00 2001
+From 6fe262f07e116ee185d3acf7967b2ea0d6cc3f3d Mon Sep 17 00:00:00 2001
 From: arun-pm <arun.p.m@linux.intel.com>
 Date: Fri, 29 Nov 2019 00:19:09 +0530
 Subject: [PATCH] SPI Quad IO Mode
@@ -14,10 +14,10 @@ Note:- Removed n25q00 Quad I/O support for the time being due to clock issue
  3 files changed, 25 insertions(+), 6 deletions(-)
 
 diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts
-index 9a15e204f83b..1f14753056ee 100644
+index e6197831cf02..c7970c16a474 100644
 --- a/arch/arm/dts/ast2600-intel.dts
 +++ b/arch/arm/dts/ast2600-intel.dts
-@@ -120,16 +120,14 @@
+@@ -133,16 +133,14 @@
  
  &fmc {
  	status = "okay";
@@ -55,7 +55,7 @@ index 5882eab2e3fc..42546f4d222a 100644
  	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
  	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c
-index f93200f8f67e..8ac6e40524fe 100644
+index f93200f8f67e..6db64079ae72 100644
 --- a/drivers/spi/aspeed_spi.c
 +++ b/drivers/spi/aspeed_spi.c
 @@ -17,6 +17,9 @@
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
index c4b8a00ef..bab279c40 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
@@ -1,4 +1,4 @@
-From 844e425a503c56bd84dbfe5396c5f8f9b4284e6d Mon Sep 17 00:00:00 2001
+From 053770be23c7826efefa9b7b087d8b285bf8bbcd Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 29 Jan 2020 14:55:44 -0800
 Subject: [PATCH] ast2600: Override OTP strap settings
@@ -8,11 +8,11 @@ Also, this commit disables SoC debug interface.
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- arch/arm/mach-aspeed/ast2600/platform.S | 24 ++++++++++++++++++++++--
- 1 file changed, 22 insertions(+), 2 deletions(-)
+ arch/arm/mach-aspeed/ast2600/platform.S | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index f96ef1f0dac4..3b6f91a60c3d 100644
+index 81520b0f036e..e479d0276d39 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
 @@ -44,7 +44,9 @@
@@ -22,10 +22,10 @@ index f96ef1f0dac4..3b6f91a60c3d 100644
 +#define AST_SCU_HW_STRAP1_CLR		(AST_SCU_BASE + 0x504)
  #define AST_SCU_HW_STRAP2		(AST_SCU_BASE + 0x510)
 +#define AST_SCU_HW_STRAP2_CLR		(AST_SCU_BASE + 0x514)
+ #define AST_SCU_HW_STRAP3		(AST_SCU_BASE + 0x51C)
  #define AST_SCU_CA7_PARITY_CHK		(AST_SCU_BASE + 0x820)
  #define AST_SCU_CA7_PARITY_CLR		(AST_SCU_BASE + 0x824)
- #define AST_SCU_MMIO_DEC_SET		(AST_SCU_BASE + 0xC24)
-@@ -175,6 +177,26 @@ do_primary_core_setup:
+@@ -176,6 +178,26 @@ do_primary_core_setup:
  	/* unlock system control unit */
  	scu_unlock
  
@@ -52,22 +52,6 @@ index f96ef1f0dac4..3b6f91a60c3d 100644
  	/* identify AST2600 A0/A1 */
  	ldr	r0, =AST_SCU_REV_ID
  	ldr	r0, [r0]
-@@ -277,7 +299,6 @@ skip_fill_wip_bit:
- 	ldr	r1, =AST_FMC_WDT1_CTRL_MODE
- 	str	r0, [r1]
- 
--#if 0
- 	/* disable UART-based SoC Debug Interface UART5 and P2A bridge*/
- 	ldr     r0, =AST_SCU_DEBUG_CTRL
- 	ldr     r1, [r0]
-@@ -289,7 +310,6 @@ skip_fill_wip_bit:
- 	ldr     r1, [r0]
- 	orr     r1, #0x0A
- 	str     r1, [r0]
--#endif
- 
- 	/* relocate mailbox insn. for cpuN polling SMP go signal */
- 	adrl	r0, mailbox_insn
 -- 
 2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch
index 6b417fae9..f3cb01143 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch
@@ -1,4 +1,4 @@
-From ec8377bb77dd560b3f03f02361d268b362e28e7f Mon Sep 17 00:00:00 2001
+From a3b27074feba66aaf63930197b4aa507abdcc983 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 25 Mar 2020 15:04:26 -0700
 Subject: [PATCH] AST2600: Add TPM pulse trigger
@@ -11,7 +11,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 17 insertions(+)
 
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index d03a446846bc..ebf883144418 100644
+index 634b8ce20e7d..e8165694c312 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
 @@ -234,6 +234,21 @@ static void set_gpio_default_state(void)
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch
index a506f3028..6196551a2 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch
@@ -1,4 +1,4 @@
-From f545610f26089e78e71469e9006e3337670af0f4 Mon Sep 17 00:00:00 2001
+From 970a7c3b21e7264bb6ada434652795b5ce947ac7 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Tue, 31 Mar 2020 13:28:31 -0700
 Subject: [PATCH] AST2600: Disable DMA arbitration options on MAC1 and MAC2
@@ -17,10 +17,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 18 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index 3b6f91a60c3d..eac52db538b0 100644
+index e479d0276d39..aaacb61a1f8b 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -57,6 +57,12 @@
+@@ -58,6 +58,12 @@
  #define AST_FMC_WDT1_CTRL_MODE	(AST_FMC_BASE + 0x060)
  #define AST_FMC_WDT2_CTRL_MODE	(AST_FMC_BASE + 0x064)
  
@@ -33,7 +33,7 @@ index 3b6f91a60c3d..eac52db538b0 100644
  #define AST_GPIO_BASE		(0x1E780000)
  #define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
  
-@@ -244,6 +250,18 @@ wait_lock:
+@@ -245,6 +251,18 @@ wait_lock:
  	bne	2f
  
  1:
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0015-net-phy-realtek-Change-LED-configuration.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0015-net-phy-realtek-Change-LED-configuration.patch
index d701d5a27..e3b53f76a 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0015-net-phy-realtek-Change-LED-configuration.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0015-net-phy-realtek-Change-LED-configuration.patch
@@ -1,4 +1,4 @@
-From 144b845cd597cb93e4a6143a194e5018f2176f23 Mon Sep 17 00:00:00 2001
+From cb1d9b2cb8a3afbbdcc0b5ee81f48c4b185da2bd Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Fri, 5 Jun 2020 14:08:20 -0700
 Subject: [PATCH] net: phy: realtek: Change LED configuration
@@ -14,10 +14,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 7 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
-index dd45e11b3ad9..167b34b2b2c9 100644
+index 6976ff7c0846..5bd620f67b6a 100644
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -169,10 +169,15 @@ static int rtl8211f_config(struct phy_device *phydev)
+@@ -180,10 +180,15 @@ static int rtl8211f_config(struct phy_device *phydev)
  	phy_write(phydev, MDIO_DEVAD_NONE,
  		  MIIM_RTL8211F_PAGE_SELECT, 0x0);
  
@@ -36,5 +36,5 @@ index dd45e11b3ad9..167b34b2b2c9 100644
  		  MIIM_RTL8211F_PAGE_SELECT, 0x0);
  
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-LED-control-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-LED-control-support.patch
index bc2007288..774767f97 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-LED-control-support.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-LED-control-support.patch
@@ -1,4 +1,4 @@
-From d7befc37ba40a248899b5dc8e99bef2746a957d2 Mon Sep 17 00:00:00 2001
+From d88bb32a5c33f356926a309289497f1b1e7c9aa1 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Fri, 2 Apr 2021 09:48:38 -0700
 Subject: [PATCH] Add LED control support
@@ -24,10 +24,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  6 files changed, 226 insertions(+), 8 deletions(-)
 
 diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts
-index 1f14753056ee..5243d1a0afc3 100644
+index c7970c16a474..7cae636554b6 100644
 --- a/arch/arm/dts/ast2600-intel.dts
 +++ b/arch/arm/dts/ast2600-intel.dts
-@@ -47,8 +47,8 @@
+@@ -58,8 +58,8 @@
  		};
  		hb-led {
  			label = "hb";
@@ -39,7 +39,7 @@ index 1f14753056ee..5243d1a0afc3 100644
  	};
  };
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index 849e81ff3fef..fb9075f93945 100644
+index 6e442cf01472..46f169589915 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
 @@ -5,6 +5,7 @@
@@ -388,7 +388,7 @@ index 93f6b913c647..a88efde71a69 100644
  
  static const struct udevice_id led_gpio_ids[] = {
 diff --git a/include/led.h b/include/led.h
-index 7bfdddfd6fab..fb072c8b9f1a 100644
+index 7bfdddfd6fab..583dbd2f8f0e 100644
 --- a/include/led.h
 +++ b/include/led.h
 @@ -32,7 +32,6 @@ enum led_state_t {
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch
index 66a1b564e..250ca7f5c 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch
@@ -1,4 +1,4 @@
-From 2f4d7260a4ab0eb33d1145cd640019aa1fa1414a Mon Sep 17 00:00:00 2001
+From d7cdcbd4222ef3ad6d532c1034f4649432b0a69d Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Thu, 18 Jun 2020 15:08:57 -0700
 Subject: [PATCH] Add a workaround to cover VGA memory size bug in A0
@@ -13,10 +13,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 17 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index eac52db538b0..cf709aaa5d98 100644
+index aaacb61a1f8b..7e6787e5c6db 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -212,6 +212,12 @@ do_primary_core_setup:
+@@ -213,6 +213,12 @@ do_primary_core_setup:
  
  	bne	0f
  
@@ -29,7 +29,7 @@ index eac52db538b0..cf709aaa5d98 100644
  	/* tune up CPU clocks (A0 only) */
  	ldr	r0, =AST_SCU_HW_STRAP1
  	ldr	r1, [r0]
-@@ -250,6 +256,17 @@ wait_lock:
+@@ -251,6 +257,17 @@ wait_lock:
  	bne	2f
  
  1:
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch
index 26c83f8d6..547264260 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch
@@ -1,4 +1,4 @@
-From 783ef5212c5efc0561361fd779f1be3b047aee74 Mon Sep 17 00:00:00 2001
+From f7671739c0d48994c3b6b90d08a75f0ba9e9a2ca Mon Sep 17 00:00:00 2001
 From: Suryakanth Sekar <suryakanth.sekar@linux.intel.com>
 Date: Thu, 18 Jun 2020 05:32:48 +0530
 Subject: [PATCH] Apply WDT1-2 reset mask to reset needed controller
@@ -61,10 +61,10 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
  1 file changed, 22 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index cf709aaa5d98..027265593f03 100644
+index 7e6787e5c6db..937ea0d7b9a0 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -63,6 +63,14 @@
+@@ -64,6 +64,14 @@
  #define AST_MAC2_BASE		(0x1E680000)
  #define AST_MAC2_CTRL2		(AST_MAC2_BASE + 0x058)
  
@@ -79,7 +79,7 @@ index cf709aaa5d98..027265593f03 100644
  #define AST_GPIO_BASE		(0x1E780000)
  #define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
  
-@@ -292,6 +300,20 @@ wait_lock:
+@@ -293,6 +301,20 @@ wait_lock:
  	str	r1, [r0]
  
  2:
@@ -97,9 +97,9 @@ index cf709aaa5d98..027265593f03 100644
 +	bic	r1, r2
 +	str	r1, [r0]
 +
- 	/* MMIO decode setting */
- 	ldr	r0, =AST_SCU_MMIO_DEC_SET
- 	mov	r1, #0x2000
+ 	/* PCIeRC/E2M8 power-on reset comes from SCU040
+ 	But SCU04018 default value is 0x0.
+ 	It should be 0x1 to reset PCIeRC/E2M8.*/
 -- 
 2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch
index e62403413..e143692a0 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch
@@ -1,4 +1,4 @@
-From 385629a99a8d07182812264f2868d5f85fb711e0 Mon Sep 17 00:00:00 2001
+From d1acf70afd376b45a73b325ee30c0532a142c4f2 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 16 Sep 2020 13:25:36 -0700
 Subject: [PATCH] Add WDT to u-boot to cover booting failures
@@ -20,10 +20,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  7 files changed, 116 insertions(+), 38 deletions(-)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index 027265593f03..e57bd325277f 100644
+index 937ea0d7b9a0..c65adff0d69a 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -64,6 +64,9 @@
+@@ -65,6 +65,9 @@
  #define AST_MAC2_CTRL2		(AST_MAC2_BASE + 0x058)
  
  #define AST_WDT1_BASE		0x1E785000
@@ -33,7 +33,7 @@ index 027265593f03..e57bd325277f 100644
  #define AST_WDT1_RESET_MASK1	(AST_WDT1_BASE + 0x01C)
  #define AST_WDT1_RESET_MASK2	(AST_WDT1_BASE + 0x020)
  
-@@ -328,6 +331,18 @@ wait_lock:
+@@ -348,6 +351,18 @@ wait_lock:
  	ldr	r1, =AST_SCU_CA7_PARITY_CHK
  	str	r0, [r1]
  
@@ -53,7 +53,7 @@ index 027265593f03..e57bd325277f 100644
  	ldr	r1, =AST_FMC_WDT2_CTRL_MODE
  	str	r0, [r1]
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index 948f8a01f868..1a95893631c8 100644
+index 03eff62ce04b..88d9384faf2d 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
 @@ -7,6 +7,7 @@
@@ -150,7 +150,7 @@ index 4d4248f234fb..90687092e1ae 100644
  		from += len;
  		to += len;
 diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
-index a8f5b6158241..69dfc7f21698 100644
+index e1fe91712e24..13f499a90272 100644
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
 @@ -20,6 +20,7 @@
@@ -300,7 +300,7 @@ index c2dc3cf548d2..811ead41bb95 100644
  	return 0;
  }
 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
-index 70590067dbcf..0eaf76b50b39 100644
+index 183a7a502e9c..d5befb185b6a 100644
 --- a/include/configs/aspeed-common.h
 +++ b/include/configs/aspeed-common.h
 @@ -20,6 +20,8 @@
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch
index 1191a6077..959fd0bf4 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch
@@ -1,4 +1,4 @@
-From 438ff3a8db6718bb137dccaafa707f8275407742 Mon Sep 17 00:00:00 2001
+From fc01155d6f78ab9940f1d1482b0df44addc5f313 Mon Sep 17 00:00:00 2001
 From: Vikram Bodireddy <vikram.bodireddy@intel.com>
 Date: Mon, 22 Feb 2021 17:22:16 +0530
 Subject: [PATCH] ast2600-PFR-platform-EXTRST-reset-mask-selection
@@ -16,7 +16,7 @@ Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
  1 file changed, 12 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index bdc0884de1bd..d7115c96f117 100644
+index c65adff0d69a..3db7d993d3ca 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
 @@ -39,6 +39,8 @@
@@ -28,18 +28,18 @@ index bdc0884de1bd..d7115c96f117 100644
  #define AST_SCU_DEBUG_CTRL              (AST_SCU_BASE + 0x0C8)
  #define AST_SCU_DEBUG_CTRL2             (AST_SCU_BASE + 0x0D8)
  #define AST_SCU_HPLL_PARAM		(AST_SCU_BASE + 0x200)
-@@ -303,6 +305,16 @@ wait_lock:
+@@ -304,6 +306,16 @@ wait_lock:
  	str	r1, [r0]
  
  2:
 +	/* SCU060:EXTRST1# reset mask selection */
 +	ldr 	r0, =AST_SCU_EXTRST_SEL1
-+	ldr 	r1, =0x6FF1FF5
++	ldr 	r1, =0x6FF1FF1
 +	str 	r1, [r0]
 +
 +	/* SCU070:EXTRST2# reset mask selection */
 +	ldr 	r0, =AST_SCU_EXTRST_SEL2
-+	ldr 	r1, =0x3FFFFF7
++	ldr 	r1, =0x3FFFFF3
 +	str 	r1, [r0]
 +
  	/* disable eSPI, LPC and PWM resets on WDT1 reset */
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch
index b01b96e16..ee1a8f7a4 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch
@@ -1,4 +1,4 @@
-From 8534fb50dfe7c4e1c042843ded54c4ed23ee7bc2 Mon Sep 17 00:00:00 2001
+From cd13ae4e64d57af84dc98ff6c8d5b31661bc450d Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Tue, 8 Jan 2019 13:33:15 -0800
 Subject: [PATCH] Enable PCIe L1 support
@@ -11,12 +11,12 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 14 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index d7115c96f117..803ff94c4fc0 100644
+index 3db7d993d3ca..e2fcb732b6a6 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -329,6 +329,20 @@ wait_lock:
- 	bic	r1, r2
- 	str	r1, [r0]
+@@ -349,6 +349,20 @@ wait_lock:
+ 	movt    r1, #0x0000
+ 	str     r1, [r0]
  
 +	/* enable PCIe L1 support */
 +	ldr	r0, =0x1e6ed07c
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0029-Set-UART-routing-in-lowlevel_init.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0029-Set-UART-routing-in-lowlevel_init.patch
index 4d8d97d10..72be1a0b4 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0029-Set-UART-routing-in-lowlevel_init.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0029-Set-UART-routing-in-lowlevel_init.patch
@@ -1,4 +1,4 @@
-From b6f6c6fe9b92e3b1bbed12e27a65e822a44da528 Mon Sep 17 00:00:00 2001
+From 44321f61f0b0edbde3300cc43b2f3e9f9fd93d44 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Mon, 26 Apr 2021 13:20:21 -0700
 Subject: [PATCH] Set UART routing in lowlevel_init
@@ -13,10 +13,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 8 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index 0d038920b150..dce15c83a093 100644
+index e2fcb732b6a6..4cc22e31c604 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -79,6 +79,9 @@
+@@ -80,6 +80,9 @@
  #define AST_GPIO_BASE		(0x1E780000)
  #define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
  
@@ -26,9 +26,9 @@ index 0d038920b150..dce15c83a093 100644
  /* Revision ID */
  #define REV_ID_AST2600A0	0x05000303
  #define REV_ID_AST2600A1	0x05010303
-@@ -409,6 +412,11 @@ skip_fill_wip_bit:
- 	orr     r1, #0x0A
- 	str     r1, [r0]
+@@ -433,6 +436,11 @@ skip_fill_wip_bit:
+ 	moveq	r1, #0xff
+ 	str	r1, [r0]
  
 +	/* set UART routing back to default */
 +	ldr	r0, =AST_LPC_HICRA
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch
index ac7262f2c..176f9fa04 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch
@@ -1,4 +1,4 @@
-From b68b7c30fa3331642e321d150017d431d8cf6f6d Mon Sep 17 00:00:00 2001
+From a772d7bdde659d689fda47accc0f50bb6ce047d1 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Mon, 17 May 2021 13:11:24 -0700
 Subject: [PATCH] Add Aspeed PWM uclass driver
@@ -14,15 +14,15 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  drivers/pinctrl/aspeed/pinctrl_ast2600.c | 130 ++++++++++++++++-
  drivers/pwm/Kconfig                      |   8 ++
  drivers/pwm/Makefile                     |   1 +
- drivers/pwm/aspeed_pwm.c                 | 175 +++++++++++++++++++++++
- 7 files changed, 461 insertions(+), 1 deletion(-)
+ drivers/pwm/aspeed_pwm.c                 | 172 +++++++++++++++++++++++
+ 7 files changed, 458 insertions(+), 1 deletion(-)
  create mode 100644 drivers/pwm/aspeed_pwm.c
 
 diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts
-index 5243d1a0afc3..79356d8b7a64 100644
+index 7cae636554b6..a76193716d34 100644
 --- a/arch/arm/dts/ast2600-intel.dts
 +++ b/arch/arm/dts/ast2600-intel.dts
-@@ -53,6 +53,17 @@
+@@ -64,6 +64,17 @@
  	};
  };
  
@@ -41,7 +41,7 @@ index 5243d1a0afc3..79356d8b7a64 100644
  	status = "okay";
  };
 diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
-index e619f7118886..44ec6655fee7 100644
+index 9c4282515d55..3ff5bf2e16e1 100644
 --- a/arch/arm/dts/ast2600.dtsi
 +++ b/arch/arm/dts/ast2600.dtsi
 @@ -265,6 +265,14 @@
@@ -59,7 +59,7 @@ index e619f7118886..44ec6655fee7 100644
  			syscon: syscon@1e6e2000 {
  				compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
  				reg = <0x1e6e2000 0x1000>;
-@@ -1589,6 +1597,86 @@
+@@ -1598,6 +1606,86 @@
  		groups = "PWM7";
  	};
  
@@ -147,7 +147,7 @@ index e619f7118886..44ec6655fee7 100644
  		function = "RGMII1";
  		groups = "RGMII1";
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index ec6b70ae6659..11b8d4dd8360 100644
+index 82df0ac6137e..f1136eec9ab9 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
 @@ -8,6 +8,7 @@
@@ -212,7 +212,7 @@ index ec6b70ae6659..11b8d4dd8360 100644
  int board_early_init_f(void)
  {
  	/* This is called before relocation; beware! */
-@@ -613,6 +661,7 @@ int board_late_init(void)
+@@ -576,6 +624,7 @@ int board_late_init(void)
  		     timer_callback, (void *)1);
  #endif
  
@@ -395,7 +395,7 @@ index a837c35ed2e3..770b054c3f3b 100644
 +obj-$(CONFIG_PWM_ASPEED)	+= aspeed_pwm.o
 diff --git a/drivers/pwm/aspeed_pwm.c b/drivers/pwm/aspeed_pwm.c
 new file mode 100644
-index 000000000000..111e2971d226
+index 000000000000..bd9a911b4fe2
 --- /dev/null
 +++ b/drivers/pwm/aspeed_pwm.c
 @@ -0,0 +1,172 @@
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0032-Disable-eSPI-initialization-in-u-boot-for-normal-boo.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0032-Disable-eSPI-initialization-in-u-boot-for-normal-boo.patch
new file mode 100644
index 000000000..aa1f0cc65
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0032-Disable-eSPI-initialization-in-u-boot-for-normal-boo.patch
@@ -0,0 +1,62 @@
+From e152d718da6bfdf71d309b7ec885d2050fc19d01 Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Wed, 2 Jun 2021 13:03:47 -0700
+Subject: [PATCH] Disable eSPI initialization in u-boot for normal booting
+ cases
+
+Initializing eSPI in u-boot introduces a small blind window of
+handshaking when BMC jumps from boot loader to kernel and it causes
+an infinite PCH waiting issue in ME recovery mode. During the power
+on handshaking, PCH keeps waiting for OOB_FREE to continue its
+booting so the OOB_FREE actually means that BMC is fully ready for
+the power on handshake. To prevent the small blind window, this
+commit removes eSPI initialization in u-boot for normal booting
+cases and makes the kernel eSPI driver responsible for full
+eSPI initialization.
+
+eSPI will be initialized in u-boot only in these specific cases:
+1. When FFUJ (Force Firmware Update Jumper) is populated.
+2. When BMC booting is stopped at u-boot by typing a key.
+3. When BMC goes to u-boot due to the boot failure condition.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/intel.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
+index aff0c8593759..fc2f3c8feea7 100644
+--- a/board/aspeed/ast2600_intel/intel.c
++++ b/board/aspeed/ast2600_intel/intel.c
+@@ -201,7 +201,11 @@ static void gpio_passthru_init(void)
+ 
+ void board_pre_abort_autoboot(void)
+ {
+-	gpio_passthru_init();
++	if (!read_ffuj()) {
++		espi_init();
++		gpio_passthru_init();
++		kcs_init();
++	}
+ }
+ 
+ #define AST_LPC_BASE 0x1e789000
+@@ -662,7 +666,6 @@ int board_late_init(void)
+ #endif
+ 
+ 	pwm_init();
+-	espi_init();
+ 
+ 	/* Add reset reason to bootargs */
+ 	snprintf(value, sizeof(value), "0x%x", gd->reset_reason);
+@@ -684,6 +687,7 @@ int board_late_init(void)
+ 		update_bootargs_cmd("special", "mfg");
+ 
+ 	if (read_ffuj()) {
++		espi_init();
+ 		gpio_passthru_init();
+ 		kcs_init();
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0033-Disable-debug-interfaces.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0033-Disable-debug-interfaces.patch
new file mode 100644
index 000000000..9a7541eed
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0033-Disable-debug-interfaces.patch
@@ -0,0 +1,86 @@
+From 7a0f0e0915c7d9260a3d067746157112f85822db Mon Sep 17 00:00:00 2001
+From: Chen Yugang <yugang.chen@linux.intel.com>
+Date: Fri, 11 Jun 2021 12:44:25 +0800
+Subject: [PATCH] Disable debug interfaces
+
+1.Disable ARM Core CA7 debug features in
+SCU800: CA7 processor Control
+2.Disable Mailbox Write/Disable in PDSEF0: PCIe
+Device Security Enhancement Control Register F0
+3.Disable target AHB to PCIE RC bridge controller
+in AHBC88: AHB Bus Target Disable Control Register
+
+Signed-off-by: Chen Yugang <yugang.chen@linux.intel.com>
+---
+ arch/arm/mach-aspeed/ast2600/platform.S | 34 +++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
+index 4cc22e31c6..636bccad32 100644
+--- a/arch/arm/mach-aspeed/ast2600/platform.S
++++ b/arch/arm/mach-aspeed/ast2600/platform.S
+@@ -26,6 +26,9 @@
+  * +----------------------+ AST_SMP_MAILBOX_BASE
+  */
+ 
++#define AST_AHBC_BASE			0x1E600000
++#define AST_AHBC_BUS_TARGET_CTRL	(AST_AHBC_BASE + 0x088)
++
+ #define AST_SMP_MAILBOX_BASE		(0x1E6E2180)
+ #define AST_SMP_MBOX_FIELD_ENTRY	(AST_SMP_MAILBOX_BASE + 0x0)
+ #define AST_SMP_MBOX_FIELD_GOSIGN	(AST_SMP_MAILBOX_BASE + 0x4)
+@@ -50,6 +53,7 @@
+ #define AST_SCU_HW_STRAP2		(AST_SCU_BASE + 0x510)
+ #define AST_SCU_HW_STRAP2_CLR		(AST_SCU_BASE + 0x514)
+ #define AST_SCU_HW_STRAP3		(AST_SCU_BASE + 0x51C)
++#define AST_SCU_CA7_PROCESSOR_CTRL	(AST_SCU_BASE + 0x800)
+ #define AST_SCU_CA7_PARITY_CHK		(AST_SCU_BASE + 0x820)
+ #define AST_SCU_CA7_PARITY_CLR		(AST_SCU_BASE + 0x824)
+ #define AST_SCU_MMIO_DEC_SET		(AST_SCU_BASE + 0xC24)
+@@ -83,6 +87,9 @@
+ #define AST_LPC_BASE		0x1E789000
+ #define AST_LPC_HICRA		(AST_LPC_BASE + 0x09C)
+ 
++#define AST_PCIEATH_BASE		0x1E7F2000
++#define AST_PCIEATH_SECURITY_CTRL	(AST_PCIEATH_BASE + 0x0F0)
++
+ /* Revision ID */
+ #define REV_ID_AST2600A0	0x05000303
+ #define REV_ID_AST2600A1	0x05010303
+@@ -436,6 +443,33 @@ skip_fill_wip_bit:
+ 	moveq	r1, #0xff
+ 	str	r1, [r0]
+ 
++	/* disable debug interfaces  */
++	/* SCU_800 */
++	ldr	r0, =AST_SCU_CA7_PROCESSOR_CTRL
++	ldr	r1, [r0]
++	ldr	r2, =0x0c03f
++	and	r1, r1, r2
++	str	r1, [r0]
++
++	/* PCIEATH_F0 */
++	ldr	r0, =AST_PCIEATH_SECURITY_CTRL
++	ldr	r1, [r0]
++	orr	r1, #0x50000
++	str	r1, [r0]
++
++	/* AHBC_088 */
++	ldr	r0, =AST_AHBC_BASE
++	movw	r1, #0x1a03
++	movt	r1, #0xaeed
++	str	r1, [r0]
++	ldr	r0, =AST_AHBC_BUS_TARGET_CTRL
++	ldr	r1, [r0]
++	orr	r1, #0xc0000
++	str	r1, [r0]
++	ldr	r0, =AST_AHBC_BASE
++	movw	r1, #0
++	str	r1, [r0]
++
+ 	/* set UART routing back to default */
+ 	ldr	r0, =AST_LPC_HICRA
+ 	ldr	r1, =0x0
+-- 
+2.27.0
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0034-Implement-the-IPMI-commands-in-FFUJ-mode-in-u-boot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0034-Implement-the-IPMI-commands-in-FFUJ-mode-in-u-boot.patch
new file mode 100644
index 000000000..0d27f9d70
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0034-Implement-the-IPMI-commands-in-FFUJ-mode-in-u-boot.patch
@@ -0,0 +1,211 @@
+From 8b0d9f83aeb6e58c271ffe2d07c79397fe813a78 Mon Sep 17 00:00:00 2001
+From: AKSHAY RAVEENDRAN K <akshay.raveendran.k@intel.com>
+Date: Wed, 23 Jun 2021 18:10:08 +0000
+Subject: [PATCH] Implement the IPMI commands in FFUJ mode in u-boot
+
+Implemented the following IPMI commands in force firmware update
+jumper (FFUJ) mode in u-boot.
+
+1. Get BMC execution context (0x23)
+2. Get Security mode (0xb3)
+3. Set security mode (0xb4)
+4. Get buffer size (0x66)
+
+Tested:
+Used ipmitool from Host OS to verify each individual commands
+
+Positive test cases:
+
+get execution context
+ipmitool raw 8 0x23
+11 01
+get buffer size
+ipmitool raw 0x30 0x66
+ff ff
+set security mode 
+ipmitool raw 0x30 0xb4 5
+get security mode
+ipmitool raw 0x30 0xb3
+05 00
+set security mode
+ipmitool raw 0x30 0xb4 4
+get security mode
+ipmitool raw 0x30 0xb3
+04 00
+set security mode
+ipmitool raw 0x30 0xb4 3
+get security mode
+ipmitool raw 0x30 0xb3
+03 00
+
+Negative test cases:
+
+set security mode
+ipmitool raw 0x30 0xb4 1
+Unable to send RAW command: Invalid data field in request
+ipmitool raw 0x30 0xb4 2
+Unable to send RAW command: Invalid data field in request
+ipmitool raw 0x30 0xb4 6
+Unable to send RAW command: Invalid data field in request
+ipmitool raw 0x30 0xb4 7
+Unable to send RAW command: Invalid data field in request
+
+Change-Id: I515cec5ff6019aa3ea30a9a38886130e354252a8
+Signed-off-by: AKSHAY RAVEENDRAN K <akshay.raveendran.k@intel.com>
+---
+ board/aspeed/ast2600_intel/ipmi-handler.c | 120 +++++++++++++++++++++-
+ 1 file changed, 117 insertions(+), 3 deletions(-)
+
+diff --git a/board/aspeed/ast2600_intel/ipmi-handler.c b/board/aspeed/ast2600_intel/ipmi-handler.c
+index 04732846ac..5319f986a7 100644
+--- a/board/aspeed/ast2600_intel/ipmi-handler.c
++++ b/board/aspeed/ast2600_intel/ipmi-handler.c
+@@ -4,11 +4,28 @@
+ #include "ipmi-handler.h"
+ 
+ /* IPMI network function codes */
+-#define NETFN_APP			0x06
++#define NETFN_APP		0x06
++#define NETFN_FIRMWARE		0x08
++#define NETFN_INTEL_OEM	0x30
+ 
+ /* IPMI command codes */
+ #define CMD_GET_DEV_ID			0x01
+ #define CMD_GET_SELF_TEST_RESULTS	0x04
++#define CMD_FWUPD_GET_EXECUTION_CTX 	0x23
++#define CMD_INTL_OEM_GET_BUFFER_SIZE	0x66
++#define CMD_INTL_OEM_GET_SEC_MODE	0xB3
++#define CMD_INTL_OEM_SET_SEC_MODE	0xB4
++
++#define MAX_KCS_BUF_SIZE	1020	/* (0xFF * 4) */
++#define MAX_IPMB_BUF_SIZE	1020	/* (0xFF * 4) */
++
++/* Restriction mode values */
++#define RESTRICTION_MODE_MIN_VALUE	3	/*Provisioning*/
++#define RESTRICION_MODE_MAX_VALUE	5	/*Provisioned host disabled */
++
++#define STR_ENV_PROVISION	"provision"
++
++#define PRIMARY_IMAGE	0x01
+ 
+ typedef u16 (*fun_handler)(u8 *req, u16 req_len, u8 *res);
+ 
+@@ -28,6 +45,21 @@ struct self_test_res {
+ 	u8 completion_code;
+ 	u8 res_byte[2];
+ };
++struct fwupd_get_exe_ctx_res {
++	u8 completion_code;
++	u8 execution_ctx;
++	u8 partition_ptr;
++};
++struct intc_get_buf_size_res {
++	u8 completion_code;
++	u8 kcs_size;
++	u8 ipmb_size;
++};
++struct intc_get_secuirty_mode_res {
++	u8 completion_code;
++	u8 restriction_mode;
++	u8 special_mode;
++};
+ 
+ struct ipmi_cmd_table {
+ 	u8 net_fun;
+@@ -84,9 +116,91 @@ static u16 get_self_test_result(u8 *req, u16 req_len, u8 *res)
+ 	return sizeof(struct self_test_res);
+ }
+ 
++u16 fwupd_get_execution_ctx(u8 *req, u16 req_len, u8 *res) {
++
++	/* Get firmware update execution context */
++	struct fwupd_get_exe_ctx_res *result = (struct fwupd_get_exe_ctx_res *)res;
++
++	/* For PFR platforms, only primary/active image always */
++	result->partition_ptr = PRIMARY_IMAGE;
++	result->execution_ctx = 0x11; /* Forced Firmware Update mode */
++	result->completion_code = IPMI_CC_OK;
++
++	return sizeof(struct fwupd_get_exe_ctx_res);
++}
++
++static u16 intel_get_buffer_size(u8 *req, u16 req_len, u8 *res) {
++
++	/* Get buffer size */
++	struct intc_get_buf_size_res *result = (struct intc_get_buf_size_res *)res;
++
++	if (req_len != 0) {
++		result->completion_code = IPMI_CC_INVALID_DATA_LENGTH;
++		return sizeof(result->completion_code);
++	}
++
++	/* Size is multiples of four bytes */
++	result->completion_code = IPMI_CC_OK;
++	result->kcs_size = MAX_KCS_BUF_SIZE / 4;
++	result->ipmb_size = MAX_IPMB_BUF_SIZE / 4;
++
++	return sizeof(struct intc_get_buf_size_res);
++}
++
++static u16 intel_get_security_mode(u8 *req, u16 req_len, u8 *res) {
++
++	char *cmdline = NULL;
++	/* Get security mode */
++	struct intc_get_secuirty_mode_res *result =
++		(struct intc_get_secuirty_mode_res *)res;
++
++	if (req_len != 0) {
++		result->completion_code = IPMI_CC_INVALID_DATA_LENGTH;
++		return sizeof(result->completion_code);
++	}
++
++	cmdline = env_get(STR_ENV_PROVISION);
++
++	if (!cmdline) {
++		/* Default provision must be set only by linux */
++		result->completion_code = IPMI_CC_UNSPECIFIED;
++		return sizeof(result->completion_code);
++	}
++
++	result->restriction_mode = simple_strtol(cmdline, NULL, 10);
++	/* special mode is non-volatile and not applicable in U-Boot */
++	result->special_mode = 0;
++	result->completion_code = IPMI_CC_OK;
++
++	return sizeof(*result);
++}
++
++static u16 intel_set_security_mode(u8 *req, u16 req_len, u8 *res) {
++
++	if (req_len != sizeof(*req)) {
++		*res = IPMI_CC_INVALID_DATA_LENGTH;
++		return sizeof(*res);
++	}
++
++	if (*req > RESTRICION_MODE_MAX_VALUE || *req < RESTRICTION_MODE_MIN_VALUE) {
++		*res = IPMI_CC_INVALID_DATA_FIELD;
++		return sizeof(*res);
++	}
++
++	env_set_ulong(STR_ENV_PROVISION, *req);
++	env_save();
++	*res = IPMI_CC_OK;
++
++	return sizeof(*res);
++}
++
+ const struct ipmi_cmd_table cmd_info[] = {
+-	{ NETFN_APP,	CMD_GET_DEV_ID,			get_device_id },
+-	{ NETFN_APP,	CMD_GET_SELF_TEST_RESULTS,	get_self_test_result }
++	{ NETFN_APP, CMD_GET_DEV_ID, get_device_id},
++	{ NETFN_APP, CMD_GET_SELF_TEST_RESULTS, get_self_test_result},
++	{ NETFN_FIRMWARE, CMD_FWUPD_GET_EXECUTION_CTX, fwupd_get_execution_ctx},
++	{ NETFN_INTEL_OEM, CMD_INTL_OEM_GET_BUFFER_SIZE, intel_get_buffer_size},
++	{ NETFN_INTEL_OEM, CMD_INTL_OEM_GET_SEC_MODE, intel_get_security_mode},
++	{ NETFN_INTEL_OEM, CMD_INTL_OEM_SET_SEC_MODE, intel_set_security_mode}
+ };
+ 
+ #define CMD_TABLE_SIZE ARRAY_SIZE(cmd_info)
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch
index 3d9d50c8d..df26cb5a9 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch
@@ -1,4 +1,4 @@
-From 948a92b3000120f902292b661a544e35d796784a Mon Sep 17 00:00:00 2001
+From 0b1cf63187baba9016fa01df7e58989c80d57465 Mon Sep 17 00:00:00 2001
 From: Kuiying Wang <kuiying.wang@intel.com>
 Date: Mon, 13 Apr 2020 09:30:14 +0800
 Subject: [PATCH] PFR u-boot env changes as per PFR BMC image
@@ -12,10 +12,10 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
  1 file changed, 5 insertions(+), 3 deletions(-)
 
 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
-index 6065ec58db..b13dbd02f3 100644
+index d5befb185b6a..2be63a5c662b 100644
 --- a/include/configs/aspeed-common.h
 +++ b/include/configs/aspeed-common.h
-@@ -64,9 +64,11 @@
+@@ -68,9 +68,11 @@
  #define CONFIG_ENV_SIZE			0x10000
  #endif
  
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
index e61f3de1e..7d64f1584 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
@@ -30,3 +30,8 @@ CONFIG_USB_EHCI_HCD=n
 CONFIG_USB_STORAGE=n
 CONFIG_NETCONSOLE=n
 CONFIG_CMD_NFS=n
+CONFIG_POSITION_INDEPENDENT=n
+CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SPL=n
+CONFIG_ASPEED_DP=n
+CONFIG_PHY_BROADCOM=n
\ No newline at end of file
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
index dd03c1f17..08eb6336e 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
@@ -1,6 +1,8 @@
 COMPATIBLE_MACHINE = "intel-ast2600"
 FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:"
 
+SRCREV = "e1417368fdc3ba45ffde51a4b13290114a643be4"
+
 # the meta-phosphor layer adds this patch, which conflicts
 # with the intel layout for environment
 
@@ -36,6 +38,9 @@ SRC_URI_append_intel-ast2600 = " \
     file://0029-Set-UART-routing-in-lowlevel_init.patch \
     file://0030-Add-Aspeed-PWM-uclass-driver.patch \
     file://0031-Add-a-workaround-to-fix-AST2600-A0-booting-issue.patch \
+    file://0032-Disable-eSPI-initialization-in-u-boot-for-normal-boo.patch \
+    file://0033-Disable-debug-interfaces.patch \
+    file://0034-Implement-the-IPMI-commands-in-FFUJ-mode-in-u-boot.patch \
     "
 
 # CVE-2020-10648 vulnerability fix