Update to internal 0.44

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

24 files changed, 1303 insertions, 107 deletions

diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json
index 71ea74135..80d4606bb 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json
@@ -992,6 +992,18 @@
         },
         {
             "Address": "0x72",
+            "Bus": 7,
+            "ChannelNames": [
+                "PMBusSlot1",
+                "PMBusSlot2",
+                "PMBusSlot3",
+                "PMBusSlot4"
+            ],
+            "Name": "PMBus Mux",
+            "Type": "PCA9544Mux"
+        },
+        {
+            "Address": "0x72",
             "Bus": 2,
             "ChannelNames": [
                 "Pcie_Slot_1",
@@ -1885,6 +1897,6 @@
     },
     "xyz.openbmc_project.Inventory.Item.Board.Motherboard": {
         "ProductId": 157
-},
+    },
     "xyz.openbmc_project.Inventory.Item.System": {}
 }
\ No newline at end of file
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json
index de98c78fa..02929fb33 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json
@@ -627,6 +627,7 @@
                     "I2cAddress": "0xB0",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 0,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -642,6 +643,7 @@
                     "I2cAddress": "0xB2",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 0,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -657,6 +659,7 @@
                     "I2cAddress": "0xB4",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 0,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -672,6 +675,7 @@
                     "I2cAddress": "0xB6",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 0,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -687,6 +691,7 @@
                     "I2cAddress": "0xB8",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 1,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -702,6 +707,7 @@
                     "I2cAddress": "0xBA",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 1,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -717,6 +723,7 @@
                     "I2cAddress": "0xBC",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 1,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -732,6 +739,7 @@
                     "I2cAddress": "0xBE",
                     "I2cbus": "MemoryChannel1",
                     "Imc": 1,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -747,6 +755,7 @@
                     "I2cAddress": "0xB0",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 2,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -762,6 +771,7 @@
                     "I2cAddress": "0xB2",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 2,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -777,6 +787,7 @@
                     "I2cAddress": "0xB4",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 2,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -792,6 +803,7 @@
                     "I2cAddress": "0xB6",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 2,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -807,6 +819,7 @@
                     "I2cAddress": "0xB8",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 3,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -822,6 +835,7 @@
                     "I2cAddress": "0xBA",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 3,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -837,6 +851,7 @@
                     "I2cAddress": "0xBC",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 3,
+                    "Pecibus": "0x30",
                     "Slot": 0,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -852,6 +867,7 @@
                     "I2cAddress": "0xBE",
                     "I2cbus": "MemoryChannel2",
                     "Imc": 3,
+                    "Pecibus": "0x30",
                     "Slot": 1,
                     "Socket": 0,
                     "Spdpcibus": "0x7E",
@@ -867,6 +883,7 @@
                     "I2cAddress": "0xB0",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 0,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -882,6 +899,7 @@
                     "I2cAddress": "0xB2",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 0,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -897,6 +915,7 @@
                     "I2cAddress": "0xB4",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 0,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -912,6 +931,7 @@
                     "I2cAddress": "0xB6",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 0,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -927,6 +947,7 @@
                     "I2cAddress": "0xB8",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 1,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -942,6 +963,7 @@
                     "I2cAddress": "0xBA",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 1,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -957,6 +979,7 @@
                     "I2cAddress": "0xBC",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 1,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -972,6 +995,7 @@
                     "I2cAddress": "0xBE",
                     "I2cbus": "MemoryChannel3",
                     "Imc": 1,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -987,6 +1011,7 @@
                     "I2cAddress": "0xB0",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 2,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1002,6 +1027,7 @@
                     "I2cAddress": "0xB2",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 2,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1017,6 +1043,7 @@
                     "I2cAddress": "0xB4",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 2,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1032,6 +1059,7 @@
                     "I2cAddress": "0xB6",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 2,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1047,6 +1075,7 @@
                     "I2cAddress": "0xB8",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 3,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1062,6 +1091,7 @@
                     "I2cAddress": "0xBA",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 3,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1077,6 +1107,7 @@
                     "I2cAddress": "0xBC",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 3,
+                    "Pecibus": "0x31",
                     "Slot": 0,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1092,6 +1123,7 @@
                     "I2cAddress": "0xBE",
                     "I2cbus": "MemoryChannel4",
                     "Imc": 3,
+                    "Pecibus": "0x31",
                     "Slot": 1,
                     "Socket": 1,
                     "Spdpcibus": "0x7E",
@@ -1102,6 +1134,10 @@
                     "Spdpcistatusregister": "0x84"
                 }
             ],
+            "Interface": [
+                "i2c",
+                "peci"
+            ],
             "Name": "DCPMM",
             "Type": "DCPMM"
         },
@@ -2376,4 +2412,4 @@
         "ProductId": 154
     },
     "xyz.openbmc_project.Inventory.Item.System": {}
-}
\ No newline at end of file
+}
diff --git a/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass b/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass
index 7db3fa4a6..b43933278 100644
--- a/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass
+++ b/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass
@@ -42,6 +42,7 @@ IMAGE_INSTALL_append = " \
         nv-sync \
         security-manager \
         multi-node-nl \
+        mctpd \
         "
 
 IMAGE_INSTALL_append = "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', 'intel-pfr-manager', '', d)}"
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch
new file mode 100644
index 000000000..2ec774144
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch
@@ -0,0 +1,265 @@
+From 8c9e2fffa9ea72ddc8734ee74b30cc62ba06fd3a Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 2 Mar 2020 13:54:50 -0800
+Subject: [PATCH] AST2600: Add the latest chip initialization code
+
+This commit cherry picked the latest chip initialization code from
+Aspped SDK v00.05.05 to support AST2600 A1 revision.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ arch/arm/mach-aspeed/ast2600/Makefile   |   2 +-
+ arch/arm/mach-aspeed/ast2600/cache.c    |  26 +++++++
+ arch/arm/mach-aspeed/ast2600/platform.S | 132 +++++++++++++++++++++++++-------
+ 3 files changed, 130 insertions(+), 30 deletions(-)
+ create mode 100644 arch/arm/mach-aspeed/ast2600/cache.c
+
+diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile
+index b074d4b70a14..2889388fab75 100644
+--- a/arch/arm/mach-aspeed/ast2600/Makefile
++++ b/arch/arm/mach-aspeed/ast2600/Makefile
+@@ -1,2 +1,2 @@
+-obj-y   += platform.o aspeed_scu_info.o
++obj-y   += platform.o aspeed_scu_info.o cache.o
+ obj-$(CONFIG_SPL_BUILD) += spl.o
+diff --git a/arch/arm/mach-aspeed/ast2600/cache.c b/arch/arm/mach-aspeed/ast2600/cache.c
+new file mode 100644
+index 000000000000..82de0b0fda8a
+--- /dev/null
++++ b/arch/arm/mach-aspeed/ast2600/cache.c
+@@ -0,0 +1,26 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) ASPEED Technology Inc.
++ * Chia-Wei Wang <chiawei_wang@aspeedtech.com>
++ */
++
++#include <common.h>
++#include <asm/system.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++void enable_caches(void)
++{
++#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
++	enum dcache_option opt = DCACHE_WRITETHROUGH;
++#else
++	enum dcache_option opt = DCACHE_WRITEBACK;
++#endif
++	/* enable D-cache as well as MMU */
++	dcache_enable();
++
++	/* setup cache attribute for DRAM region */
++	mmu_set_region_dcache_behaviour(ASPEED_DRAM_BASE,
++				       gd->ram_size,
++				       opt);
++}
+diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
+index de97cccc78b7..f1a1f057c09b 100644
+--- a/arch/arm/mach-aspeed/ast2600/platform.S
++++ b/arch/arm/mach-aspeed/ast2600/platform.S
+@@ -26,39 +26,45 @@
+  * +----------------------+ AST_SMP_MAILBOX_BASE
+  */
+ 
+-#define AST_SMP_MAILBOX_BASE		0x1E6E2180
++#define AST_SMP_MAILBOX_BASE		(0x1E6E2180)
+ #define AST_SMP_MBOX_FIELD_ENTRY	(AST_SMP_MAILBOX_BASE + 0x0)
+ #define AST_SMP_MBOX_FIELD_GOSIGN	(AST_SMP_MAILBOX_BASE + 0x4)
+ #define AST_SMP_MBOX_FIELD_READY	(AST_SMP_MAILBOX_BASE + 0x8)
+ #define AST_SMP_MBOX_FIELD_POLLINSN	(AST_SMP_MAILBOX_BASE + 0xc)
+ 
+ /* AST2600 HW registers */
+-#define AST_SCU_BASE		0x1E6E2000
+-#define AST_SCU_PROT_KEY1	(AST_SCU_BASE)
+-#define AST_SCU_PROT_KEY2	(AST_SCU_BASE + 0x010)
+-#define AST_SCU_REV_ID		(AST_SCU_BASE + 0x014)
+-#define AST_SCU_HPLL_PARAM	(AST_SCU_BASE + 0x200)
+-#define AST_SCU_HPLL_PARAM_EXT	(AST_SCU_BASE + 0x204)
+-#define AST_SCU_HW_STRAP1	(AST_SCU_BASE + 0x500)
+-#define AST_SCU_CA7_PARITY_CHK	(AST_SCU_BASE + 0x820)
+-#define AST_SCU_CA7_PARITY_CLR	(AST_SCU_BASE + 0x824)
+-
+-#define AST_FMC_BASE		0x1E620000
++#define AST_SCU_BASE			(0x1E6E2000)
++#define AST_SCU_PROT_KEY1		(AST_SCU_BASE)
++#define AST_SCU_PROT_KEY2		(AST_SCU_BASE + 0x010)
++#define AST_SCU_REV_ID			(AST_SCU_BASE + 0x014)
++#define AST_SCU_SYSRST_CTRL		(AST_SCU_BASE + 0x040)
++#define AST_SCU_SYSRST_CTRL_CLR		(AST_SCU_BASE + 0x044)
++#define AST_SCU_DEBUG_CTRL              (AST_SCU_BASE + 0x0C8)
++#define AST_SCU_DEBUG_CTRL2             (AST_SCU_BASE + 0x0D8)
++#define AST_SCU_HPLL_PARAM		(AST_SCU_BASE + 0x200)
++#define AST_SCU_HPLL_PARAM_EXT		(AST_SCU_BASE + 0x204)
++#define AST_SCU_HW_STRAP1		(AST_SCU_BASE + 0x500)
++#define AST_SCU_HW_STRAP1_CLR		(AST_SCU_BASE + 0x504)
++#define AST_SCU_HW_STRAP2		(AST_SCU_BASE + 0x510)
++#define AST_SCU_HW_STRAP2_CLR		(AST_SCU_BASE + 0x514)
++#define AST_SCU_CA7_CTRL		(AST_SCU_BASE + 0x800)
++#define AST_SCU_CA7_AXI_PREFETCH_START	(AST_SCU_BASE + 0x808)
++#define AST_SCU_CA7_AXI_PREFETCH_END	(AST_SCU_BASE + 0x80C)
++#define AST_SCU_CA7_PARITY_CHK		(AST_SCU_BASE + 0x820)
++#define AST_SCU_CA7_PARITY_CLR		(AST_SCU_BASE + 0x824)
++#define AST_SCU_MMIO_DEC_SET		(AST_SCU_BASE + 0xC24)
++
++#define AST_FMC_BASE		(0x1E620000)
++#define AST_FMC_CE0_CTRL	(AST_FMC_BASE + 0x010)
+ #define AST_FMC_WDT1_CTRL_MODE	(AST_FMC_BASE + 0x060)
+ #define AST_FMC_WDT2_CTRL_MODE	(AST_FMC_BASE + 0x064)
+ 
++#define AST_GPIO_BASE		(0x1E780000)
++#define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
++
+ /* Revision ID */
+ #define REV_ID_AST2600A0	0x05000303
+ 
+-ENTRY(ast_bootmode)
+-	ldr	r1, =AST_SCU_HW_STRAP1
+-	ldr	r0, [r1]
+-	tst	r0, #0x4
+-	moveq	r0, #0x0	@; AST_BOOTMODE_SPI
+-	movne	r0, #0x1	@; AST_BOOTMODE_EMMC
+-	mov	pc, lr
+-ENDPROC(ast_bootmode)
+-
+ .macro scu_unlock
+ 	movw	r0, #0xA8A8
+ 	movt	r0, #0x1688	@; magic key to unlock SCU
+@@ -71,11 +77,19 @@ ENDPROC(ast_bootmode)
+ 
+ .macro timer_init
+ #ifdef CONFIG_FPGA_ASPEED
+-	movw	r0, #0x7840
+-	movt	r0, #0x17D
++	movw	r0, #0xF080
++	movt	r0, #0x2FA
+ #else
+-	movw 	r0, #0x2340
+-	movt	r0, #0x430E
++	ldr	r0, =AST_SCU_REV_ID
++	ldr	r0, [r0]
++
++	ldr	r1, =REV_ID_AST2600A0
++	cmp	r0, r1
++
++	movweq 	r0, #0x32C0
++	movteq	r0, #0x4013
++	movwne	r0, #0x8C00
++	movtne	r0, #0x4786
+ #endif
+ 	mcr	p15, 0, r0, c14, c0, 0	@; update CNTFRQ
+ .endm
+@@ -133,7 +147,7 @@ do_primary_core_setup:
+ 	/* unlock system control unit */
+ 	scu_unlock
+ 
+-	/* tune-up CPU clock for AST2600 A0 */
++	/* identify AST2600 A0/A1 */
+ 	ldr	r0, =AST_SCU_REV_ID
+ 	ldr	r0, [r0]
+ 
+@@ -142,7 +156,7 @@ do_primary_core_setup:
+ 
+ 	bne	0f
+ 
+-	/* setup CPU clocks */
++	/* tune up CPU clocks (A0 only) */
+ 	ldr	r0, =AST_SCU_HW_STRAP1
+ 	ldr	r1, [r0]
+ 	bic	r1, #0x1800
+@@ -150,7 +164,7 @@ do_primary_core_setup:
+ 	str	r1, [r0]
+ 
+ 	ldr	r0, =AST_SCU_HPLL_PARAM
+-	movw	r1, #0x4087
++	movw	r1, #0x4080
+ 	movt	r1, #0x1000
+ 	str	r1, [r0]
+ 
+@@ -163,13 +177,54 @@ wait_lock:
+ 	tst	r1, #0x80000000
+ 	beq	wait_lock
+ 
++	/* skip A1 only area */
++	b 1f
++
+ 0:
++	/* enable AXI prefetch (A1 only) */
++	ldr	r0, =AST_SCU_CA7_AXI_PREFETCH_START
++	ldr r1, =ASPEED_DRAM_BASE
++	str r1, [r0]
++
++	ldr	r0, =AST_SCU_CA7_AXI_PREFETCH_END
++	ldr	r1, =0xFFFFFFFF
++	str r1, [r0]
++
++	ldr	r0, =AST_SCU_CA7_CTRL
++	ldr	r1, [r0]
++	orr	r1, #0x8000
++	str	r1, [r0]
++
++	/* LPC/eSPI mode selection (A1 only) */
++	ldr	r0, =AST_GPIOYZ_DATA_VALUE
++	ldr	r0, [r0]
++	tst	r0, #0x1000
++	beq	1f
++
++	/* switch to LPC mode if GPIOZ[4]=1 */
++	ldr	r0, =AST_SCU_HW_STRAP2
++	ldr	r1, [r0]
++	orr	r1, #0x40
++	str	r1, [r0]
++
++1:
++	/* release display port reset */
++	ldr	r0, =AST_SCU_SYSRST_CTRL_CLR
++	movw	r1, #0x0000
++	movt	r1, #0x3000
++	str	r1, [r0]
++
++	/* MMIO decode setting */
++	ldr	r0, =AST_SCU_MMIO_DEC_SET
++	mov	r1, #0x2000
++	str	r1, [r0]
++
+ 	/* enable cache & SRAM parity check */
+ 	mov	r0, #0
+ 	ldr	r1, =AST_SCU_CA7_PARITY_CLR
+ 	str	r0, [r1]
+ 
+-	mov	r0, #0x11
++	mov	r0, #0x1
+ 	ldr	r1, =AST_SCU_CA7_PARITY_CHK
+ 	str	r0, [r1]
+ 
+@@ -177,8 +232,27 @@ wait_lock:
+ 	mov	r0, #0
+ 	ldr	r1, =AST_FMC_WDT1_CTRL_MODE
+ 	str	r0, [r1]
++#if 0
+ 	ldr	r1, =AST_FMC_WDT2_CTRL_MODE
+ 	str	r0, [r1]
++#endif
++	/* tune up SPI clock */
++	movw	r0, #0x0641
++	movt	r0, #0x203B
++	ldr	r1, =AST_FMC_CE0_CTRL
++	str	r0, [r1]
++
++	/* disable UART-based SoC Debug Interface UART5 and P2A bridge*/
++	ldr     r0, =AST_SCU_DEBUG_CTRL
++	ldr     r1, [r0]
++	orr     r1, #0x03
++	str     r1, [r0]
++
++	/* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */
++	ldr     r0, =AST_SCU_DEBUG_CTRL2
++	ldr     r1, [r0]
++	orr     r1, #0x0A
++	str     r1, [r0]
+ 
+ 	/* relocate mailbox insn. for cpuN polling SMP go signal */
+ 	adrl	r0, mailbox_insn
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch
index fac5a64ef..40336d3dd 100644
--- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch
@@ -1,4 +1,4 @@
-From 74a1399befdb0f7604d116ac8578e7e4004728d8 Mon Sep 17 00:00:00 2001
+From dff3a123b0318f83ecd753eea8945ebdc15fd2f9 Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@linux.intel.com>
 Date: Wed, 14 Nov 2018 10:21:40 -0800
 Subject: [PATCH 1/1] Add espi support
@@ -16,10 +16,10 @@ Signed-off-by: James Feist <james.feist@linux.intel.com>
 ---
  arch/arm/include/asm/arch-aspeed/regs-scu.h |   2 +
  board/aspeed/ast-g5/Makefile                |   2 +
- board/aspeed/ast-g5/ast-g5-espi.c           | 242 ++++++++++++++++++++
+ board/aspeed/ast-g5/ast-g5-espi.c           | 248 ++++++++++++++++++++
  board/aspeed/ast-g5/ast-g5-intel.c          |  16 ++
  board/aspeed/ast-g5/ast-g5.c                |   3 +
- 5 files changed, 265 insertions(+)
+ 5 files changed, 271 insertions(+)
  create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c
  create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c
 
@@ -47,10 +47,10 @@ index df4e63966e..58e0c648f4 100644
  obj-y += ast-g5-irq.o
 diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c
 new file mode 100644
-index 0000000000..dda7ac7cd5
+index 0000000000..5a3ffe7bef
 --- /dev/null
 +++ b/board/aspeed/ast-g5/ast-g5-espi.c
-@@ -0,0 +1,242 @@
+@@ -0,0 +1,248 @@
 +/*
 + * Copyright 2018 Intel Corporation
 + *
@@ -191,55 +191,60 @@ index 0000000000..dda7ac7cd5
 +static int espi_irq_handler(struct pt_regs *regs)
 +{
 +	uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008);
-+
 +	DBG_ESPI("ISR irq_status : 0x%08X\n", irq_status);
 +
++	if (irq_status & AST_ESPI_VW_SYS_EV1) {
++		uint32_t sys1_status = readl(AST_ESPI_BASE + ESPI12C);
++		uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104);
 +
-+	if (irq_status & AST_ESPI_IEN_HW_RST) {
-+	    uint32_t v = readl(AST_ESPI_BASE + ESPI000);
-+	    writel(v & ~ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
-+	    writel(v | ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
-+	    espi_handshake_ack();
++		DBG_ESPI("sys1_status : 0x%08X\n", sys1_status);
++		if (sys1_status & AST_ESPI_SUS_WARN) {
++			DBG_ESPI("SUS WARN ev: %08X\n", sys1_event);
++			if (sys1_event & AST_ESPI_SUS_WARN) {
++				uint32_t v = readl(AST_ESPI_BASE + ESPI104)
++						 | AST_ESPI_SUS_ACK;
++				writel(v, AST_ESPI_BASE + ESPI104);
++			}
++		}
++		writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status
 +	}
 +
 +	if (irq_status & AST_ESPI_VW_SYS_EVT) {
 +		uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C);
 +		uint32_t sys_event = readl(AST_ESPI_BASE + ESPI098);
 +
++		if (!(sys_event & AST_ESPI_SL_BT_STATUS)) {
++			DBG_ESPI("Setting espi slave boot done\n");
++			uint32_t v = readl(AST_ESPI_BASE + ESPI098)
++					| AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE;
++			writel(v, AST_ESPI_BASE + ESPI098);
++		 }
++
 +		DBG_ESPI("sys_status : 0x%08X\n", sys_status);
 +		if (sys_status & AST_ESPI_HOST_RST_WARN) {
-+			DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event);
-+			if (sys_event & AST_ESPI_HOST_RST_WARN) {
-+				uint32_t v = readl(AST_ESPI_BASE + ESPI098)
-+					     | AST_ESPI_HOST_RST_ACK;
-+				writel(v, AST_ESPI_BASE + ESPI098);
-+			}
++				DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event);
++				if (sys_event & AST_ESPI_HOST_RST_WARN) {
++						uint32_t v = readl(AST_ESPI_BASE + ESPI098)
++										| AST_ESPI_HOST_RST_ACK;
++						writel(v, AST_ESPI_BASE + ESPI098);
++				}
 +		}
 +		if (sys_status & AST_ESPI_OOB_RST_WARN) {
 +			DBG_ESPI("OOB_RST_WARN ev: %08X\n", sys_event);
 +			if (sys_event & AST_ESPI_OOB_RST_WARN) {
 +				uint32_t v = readl(AST_ESPI_BASE + ESPI098)
-+					     | AST_ESPI_OOB_RST_ACK;
++							| AST_ESPI_OOB_RST_ACK;
 +				writel(v, AST_ESPI_BASE + ESPI098);
 +			}
 +		}
 +		writel(sys_status, AST_ESPI_BASE + ESPI11C); // clear status
 +	}
 +
-+	if (irq_status & AST_ESPI_VW_SYS_EV1) {
-+		uint32_t sys1_status = readl(AST_ESPI_BASE + ESPI12C);
-+		uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104);
-+
-+		DBG_ESPI("sys1_status : 0x%08X\n", sys1_status);
-+		if (sys1_status & AST_ESPI_SUS_WARN) {
-+			DBG_ESPI("SUS WARN ev: %08X\n", sys1_event);
-+			if (sys1_event & AST_ESPI_SUS_WARN) {
-+				uint32_t v = readl(AST_ESPI_BASE + ESPI104)
-+					     | AST_ESPI_SUS_ACK;
-+				writel(v, AST_ESPI_BASE + ESPI104);
-+			}
-+		}
-+		writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status
++	if (irq_status & AST_ESPI_IEN_HW_RST) {
++		uint32_t v = readl(AST_ESPI_BASE + ESPI000);
++		writel(v & ~ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
++		writel(v | ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
++		espi_handshake_ack();
 +	}
 +
 +	writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status
@@ -255,7 +260,7 @@ index 0000000000..dda7ac7cd5
 +
 +		/* Block flash access from Host */
 +		v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY;
-+		v |= AST_ESPI_FLASH_SW_READ | AST_ESPI_OOB_CHRDY;
++		v |= AST_ESPI_FLASH_SW_READ;
 +		writel(v, AST_ESPI_BASE + ESPI000);
 +
 +		/* Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for
@@ -283,8 +288,9 @@ index 0000000000..dda7ac7cd5
 +		       AST_ESPI_BASE
 +			       + ESPI100); // Enable sysev1 ints for susp warn
 +
-+		writel(AST_ESPI_IEN_SYS_EV | AST_ESPI_IEN_HW_RST,
-+		       AST_ESPI_BASE + ESPI00C); // Enable events
++		writel(AST_ESPI_IEN_SYS_EV | AST_ESPI_IEN_HW_RST
++			   | AST_ESPI_VW_SYS_EV1,
++			   AST_ESPI_BASE + ESPI00C); // Enable events
 +
 +		espi_handshake_ack();
 +
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
index e309f6a98..94a658610 100644
--- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
@@ -1,4 +1,4 @@
-From 899934a036171eb9174e800ba6367b8b8a3e70c4 Mon Sep 17 00:00:00 2001
+From 3f53513c2b16ce2f9a24975cb23b2b58e70ba0f2 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 29 Jan 2020 14:55:44 -0800
 Subject: [PATCH] Override OTP strap settings
@@ -7,33 +7,38 @@ This commit adds settings to override OTP strap.
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- arch/arm/mach-aspeed/ast2600/platform.S | 8 ++++++++
- 1 file changed, 8 insertions(+)
+ arch/arm/mach-aspeed/ast2600/platform.S | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index de97cccc78b7..ab8d10b70b9a 100644
+index 80ba06802acd..e7ae9041093c 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -40,6 +40,7 @@
- #define AST_SCU_HPLL_PARAM	(AST_SCU_BASE + 0x200)
- #define AST_SCU_HPLL_PARAM_EXT	(AST_SCU_BASE + 0x204)
- #define AST_SCU_HW_STRAP1	(AST_SCU_BASE + 0x500)
-+#define AST_SCU_HW_STRAP2	(AST_SCU_BASE + 0x510)
- #define AST_SCU_CA7_PARITY_CHK	(AST_SCU_BASE + 0x820)
- #define AST_SCU_CA7_PARITY_CLR	(AST_SCU_BASE + 0x824)
- 
-@@ -133,6 +134,13 @@ do_primary_core_setup:
+@@ -147,6 +147,26 @@ do_primary_core_setup:
  	/* unlock system control unit */
  	scu_unlock
  
-+	/* enable eSPI and ACPI */
++	/* disable CA7 CPU boot */
++	ldr	r0, =AST_SCU_HW_STRAP1_CLR
++	movw	r1, #0x0001		@; Disable ARM CA7 CPU boot
++	movt	r1, #0x0000
++	str	r1, [r0]
++
++	/* enable eSPI, debug interface and disable UART5 boot*/
++	ldr	r0, =AST_SCU_HW_STRAP2_CLR
++	movw	r1, #0x0040		@; Select eSPI
++	movt	r1, #0x0000
++	orr	r1, #0x0010		@; Enable debug interface
++	orr	r1, #0x0100		@; Disable UART5 boot
++	str	r1, [r0]
++
++	/* enable ACPI */
 +	ldr	r0, =AST_SCU_HW_STRAP2
 +	ldr	r1, [r0]
-+	bic	r1, #0x40		@; Select eSPI
 +	orr	r1, #0x20		@; Enable ACPI
 +	str	r1, [r0]
 +
- 	/* tune-up CPU clock for AST2600 A0 */
+ 	/* identify AST2600 A0/A1 */
  	ldr	r0, =AST_SCU_REV_ID
  	ldr	r0, [r0]
 -- 
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
index bc5d2f415..04496acf7 100644
--- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
@@ -6,6 +6,7 @@ FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:"
 SRC_URI_append_intel-ast2600 = " \
     file://fw_env.config \
     file://intel.cfg \
+    file://0000-AST2600-Add-the-latest-chip-initialization-code.patch \
     file://0001-Add-ast2600-intel-as-a-new-board.patch \
     file://0021-AST2600-Enable-host-searial-port-clock-configuration.patch \
     file://0003-ast2600-intel-layout-environment-addr.patch \
diff --git a/meta-openbmc-mods/meta-common/recipes-core/dropbear/dropbear_%.bbappend b/meta-openbmc-mods/meta-common/recipes-core/dropbear/dropbear_%.bbappend
index 307400322..cfa1d0711 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/dropbear/dropbear_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-core/dropbear/dropbear_%.bbappend
@@ -1,5 +1,22 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += "file://enable-ssh.sh"
+
+add_manual_ssh_enable() {
+   install -d ${D}/usr/share/misc
+   install -m 0755 ${D}/${systemd_unitdir}/system/dropbear@.service ${D}/usr/share/misc/dropbear@.service
+   install -m 0755 ${D}/${systemd_unitdir}/system/dropbear.socket ${D}/usr/share/misc/dropbear.socket
+   install -m 0755 ${WORKDIR}/enable-ssh.sh ${D}${bindir}/enable-ssh.sh
+   # Remove dropbear service and socket by default, if debug-tweaks is disabled
+   rm ${D}/${systemd_unitdir}/system/dropbear@.service
+   rm ${D}/${systemd_unitdir}/system/dropbear.socket
+}
+
 do_install_append() {
-   # Remove dropbear service, if debug-tweaks is disabled
-   ${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'debug-tweaks', '', 'rm ${D}/${systemd_unitdir}/system/dropbear@.service', d)}
+   # Add manual ssh enable script if debug-tweaks is disabled
+   ${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'debug-tweaks', '', 'add_manual_ssh_enable', d)}
 }
 
+FILES_${PN} += "/usr/share/misc"
+SYSTEMD_SERVICE_${PN} += "dropbearkey.service"
+SYSTEMD_SERVICE_${PN}_remove += " ${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'debug-tweaks', '', 'dropbear.socket', d)}"
diff --git a/meta-openbmc-mods/meta-common/recipes-core/dropbear/files/enable-ssh.sh b/meta-openbmc-mods/meta-common/recipes-core/dropbear/files/enable-ssh.sh
new file mode 100755
index 000000000..e97995cc1
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-core/dropbear/files/enable-ssh.sh
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+if [ -e /etc/systemd/system/dropbear@.service ] && \
+   [ -e /etc/systemd/system/sockets.target.wants/dropbear.socket ]
+then
+    echo "SSH is already enabled"
+else
+    cp /usr/share/misc/dropbear@.service /etc/systemd/system/dropbear@.service
+    cp /usr/share/misc/dropbear.socket /etc/systemd/system/dropbear.socket
+    ln -s  /etc/systemd/system/dropbear.socket /etc/systemd/system/sockets.target.wants/dropbear.socket
+    groupmems -g priv-admin -a root
+    systemctl daemon-reload
+    systemctl restart dropbear.socket
+    echo "Enabled SSH service for root user successful"
+fi
diff --git a/meta-openbmc-mods/meta-common/recipes-core/host-error-monitor/host-error-monitor_git.bb b/meta-openbmc-mods/meta-common/recipes-core/host-error-monitor/host-error-monitor_git.bb
index 6b6d58bfc..f70e81fd2 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/host-error-monitor/host-error-monitor_git.bb
+++ b/meta-openbmc-mods/meta-common/recipes-core/host-error-monitor/host-error-monitor_git.bb
@@ -7,11 +7,12 @@ SRC_URI = "git://github.com/Intel-BMC/host-error-monitor.git;protocol=ssh"
 DEPENDS = "boost sdbusplus libgpiod libpeci"
 
 PV = "0.1+git${SRCPV}"
-SRCREV = "4215c9de1b5fc3f86f2a2538f04675fc0ee12086"
+SRCREV = "4b56eb0cd42ac87ae8bfd0b725fc274ee3cbbc36"
 
 S = "${WORKDIR}/git"
 
 SYSTEMD_SERVICE_${PN} += "xyz.openbmc_project.HostErrorMonitor.service"
+SECURITY_CFLAGS_pn-host-error-monitor  = "${SECURITY_NOPIE_CFLAGS}"
 
 # linux-libc-headers guides this way to include custom uapi headers
 CFLAGS_append = " -I ${STAGING_KERNEL_DIR}/include/uapi"
diff --git a/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend b/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend
index eeafa0222..c20a59045 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend
@@ -2,4 +2,4 @@ EXTRA_OECMAKE += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', '-DINTEL_PF
 EXTRA_OECMAKE += "${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'validation-unsecure', '-DBMC_VALIDATION_UNSECURE_FEATURE=ON', '', d)}"
 EXTRA_OECMAKE += "-DUSING_ENTITY_MANAGER_DECORATORS=OFF"
 SRC_URI = "git://github.com/openbmc/intel-ipmi-oem.git"
-SRCREV = "849c319f95bfc5b76b1731cadbf95c24093aa53c"
+SRCREV = "4b1552d890fd091566fa7cf2d559f066a58eaae1"
diff --git a/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service b/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service
index 852027209..f5210dd5b 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service
+++ b/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service
@@ -3,9 +3,9 @@ Description=Overlay sync to NV storage
 
 [Service]
 # Run rsync periodically to sync the overlay to NV storage
-ExecStart=bash -c 'while true; do rsync -a --delete /tmp/.overlay/ /tmp/.rwfs/.overlay; sleep 20; done'
+ExecStart=bash -c 'while true; do rsync -a --delete /tmp/.overlay/ /tmp/.rwfs/.overlay; sync /tmp/.rwfs/.overlay; sleep 10; done'
 # On shutdown, archive the bash history so we don't lose it and run one last sync
-ExecStop=bash -c 'history -a; rsync -a --delete /tmp/.overlay/ /tmp/.rwfs/.overlay'
+ExecStop=bash -c 'history -a; rsync -a --delete /tmp/.overlay/ /tmp/.rwfs/.overlay; sync /tmp/.rwfs/.overlay; sleep 5'
 
 [Install]
 WantedBy=multi-user.target
diff --git a/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend b/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend
index fc1dd5a37..7394e3e59 100644
--- a/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend
@@ -2,4 +2,4 @@ FILESEXTRAPATHS_append := ":${THISDIR}/${PN}"
 
 # Use the latest to support obmc-ikvm properly
 #SRC_URI = "git://github.com/LibVNC/libvncserver"
-SRCREV = "6fa1b219f8b173e292b5a0591986d390e3c86ef5"
+SRCREV = "49880e33ee430d50804f46c307bcadce5b3e3be2"
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
index cc025e1f8..dcc4b887e 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
@@ -1,26 +1,28 @@
-From 733ea1e7c0fd70ce372efcc8250bb2baebd74b68 Mon Sep 17 00:00:00 2001
+From a25d8478847866e823aed2ecd1e360d5685410bf Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@linux.intel.com>
 Date: Tue, 19 Sep 2017 15:55:39 +0800
 Subject: [PATCH] arm: dts: add DTS for Intel ast2600 platforms
 
 Add the DTS file for Intel ast2600-based systems.
 
+Change-Id: Ib0b5358570a967c255a370bf2503cc2f448039bb
 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
 Signed-off-by: Chen Yugang <yugang.chen@linux.intel.com>
 Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 Signed-off-by: arun-pm <arun.p.m@linux.intel.com>
+Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com>
 ---
- arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 497 +++++++++++++++++++++++++
- 1 file changed, 497 insertions(+)
+ .../arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 502 ++++++++++++++++++
+ 1 file changed, 502 insertions(+)
  create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
 
 diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
 new file mode 100644
-index 000000000000..5bc76dd069af
+index 000000000000..d32b0390cd87
 --- /dev/null
 +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
-@@ -0,0 +1,497 @@
+@@ -0,0 +1,502 @@
 +// SPDX-License-Identifier: GPL-2.0+
 +/dts-v1/;
 +
@@ -460,53 +462,58 @@ index 000000000000..5bc76dd069af
 +};
 +
 +&pwm_tacho {
-+	status = "disabled"; /* FIXME: disabled because of bug in driver */
++	status = "okay";
 +	pinctrl-names = "default";
-+	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
-+			 &pinctrl_pwm2_default &pinctrl_pwm3_default
-+			 &pinctrl_pwm4_default &pinctrl_pwm5_default
-+			 &pinctrl_pwm12g1_default &pinctrl_pwm13g1_default
-+			 &pinctrl_pwm14g1_default &pinctrl_pwm15g1_default>;
++	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default
++			&pinctrl_pwm1_default &pinctrl_tach1_default
++			&pinctrl_pwm2_default &pinctrl_tach2_default
++			&pinctrl_pwm3_default &pinctrl_tach3_default
++			&pinctrl_pwm4_default &pinctrl_tach4_default
++			&pinctrl_pwm5_default &pinctrl_tach5_default
++			&pinctrl_pwm12g1_default &pinctrl_tach6_default
++			&pinctrl_pwm13g1_default &pinctrl_tach7_default
++			&pinctrl_pwm14g1_default &pinctrl_tach8_default
++			&pinctrl_pwm15g1_default &pinctrl_tach9_default>; /*pwm 6-11 used for some other functionality*/
 +
 +	fan@0 {
 +		reg = <0x00>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
 +	};
 +	fan@1 {
 +		reg = <0x01>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
++		 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
 +	};
 +	fan@2 {
 +		reg = <0x02>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
 +	};
 +	fan@3 {
 +		reg = <0x03>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x03>;
 +	};
 +	fan@4 {
 +		reg = <0x04>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x04>;
 +	};
 +	fan@5 {
 +		reg = <0x05>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x05>;
 +	};
 +	fan@6 {
 +		reg = <0x06>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x18 0x19>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x06>;
 +	};
 +	fan@7 {
 +		reg = <0x07>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x1A 0x1B>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x07>;
 +	};
 +	fan@8 {
 +		reg = <0x08>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x1C 0x1D>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x08>;
 +	};
 +	fan@9 {
 +		reg = <0x09>;
-+		aspeed,fan-tach-ch = /bits/ 8 <0x1E 0x1F>;
++		aspeed,fan-tach-ch = /bits/ 8 <0x09>;
 +	};
 +};
 +
@@ -519,5 +526,5 @@ index 000000000000..5bc76dd069af
 +	status = "okay";
 +};
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0092-SPI-Quad-IO-driver-support-AST2600.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0092-SPI-Quad-IO-driver-support-AST2600.patch
index dd756edbe..2717d367f 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0092-SPI-Quad-IO-driver-support-AST2600.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0092-SPI-Quad-IO-driver-support-AST2600.patch
@@ -1,4 +1,4 @@
-From 879834a305bd5c0cbf3c60f8fe235cea8783fe35 Mon Sep 17 00:00:00 2001
+From 9f1eea1fb639a0554195e29c488cefb36a04910e Mon Sep 17 00:00:00 2001
 From: arun-pm <arun.p.m@linux.intel.com>
 Date: Tue, 3 Dec 2019 17:22:28 +0530
 Subject: [PATCH] SPI Quad IO driver support AST2600
@@ -114,13 +114,13 @@ index 0805dcab8cb1..305c1940e822 100644
  		chip->ctl = controller->regs + info->ctl0 + cs * 4;
  		chip->cs = cs;
 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
-index 19fe44b0965a..c69ef8b56700 100644
+index 3668a862d37d..50904876cb09 100644
 --- a/drivers/mtd/spi-nor/spi-nor.c
 +++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -2310,7 +2310,12 @@ static const struct flash_info spi_nor_ids[] = {
- 	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- 	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
- 	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+@@ -2315,7 +2315,12 @@ static const struct flash_info spi_nor_ids[] = {
+ 			       SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ 	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
+ 			      SPI_NOR_QUAD_READ) },
 -	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 +	/* Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)'
 +	 * while enabling Quad I/O mode. As this chip is default shipped in platforms, marking it
@@ -132,5 +132,5 @@ index 19fe44b0965a..c69ef8b56700 100644
  	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
  			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
 -- 
-2.17.1
+2.7.4
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch
new file mode 100644
index 000000000..377ec2b36
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch
@@ -0,0 +1,783 @@
+From 0301f9b2bc948069aaad2899e15e6c94a07ca818 Mon Sep 17 00:00:00 2001
+From: Ayushi Smriti <smriti.ayushi@intel.com>
+Date: Mon, 2 Mar 2020 22:51:46 +0530
+Subject: [PATCH] pwm and tach driver changes for ast2600
+
+This commit includes additions/changes in driver code
+to support 9 PWM outputs and 9 fan tachometer inputs for
+ast2600
+
+Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com>
+---
+ drivers/hwmon/aspeed-g6-pwm-tacho.c | 328 +++++++++++++++-------------
+ 1 file changed, 171 insertions(+), 157 deletions(-)
+
+diff --git a/drivers/hwmon/aspeed-g6-pwm-tacho.c b/drivers/hwmon/aspeed-g6-pwm-tacho.c
+index 1894f6ad5edb..1ff788bf1133 100644
+--- a/drivers/hwmon/aspeed-g6-pwm-tacho.c
++++ b/drivers/hwmon/aspeed-g6-pwm-tacho.c
+@@ -64,6 +64,8 @@
+ #define  PWM_RISING_FALLING_BIT			(8)	//pwm falling point bit [7:0]
+ #define  PWM_RISING_RISING_BIT			(0)	//pwm rising point bit [7:0]
+ 
++#define  DEF_PWM_PERIOD	0xff
++
+ #define ASPEED_TACHO_CTRL		0x08	//TACH0 General Register
+ #define ASPEED_TACHO_CTRL_CH(x)			((x * 0x10) + 0x08)
+ #define  TACHO_IER						BIT(31)	//enable tacho interrupt
+@@ -72,8 +74,7 @@
+ #define  TACHO_ENABLE					BIT(28)	//{enable tacho}
+ #define  TACHO_DEBOUNCE_BIT				(26) //{tacho de-bounce}
+ #define  TACHO_DEBOUNCE_MASK			(0x3 << 26) //{tacho de-bounce}
+-#define  TECHIO_EDGE_MASK				(0x3 << 24) //tacho edge}
+-#define  TECHIO_EDGE_BIT				(24) //tacho edge}
++#define  TACHIO_EDGE_BIT				(24) /*tacho edge}*/
+ #define  TACHO_CLK_DIV_T_MASK			(0xf << 20)
+ #define  TACHO_CLK_DIV_BIT				(20)
+ #define  TACHO_THRESHOLD_MASK			(0xfffff)	//tacho threshold bit
+@@ -102,211 +103,183 @@
+ 
+ #define MAX_CDEV_NAME_LEN 16
+ 
++#define DEFAULT_TARGET_PWM_FREQ	25000
++#define DEFAULT_MIN_RPM	2900
++
++#define PWM_FALLING_VALUE	0xff
++
+ struct aspeed_pwm_channel_params {
++	int target_freq;
++	int pwm_freq;
+ 	int load_wdt_rising_falling_pt;
+ 	int load_wdt_selection;		//0: rising , 1: falling
+ 	int load_wdt_enable;
+ 	int	duty_sync_enable;
+ 	int invert_pin;
+-	u8	divide_h;
+-	u8	divide_l;
+-	u8	period;
+ 	u8	rising;
+ 	u8	falling;
+ };
+ 
+ static struct aspeed_pwm_channel_params default_pwm_params[] = {
+ 	[0] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 1,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[1] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[2] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[3] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[4] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[5] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[6] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[7] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[8] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[9] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[10] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[11] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[12] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[13] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[14] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ 	[15] = {
++		.target_freq = 25000,
+ 		.load_wdt_rising_falling_pt = 0x10,
+ 		.load_wdt_selection = 0,
+ 		.load_wdt_enable = 0,
+ 		.duty_sync_enable = 0,
+ 		.invert_pin = 0,
+-		.divide_h = 0x5,
+-		.divide_l = 0x6,
+-		.period = 0x13,	//5% ~~
+ 		.rising = 0x00,
+-		.falling = 0x0a,
++		.falling = PWM_FALLING_VALUE,
+ 	},
+ };
+ 
+@@ -318,125 +291,146 @@ static struct aspeed_pwm_channel_params default_pwm_params[] = {
+  * 11: reserved.
+  */
+ 
++#define F2F_EDGES	0x00
++#define R2R_EDGES	0x01
++#define BOTH_EDGES	0x02
++
+ struct aspeed_tacho_channel_params {
++	u32 min_rpm;
+ 	int limited_inverse;
+ 	u16 threshold;
+ 	u8	tacho_edge;
+ 	u8	tacho_debounce;
+-	u8	divide;
++	u32	divide;
+ };
+ 
+ 
+ static struct aspeed_tacho_channel_params default_tacho_params[] = {
+ 	[0] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[1] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[2] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[3] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[4] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[5] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[6] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[7] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[8] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[9] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[10] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[11] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[12] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[13] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[14] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+ 	[15] = {
++		.min_rpm = 2900,
+ 		.limited_inverse = 0,
+ 		.threshold = 0,
+-		.tacho_edge = 0,
++		.tacho_edge = F2F_EDGES,
+ 		.tacho_debounce = 0,
+ 		.divide = 8,
+ 	},
+@@ -501,29 +495,28 @@ static void aspeed_set_pwm_channel_enable(struct regmap *regmap, u8 pwm_channel,
+ static void aspeed_set_fan_tach_ch_enable(struct aspeed_pwm_tachometer_data *priv, u8 fan_tach_ch,
+ 					  bool enable)
+ {
+-	u32 i = 0, j;
++	u32 i;
+ 	u32 divide_val = 0;
++	u32 target_div;
+ 	u32 reg_value = 0;
+ 
+ 	if(enable) {
+-		//4 ^ n
+-		//check pwm clk and to change tacho devide 25KZ
+-		for(i = 0; i < 12; i++) {
++		/*RPM calculation as per ast2600 datasheet*/
++		target_div = (priv->clk_freq * 60 / priv->tacho_channel[fan_tach_ch].min_rpm * 2) / (0xfffff + 1);
++		if (target_div) {
++			for (i = 0; i < 12; i++) {
++				divide_val = BIT(i) * BIT(i);
++				if (divide_val > target_div)
++					break;
++			}
++		} else {
+ 			divide_val = 1;
+-			for (j = 1; j <= i; j++)
+-				divide_val *= 4;
+-//			printk("i : %d , priv->clk_freq/divide_val %d ",i, priv->clk_freq/divide_val);
+-			if((priv->clk_freq/divide_val) < 250000)
+-				break;
+ 		}
+-		i--;
+-		divide_val = ((1 << i) * (1 << i));
+-//		printk("tacho divide_val %d , i %x max tacho clk %d \n", divide_val, i, priv->clk_freq / divide_val);
+-		priv->tacho_channel[fan_tach_ch].divide = i;
++		priv->tacho_channel[fan_tach_ch].divide = divide_val;
+ 
+ 		reg_value = TACHO_ENABLE |
+-				(priv->tacho_channel[fan_tach_ch].tacho_edge << TECHIO_EDGE_BIT) |
+-				(priv->tacho_channel[fan_tach_ch].divide << TACHO_CLK_DIV_BIT) |
++				(priv->tacho_channel[fan_tach_ch].tacho_edge << TACHIO_EDGE_BIT) |
++				(i << TACHO_CLK_DIV_BIT) |
+ 				(priv->tacho_channel[fan_tach_ch].tacho_debounce << TACHO_DEBOUNCE_BIT);
+ 
+ 		if(priv->tacho_channel[fan_tach_ch].limited_inverse)
+@@ -541,14 +534,28 @@ static void aspeed_set_pwm_channel_fan_ctrl(struct aspeed_pwm_tachometer_data *p
+ 					 u8 index, u8 fan_ctrl)
+ {
+ 	u32 duty_value,	ctrl_value;
++	u32 div_h, div_l, cal_freq;
+ 
+ 	if (fan_ctrl == 0) {
+ 		aspeed_set_pwm_channel_enable(priv->regmap, index, false);
+ 	} else {
+-		duty_value = (priv->pwm_channel[index].period << PWM_PERIOD_BIT) |
+-					(0 << PWM_RISING_RISING_BIT) | (fan_ctrl << PWM_RISING_FALLING_BIT);
++		cal_freq = priv->clk_freq / (DEF_PWM_PERIOD + 1);
++		/*calculate for target frequence*/
++		for (div_l = 0; div_l < 0x100; div_l++) {
++			for (div_h = 0; div_h < 0x10; div_h++) {
++				if ((cal_freq / (BIT(div_h) * (div_l + 1))) < priv->pwm_channel[index].target_freq)
++					break;
++			}
++			if ((cal_freq / (BIT(div_h) * (div_l + 1))) < priv->pwm_channel[index].target_freq)
++				break;
++		}
++
++		priv->pwm_channel[index].pwm_freq = cal_freq / (BIT(div_h) * (div_l + 1));
+ 
+-		ctrl_value = (priv->pwm_channel[index].divide_h << 8) | priv->pwm_channel[index].divide_l;
++		ctrl_value = (div_h << 8) | div_l;
++
++		duty_value = (DEF_PWM_PERIOD << PWM_PERIOD_BIT) |
++					(0 << PWM_RISING_RISING_BIT) | (fan_ctrl << PWM_RISING_FALLING_BIT);
+ 
+ 		if (priv->pwm_channel[index].load_wdt_enable) {
+ 			ctrl_value |= PWM_DUTY_LOAD_AS_WDT_EN;
+@@ -568,13 +575,11 @@ static void aspeed_set_pwm_channel_fan_ctrl(struct aspeed_pwm_tachometer_data *p
+ 	}
+ }
+ 
+-#define BOTH_EDGES 0x02 /* 10b */
+-
+ static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tachometer_data *priv,
+ 				      u8 fan_tach_ch)
+ {
+ 	u32 raw_data, tach_div, clk_source, val;
+-	u8 mode, both;
++	u8 multiplier = 2;
+ 	int i, retries = 3;
+ 
+ 	for(i = 0; i < retries; i++) {
+@@ -587,22 +592,15 @@ static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tachometer_data *priv,
+ 	if(raw_data == 0xfffff)
+ 		return 0;
+ 
+-	tach_div = priv->tacho_channel[fan_tach_ch].divide;
+-	/*
+-	 * We need the mode to determine if the raw_data is double (from
+-	 * counting both edges).
+-	 */
+-	mode = priv->tacho_channel[fan_tach_ch].tacho_edge;
+-	both = (mode & BOTH_EDGES) ? 1 : 0;
+-//	printk("clk %ld, raw_data %x , tach_div %x  both %x \n", priv->clk_freq, raw_data, tach_div, both);
++	raw_data += 1;
++	tach_div = raw_data * (priv->tacho_channel[fan_tach_ch].divide) * (multiplier);
+ 
+-	tach_div = (tach_div * 2) * (0x1 << both);
+ 	clk_source = priv->clk_freq;
+ 
+ 	if (raw_data == 0)
+ 		return 0;
+ 
+-	return (clk_source * 60) / (2 * raw_data * tach_div);
++	return (clk_source / tach_div * 60);
+ 
+ }
+ 
+@@ -614,19 +612,27 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
+ 	int ret;
+ 	struct aspeed_pwm_tachometer_data *priv = dev_get_drvdata(dev);
+ 	long fan_ctrl;
++	u8 org_falling = priv->pwm_channel[index].falling;
+ 
+ 	ret = kstrtol(buf, 10, &fan_ctrl);
+ 	if (ret != 0)
+ 		return ret;
+ 
+-	if (fan_ctrl < 0 || fan_ctrl > priv->pwm_channel[index].period)
++	if (fan_ctrl < 0 || fan_ctrl > DEF_PWM_PERIOD)
+ 		return -EINVAL;
+ 
+ 	if (priv->pwm_channel[index].falling == fan_ctrl)
+ 		return count;
+ 
+ 	priv->pwm_channel[index].falling = fan_ctrl;
+-	aspeed_set_pwm_channel_fan_ctrl(priv, index, fan_ctrl);
++
++	if (fan_ctrl == 0)
++		aspeed_set_pwm_channel_enable(priv->regmap, index, false);
++	else
++		regmap_update_bits(priv->regmap, ASPEED_PWM_DUTY_CYCLE_CH(index), GENMASK(15, 8), (fan_ctrl << PWM_RISING_FALLING_BIT));
++
++	if (org_falling == 0)
++		aspeed_set_pwm_channel_enable(priv->regmap, index, true);
+ 
+ 	return count;
+ }
+@@ -678,40 +684,39 @@ static umode_t fan_dev_is_visible(struct kobject *kobj,
+ 	return a->mode;
+ }
+ 
+-static SENSOR_DEVICE_ATTR(pwm0, 0644,
+-			show_pwm, set_pwm, 0);
+ static SENSOR_DEVICE_ATTR(pwm1, 0644,
+-			show_pwm, set_pwm, 1);
++			show_pwm, set_pwm, 0);
+ static SENSOR_DEVICE_ATTR(pwm2, 0644,
+-			show_pwm, set_pwm, 2);
++			show_pwm, set_pwm, 1);
+ static SENSOR_DEVICE_ATTR(pwm3, 0644,
+-			show_pwm, set_pwm, 3);
++			show_pwm, set_pwm, 2);
+ static SENSOR_DEVICE_ATTR(pwm4, 0644,
+-			show_pwm, set_pwm, 4);
++			show_pwm, set_pwm, 3);
+ static SENSOR_DEVICE_ATTR(pwm5, 0644,
+-			show_pwm, set_pwm, 5);
++			show_pwm, set_pwm, 4);
+ static SENSOR_DEVICE_ATTR(pwm6, 0644,
+-			show_pwm, set_pwm, 6);
++			show_pwm, set_pwm, 5);
+ static SENSOR_DEVICE_ATTR(pwm7, 0644,
+-			show_pwm, set_pwm, 7);
++			show_pwm, set_pwm, 6);
+ static SENSOR_DEVICE_ATTR(pwm8, 0644,
+-			show_pwm, set_pwm, 8);
++			show_pwm, set_pwm, 7);
+ static SENSOR_DEVICE_ATTR(pwm9, 0644,
+-			show_pwm, set_pwm, 9);
++			show_pwm, set_pwm, 8);
+ static SENSOR_DEVICE_ATTR(pwm10, 0644,
+-			show_pwm, set_pwm, 10);
++			show_pwm, set_pwm, 9);
+ static SENSOR_DEVICE_ATTR(pwm11, 0644,
+-			show_pwm, set_pwm, 11);
++			show_pwm, set_pwm, 10);
+ static SENSOR_DEVICE_ATTR(pwm12, 0644,
+-			show_pwm, set_pwm, 12);
++			show_pwm, set_pwm, 11);
+ static SENSOR_DEVICE_ATTR(pwm13, 0644,
+-			show_pwm, set_pwm, 13);
++			show_pwm, set_pwm, 12);
+ static SENSOR_DEVICE_ATTR(pwm14, 0644,
+-			show_pwm, set_pwm, 14);
++			show_pwm, set_pwm, 13);
+ static SENSOR_DEVICE_ATTR(pwm15, 0644,
++			show_pwm, set_pwm, 14);
++static SENSOR_DEVICE_ATTR(pwm16, 0644,
+ 			show_pwm, set_pwm, 15);
+ static struct attribute *pwm_dev_attrs[] = {
+-	&sensor_dev_attr_pwm0.dev_attr.attr,
+ 	&sensor_dev_attr_pwm1.dev_attr.attr,
+ 	&sensor_dev_attr_pwm2.dev_attr.attr,
+ 	&sensor_dev_attr_pwm3.dev_attr.attr,
+@@ -727,6 +732,7 @@ static struct attribute *pwm_dev_attrs[] = {
+ 	&sensor_dev_attr_pwm13.dev_attr.attr,
+ 	&sensor_dev_attr_pwm14.dev_attr.attr,
+ 	&sensor_dev_attr_pwm15.dev_attr.attr,
++	&sensor_dev_attr_pwm16.dev_attr.attr,
+ 	NULL,
+ };
+ 
+@@ -735,40 +741,39 @@ static const struct attribute_group pwm_dev_group = {
+ 	.is_visible = pwm_is_visible,
+ };
+ 
+-static SENSOR_DEVICE_ATTR(fan0_input, 0444,
+-		show_rpm, NULL, 0);
+ static SENSOR_DEVICE_ATTR(fan1_input, 0444,
+-		show_rpm, NULL, 1);
++		show_rpm, NULL, 0);
+ static SENSOR_DEVICE_ATTR(fan2_input, 0444,
+-		show_rpm, NULL, 2);
++		show_rpm, NULL, 1);
+ static SENSOR_DEVICE_ATTR(fan3_input, 0444,
+-		show_rpm, NULL, 3);
++		show_rpm, NULL, 2);
+ static SENSOR_DEVICE_ATTR(fan4_input, 0444,
+-		show_rpm, NULL, 4);
++		show_rpm, NULL, 3);
+ static SENSOR_DEVICE_ATTR(fan5_input, 0444,
+-		show_rpm, NULL, 5);
++		show_rpm, NULL, 4);
+ static SENSOR_DEVICE_ATTR(fan6_input, 0444,
+-		show_rpm, NULL, 6);
++		show_rpm, NULL, 5);
+ static SENSOR_DEVICE_ATTR(fan7_input, 0444,
+-		show_rpm, NULL, 7);
++		show_rpm, NULL, 6);
+ static SENSOR_DEVICE_ATTR(fan8_input, 0444,
+-		show_rpm, NULL, 8);
++		show_rpm, NULL, 7);
+ static SENSOR_DEVICE_ATTR(fan9_input, 0444,
+-		show_rpm, NULL, 9);
++		show_rpm, NULL, 8);
+ static SENSOR_DEVICE_ATTR(fan10_input, 0444,
+-		show_rpm, NULL, 10);
++		show_rpm, NULL, 9);
+ static SENSOR_DEVICE_ATTR(fan11_input, 0444,
+-		show_rpm, NULL, 11);
++		show_rpm, NULL, 10);
+ static SENSOR_DEVICE_ATTR(fan12_input, 0444,
+-		show_rpm, NULL, 12);
++		show_rpm, NULL, 11);
+ static SENSOR_DEVICE_ATTR(fan13_input, 0444,
+-		show_rpm, NULL, 13);
++		show_rpm, NULL, 12);
+ static SENSOR_DEVICE_ATTR(fan14_input, 0444,
+-		show_rpm, NULL, 14);
++		show_rpm, NULL, 13);
+ static SENSOR_DEVICE_ATTR(fan15_input, 0444,
++		show_rpm, NULL, 14);
++static SENSOR_DEVICE_ATTR(fan16_input, 0444,
+ 		show_rpm, NULL, 15);
+ static struct attribute *fan_dev_attrs[] = {
+-	&sensor_dev_attr_fan0_input.dev_attr.attr,
+ 	&sensor_dev_attr_fan1_input.dev_attr.attr,
+ 	&sensor_dev_attr_fan2_input.dev_attr.attr,
+ 	&sensor_dev_attr_fan3_input.dev_attr.attr,
+@@ -784,6 +789,7 @@ static struct attribute *fan_dev_attrs[] = {
+ 	&sensor_dev_attr_fan13_input.dev_attr.attr,
+ 	&sensor_dev_attr_fan14_input.dev_attr.attr,
+ 	&sensor_dev_attr_fan15_input.dev_attr.attr,
++	&sensor_dev_attr_fan16_input.dev_attr.attr,
+ 	NULL
+ };
+ 
+@@ -802,14 +808,14 @@ static void aspeed_create_pwm_channel(struct aspeed_pwm_tachometer_data *priv,
+ }
+ 
+ static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tachometer_data *priv,
+-					   u8 *fan_tach_ch,
+-					   int count)
++					   u8 *fan_tach_ch, int count, u32 min_rpm)
+ {
+ 	u8 val, index;
+ 
+ 	for (val = 0; val < count; val++) {
+ 		index = fan_tach_ch[val];
+ 		priv->fan_tach_present[index] = true;
++		priv->tacho_channel[index].min_rpm = min_rpm;
+ 		aspeed_set_fan_tach_ch_enable(priv, index, true);
+ 	}
+ }
+@@ -906,13 +912,19 @@ static int aspeed_pwm_create_fan(struct device *dev,
+ 			     struct aspeed_pwm_tachometer_data *priv)
+ {
+ 	u8 *fan_tach_ch;
++	u32 fan_min_rpm;
+ 	u32 pwm_channel;
++	u32 target_pwm_freq;
+ 	int ret, count;
+ 
+ 	ret = of_property_read_u32(child, "reg", &pwm_channel);
+ 	if (ret)
+ 		return ret;
+ 
++	ret = of_property_read_u32(child, "aspeed,target_pwm", &target_pwm_freq);
++	if (ret)
++		target_pwm_freq = DEFAULT_TARGET_PWM_FREQ;
++
+ 	aspeed_create_pwm_channel(priv, (u8)pwm_channel);
+ 
+ 	ret = of_property_count_u8_elems(child, "cooling-levels");
+@@ -935,9 +947,11 @@ static int aspeed_pwm_create_fan(struct device *dev,
+ 					fan_tach_ch, count);
+ 	if (ret)
+ 		return ret;
++	ret = of_property_read_u32(child, "aspeed,min_rpm", &fan_min_rpm);
++	if (ret)
++		fan_min_rpm = DEFAULT_MIN_RPM;
+ 
+-	aspeed_create_fan_tach_channel(priv, fan_tach_ch, count);
+-
++	aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, fan_min_rpm);
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend
index b2a81beae..57df89699 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend
@@ -68,6 +68,7 @@ SRC_URI += " \
         file://0092-SPI-Quad-IO-driver-support-AST2600.patch \
         file://0093-ipmi-ipmb_dev_int-add-quick-fix-for-raw-I2C-type-reg.patch \
         file://0094-Return-link-speed-and-duplex-settings-for-the-NCSI-c.patch \
+	file://0095-pwm-and-tach-driver-changes-for-ast2600.patch \
         file://0096-Fix-truncated-WrEndPointConfig-MMIO-command.patch \
         "
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend
index 795d34daf..54b4e1b6b 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend
@@ -1,5 +1,5 @@
 SRC_URI = "git://github.com/openbmc/bmcweb.git"
-SRCREV = "f723d7332bbdd7b0d4fbe4aa730b63dfd8db7eff"
+SRCREV = "363c23022eb3fb0cde577405e8a084a2e819b642"
 
 FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-host_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-host_%.bbappend
index e1311a70d..fc724eb33 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-host_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-host_%.bbappend
@@ -2,7 +2,7 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 PROJECT_SRC_DIR := "${THISDIR}/${PN}"
 
 SRC_URI = "git://github.com/openbmc/phosphor-host-ipmid"
-SRCREV = "86d8bd793968e9251f41dbb8eaea482490e68eb1"
+SRCREV = "3165569a562983cf3c43b0b10c23e7695a031b56"
 
 SRC_URI += "file://phosphor-ipmi-host.service \
             file://0010-fix-get-system-GUID-ipmi-command.patch \
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb b/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb
new file mode 100644
index 000000000..72acf3127
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb
@@ -0,0 +1,26 @@
+SUMMARY = "MCTP Daemon"
+DESCRIPTION = "Implementation of MCTP (DTMF DSP0236)"
+
+LICENSE = "Apache-2.0 | GPLv2"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=e3fc50a88d0a364313df4b21ef20c29e"
+
+SRC_URI = "git://github.com/Intel-BMC/pmci.git;protocol=ssh"
+SRCREV = "df5eba0d1ea5a1e07d24eca95cc9ce5d25819c69"
+
+S = "${WORKDIR}/git/mctpd/"
+
+PV = "1.0+git${SRCPV}"
+
+inherit cmake systemd
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+DEPENDS += " \
+    libmctp \
+    systemd \
+    sdbusplus \
+    phosphor-logging \
+    boost \
+    i2c-tools \
+    "
+SYSTEMD_SERVICE_${PN} = "xyz.openbmc_project.mctpd.service"
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend
index ec101469e..d681a6266 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend
@@ -1,4 +1,4 @@
-SRCREV = "d9d8cafcb1f4096e579188478b88cb8cefca8bd4"
+SRCREV = "883fb3a97b3ac47eab7d69e0841ff38ba5b9b2aa"
 SRC_URI = "git://github.com/openbmc/dbus-sensors.git"
 
 DEPENDS_append = " libgpiod libmctp"
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/0001-Customize-phosphor-watchdog-for-Intel-platforms.patch b/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/0001-Customize-phosphor-watchdog-for-Intel-platforms.patch
index 736431e9e..360ba35f0 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/0001-Customize-phosphor-watchdog-for-Intel-platforms.patch
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/0001-Customize-phosphor-watchdog-for-Intel-platforms.patch
@@ -1,4 +1,4 @@
-From a65701eabcf205203d6363d54730a6a497c0e6fc Mon Sep 17 00:00:00 2001
+From 82f31d1e6096acd4f223f0b0fe0d814c27450022 Mon Sep 17 00:00:00 2001
 From: James Feist <james.feist@linux.intel.com>
 Date: Mon, 17 Jun 2019 12:00:58 -0700
 Subject: [PATCH] Customize phosphor-watchdog for Intel platforms
@@ -16,12 +16,12 @@ Signed-off-by: Ren Yu <yux.ren@intel.com>
 Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
 Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
 ---
- watchdog.cpp | 193 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++---
+ watchdog.cpp | 213 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++---
  watchdog.hpp |  23 ++++++-
- 2 files changed, 206 insertions(+), 10 deletions(-)
+ 2 files changed, 226 insertions(+), 10 deletions(-)
 
 diff --git a/watchdog.cpp b/watchdog.cpp
-index 9090760..68b4246 100644
+index 9090760..079d88e 100644
 --- a/watchdog.cpp
 +++ b/watchdog.cpp
 @@ -1,11 +1,14 @@
@@ -39,7 +39,7 @@ index 9090760..68b4246 100644
  
  namespace phosphor
  {
-@@ -18,10 +21,69 @@ using namespace phosphor::logging;
+@@ -18,10 +21,77 @@ using namespace phosphor::logging;
  using sdbusplus::exception::SdBusError;
  using sdbusplus::xyz::openbmc_project::Common::Error::InternalFailure;
  
@@ -94,6 +94,14 @@ index 9090760..68b4246 100644
 +static constexpr const char* request = "RequestedPowerTransition";
 +} // namespace chassis
 +
++namespace host
++{
++static constexpr const char* busName = "xyz.openbmc_project.State.Host";
++static constexpr const char* path = "/xyz/openbmc_project/state/host0";
++static constexpr const char* interface = "xyz.openbmc_project.State.Host";
++static constexpr const char* request = "RequestedHostTransition";
++} // namespace host
++
 +void Watchdog::powerStateChangedHandler(
 +    const std::map<std::string, std::variant<std::string>>& props)
 +{
@@ -113,7 +121,7 @@ index 9090760..68b4246 100644
  
  void Watchdog::resetTimeRemaining(bool enableWatchdog)
  {
-@@ -102,13 +164,102 @@ uint64_t Watchdog::interval(uint64_t value)
+@@ -102,13 +172,102 @@ uint64_t Watchdog::interval(uint64_t value)
  // Optional callback function on timer expiration
  void Watchdog::timeOutHandler()
  {
@@ -217,7 +225,7 @@ index 9090760..68b4246 100644
  
      auto target = actionTargetMap.find(action);
      if (target == actionTargetMap.end())
-@@ -128,10 +279,11 @@ void Watchdog::timeOutHandler()
+@@ -128,10 +287,23 @@ void Watchdog::timeOutHandler()
  
          try
          {
@@ -225,15 +233,27 @@ index 9090760..68b4246 100644
 -                                              SYSTEMD_INTERFACE, "StartUnit");
 -            method.append(target->second);
 -            method.append("replace");
-+            auto method =
-+                bus.new_method_call(chassis::busName, chassis::path,
-+                                    "org.freedesktop.DBus.Properties", "Set");
-+            method.append(chassis::interface, chassis::request,
-+                          std::variant<std::string>(target->second));
++            sdbusplus::message::message method;
++            if (action == Watchdog::Action::HardReset)
++            {
++                method = bus.new_method_call(host::busName, host::path,
++                                             "org.freedesktop.DBus.Properties",
++                                             "Set");
++                method.append(host::interface, host::request,
++                              std::variant<std::string>(target->second));
++            }
++            else
++            {
++                method = bus.new_method_call(chassis::busName, chassis::path,
++                                             "org.freedesktop.DBus.Properties",
++                                             "Set");
++                method.append(chassis::interface, chassis::request,
++                              std::variant<std::string>(target->second));
++            }
  
              bus.call_noreply(method);
          }
-@@ -142,6 +294,29 @@ void Watchdog::timeOutHandler()
+@@ -142,6 +314,29 @@ void Watchdog::timeOutHandler()
                              entry("ERROR=%s", e.what()));
              commit<InternalFailure>();
          }
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/phosphor-watchdog.service b/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/phosphor-watchdog.service
index 5ef1a4179..007e39d8a 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/phosphor-watchdog.service
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/watchdog/phosphor-watchdog/phosphor-watchdog.service
@@ -4,7 +4,7 @@ Description=Phosphor Watchdog
 [Service]
 ExecStart=/usr/bin/env phosphor-watchdog --continue --service=xyz.openbmc_project.Watchdog \
          --path=/xyz/openbmc_project/watchdog/host0 \
-         --action_target=xyz.openbmc_project.State.Watchdog.Action.HardReset=xyz.openbmc_project.State.Chassis.Transition.Reset \
+         --action_target=xyz.openbmc_project.State.Watchdog.Action.HardReset=xyz.openbmc_project.State.Host.Transition.ForceWarmReboot \
          --action_target=xyz.openbmc_project.State.Watchdog.Action.PowerOff=xyz.openbmc_project.State.Chassis.Transition.Off \
          --action_target=xyz.openbmc_project.State.Watchdog.Action.PowerCycle=xyz.openbmc_project.State.Chassis.Transition.PowerCycle
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend
index e16e658a1..e4e24c3d0 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend
@@ -1,2 +1,2 @@
 SRC_URI = "git://github.com/Intel-BMC/phosphor-webui;protocol=ssh;branch=intel2"
-SRCREV = "68c48ed0e48f57bf3092bc5a5bd4b8ac336a4d93"
+SRCREV = "d342b21139c40528a70a2e25c1a00fab7116441a"