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| author | jmbills <jason.m.bills@intel.com> | 2022-01-18 21:55:05 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-18 21:55:05 +0300 |
| commit | 7cf0c1cd0ce835d1833509b7b911e8a97380278b (patch) | |
| tree | 0b45c3beaa9874facc4ed1a2395a31e42be0135d /meta-phosphor/aspeed-layer/recipes-bsp | |
| parent | 4dac5fcd49b5e2de1074f1363775ec0f19041072 (diff) | |
| parent | 1fc0d70f658da30091bcd49f9bf29aecd6b99ba7 (diff) | |
| download | openbmc-7cf0c1cd0ce835d1833509b7b911e8a97380278b.tar.xz | |
Merge pull request #76 from Intel-BMC/update1-0.86
Update
Diffstat (limited to 'meta-phosphor/aspeed-layer/recipes-bsp')
| -rw-r--r-- | meta-phosphor/aspeed-layer/recipes-bsp/u-boot/files/0006-aspeed-Enable-SPI-master-mode-by-default.patch | 34 | ||||
| -rw-r--r-- | meta-phosphor/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed.inc | 4 |
2 files changed, 37 insertions, 1 deletions
diff --git a/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/files/0006-aspeed-Enable-SPI-master-mode-by-default.patch b/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/files/0006-aspeed-Enable-SPI-master-mode-by-default.patch new file mode 100644 index 000000000..bdb9a0c8f --- /dev/null +++ b/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/files/0006-aspeed-Enable-SPI-master-mode-by-default.patch @@ -0,0 +1,34 @@ +From 7947dbbfb21e10e8fb0f852a14485cedf5df1d36 Mon Sep 17 00:00:00 2001 +From: Chanh Nguyen <chanh@os.amperecomputing.com> +Date: Sun, 10 Oct 2021 11:57:20 +0700 +Subject: [PATCH] aspeed: Enable SPI master mode by default + +The ast2500 share the RGMII1 pin and the hw strap pins +for SPI interface mode selection ( pin[12:13] ). +In some systems, the RGMII/NCSI interface will use the pin. +It makes the SPI interface mode setting is not correct. + +This patch will enable the SPI master mode by default. + +Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> +--- + board/aspeed/ast-g5/ast-g5.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index e67a4bf8b2..82e9f81acc 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -21,6 +21,9 @@ int board_init(void) + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->flags = 0; + ++ //pin switch by trap[13:12] -- [0:1] Enable SPI Master ++ ast_scu_spi_master(1); /* enable SPI master */ ++ + return 0; + } + +-- +2.17.1 + diff --git a/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed.inc b/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed.inc index 69b50d6d2..5a0b7e66f 100644 --- a/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed.inc +++ b/meta-phosphor/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed.inc @@ -15,7 +15,9 @@ SRC_URI:append:aspeed:df-isolate-bmc = " \ SRC_URI:append:aspeed:df-aspeednic-use-mac2 = " \ file://0002-board-aspeed-aspeednic-Use-MAC2-for-networking.patch \ " - +SRC_URI:append:aspeed:df-aspeed-spi-master = " \ + file://0006-aspeed-Enable-SPI-master-mode-by-default.patch \ + " do_patch[depends] += "os-release:do_populate_sysroot" python do_patch:append:aspeed:df-obmc-ubi-fs () { |