diff options
Diffstat (limited to 'meta-nuvoton')
8 files changed, 561 insertions, 2 deletions
diff --git a/meta-nuvoton/conf/machine/include/npcm7xx.inc b/meta-nuvoton/conf/machine/include/npcm7xx.inc index 3d8847dc4..0a154678d 100644 --- a/meta-nuvoton/conf/machine/include/npcm7xx.inc +++ b/meta-nuvoton/conf/machine/include/npcm7xx.inc @@ -11,6 +11,17 @@ UBOOT_MACHINE ?= "PolegSVB_config" UBOOT_ENTRYPOINT ?= "0x00008000" UBOOT_LOADADDRESS ?= "0x00008000" +FLASH_UBOOT_OFFSET = "0" +FLASH_UBOOT_ENV_OFFSET = "1024" +FLASH_KERNEL_OFFSET = "2048" +FLASH_UBI_OFFSET = "${FLASH_KERNEL_OFFSET}" +FLASH_ROFS_OFFSET = "7680" +FLASH_RWFS_OFFSET = "30720" + +# UBI volume sizes in KB unless otherwise noted. +FLASH_UBI_RWFS_SIZE = "6144" +FLASH_UBI_RWFS_TXT_SIZE = "6MiB" + DEFAULTTUNE ?= "arm7a-novfp" SERIAL_CONSOLES = "115200;ttyS3" diff --git a/meta-nuvoton/recipes-bsp/images/files/BootBlockAndHeader_EB.xml b/meta-nuvoton/recipes-bsp/images/files/BootBlockAndHeader_EB.xml new file mode 100644 index 000000000..03deb3026 --- /dev/null +++ b/meta-nuvoton/recipes-bsp/images/files/BootBlockAndHeader_EB.xml @@ -0,0 +1,276 @@ +<!-- SPDX-License-Identifier: GPL-2.0 +# +# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC +# +# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved +#---------------------------------------------------------------------------> + +<?xml version="1.0" encoding="UTF-8"?> + +<Bin_Ecc_Map> + <!-- BMC mandatory fields --> + <ImageProperties> + <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool --> + <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 --> + </ImageProperties> + + <BinField> + <!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or + uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) --> + <name>StartTag</name> <!-- name of field --> + <config> + <offset>0</offset> + <size>0x8</size> + </config> + <content format='bytes'>0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Code destination address, 32-bit aligned: for BootBlock should be 0xFFFD5E00 so code will run in 0xFFFD6000 as linked for --> + <name>DestAddr</name> <!-- name of field --> + <config> + <offset>0x140</offset> + <size>0x4</size> + </config> + <content format='32bit'>0xFFFD5E00</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- BootBlock or u-boot Code size --> + <name>CodeSize</name> <!-- name of field --> + <config> + <offset>0x144</offset> + <size>0x4</size> + </config> + <content format='FileSize'>Poleg_bootblock.bin</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- The BootBlock or u-boot binary file --> + <name>Code</name> <!-- name of field --> + <config> + <offset>0x200</offset> + <size format='FileSize'>Poleg_bootblock.bin</size> <!-- size in the header calculated by tool--> + </config> + <content format='FileContent'>Poleg_bootblock.bin</content> <!-- content the user should fill --> + </BinField> + + <!-- BMC optional fields --> + <BinField> + <!-- Word contents copied by ROM code to FIU0 FIU_DRD_CFG register --> + <name>FIU0_DRD_CFG_Set</name> <!-- name of field --> + <config> + <offset>0x108</offset> + <size>0x4</size> + </config> + <content format='32bit'>0x030011BB</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines the clock divide ratio from AHB to FIU0 clock --> + <name>FIU_Clk_Divider</name> <!-- name of field --> + <config> + <offset>0x10C</offset> + <size>0x1</size> + </config> + <content format='bytes'>4</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Version (Major.Minor) --> + <name>Version</name> <!-- name of field --> + <config> + <offset>0x148</offset> + <size>0x4</size> + </config> + <content format='32bit'>0x0201</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Board manufaturer ( Dell = 0, Nuvoton = 100, Google = 1, MS = 2) --> + <name>BOARD_VENDOR</name> <!-- name of field --> + <config> + <offset>0x14C</offset> + <size>0x4</size> + </config> + <content format='32bit'>100</content> <!--Board_manufacturer: Nuvoton--> + </BinField> + <BinField> + <!-- Board type ( DRB = 0, SVB = 1, EB = 2,HORIZON = 3, SANDSTORM = 4, ROCKAWAY = 100 RunBMC = 10) --> + <!-- WARNING: Currently this value is only printed to serial. Set BOARD_VENDOR to 1 get Dell specific customization. --> + <name>BOARD_TYPE</name> <!-- name of field --> + <config> + <offset>0x150</offset> + <size>0x4</size> + </config> + <content format='32bit'>0x02</content> <!--Board_type: EB--> + </BinField> + + <!-- the next two fields are available since version 10.7.0 --> + <BinField> + <!-- supported values: 333,444,500,600,666,700,720,750,775,787,800,825,850,900,950,1000,1060 --> + <name>MC_FREQ_IN_MHZ</name> <!-- name of field --> + <config> + <offset>0x11C</offset> + <size>0x2</size> + </config> + <content format='32bit'>800</content> + </BinField> + <BinField> + <!-- supporeted values: 333,500,600,666,700,720,750,800,825,850,900,950,1000,1060 --> + <name>CPU_FREQ_IN_MHZ</name> <!-- name of field --> + <config> + <offset>0x154</offset> + <size>0x2</size> + </config> + <content format='32bit'>800</content> + </BinField> + + <BinField> + <!-- MC_CONFIG. + Bit 0: MC_DISABLE_CAPABILITY_INPUT_DQS_ENHANCE_TRAINING (0x01) + Bit 1: MC_CAPABILITY_IGNORE_ECC_DEVICE (0x02) --> + <name>MC_CONFIG</name> <!-- name of field --> + <config> + <offset>0x156</offset> + <size>0x1</size> + </config> + <content format='32bit'>0x00</content> + </BinField> + + <BinField> + <!-- HOST_IF. + 0xFF: LPC backward compatible + 0x00: LPC. + 0x01: eSPI + 0x02: GPIOs TRIS. --> + <name>HOST_IF</name> <!-- name of field --> + <config> + <offset>0x157</offset> + <size>0x1</size> + </config> + <content format='32bit'>0x00</content> + </BinField> + + <BinField> + <!-- SECURITY_LEVEL_T. + 0xFF: SECURITY_LEVEL_UNKNOWN: backward compatible + 0x00: SECURITY_LEVEL_NONE. + 0x01: SECURITY_LEVEL_STANDARD + 0x02: SECURITY_LEVEL_NIST. (require BootBlock with NIST support) --> + <name>SECURITY_LEVEL_T</name> <!-- name of field --> + <config> + <offset>0x15C</offset> + <size>0x1</size> + </config> + <content format='32bit'>0xFF</content> + </BinField> + + <BinField> + <!-- Key revoke (bitwise). Set bit 0 to revoke key 0 etc. --> + <name>SECURITY_REVOKE_KEYS</name> <!-- name of field --> + <config> + <offset>0x1D7</offset> + <size>0x1</size> + </config> + <content format='bytes'>0x00</content> + </BinField> + + <BinField> + <!-- security log offset --> + <name>SECURITY_LOG</name> <!-- name of field --> + <config> + <offset>0x1D8</offset> + <size>0x4</size> + </config> + <content format='32bit'>0x090000</content> + </BinField> + <BinField> + <!-- hole 0 size: used for NIST security. --> + <name>SECURITY_LOG_SIZE</name> <!-- name of field --> + <config> + <offset>0x1DC</offset> + <size>0x4</size> + </config> + <content format='32bit'>0x3000</content> + </BinField> + + + <BinField> + <!-- hole 0: used for NIST security. --> + <name>HOLE0</name> <!-- name of field --> + <config> + <offset>0x1E0</offset> + <size>0x4</size> + </config> + <content format='32bit'>0x0A0000</content> + </BinField> + <BinField> + <!-- hole 0 size: used for NIST security. --> + <name>HOLE0_SIZE</name> <!-- name of field --> + <config> + <offset>0x1E4</offset> + <size>0x4</size> + </config> + <content format='32bit'>0xF70000</content> + </BinField> + + <BinField> + <!-- hole 1: used for NIST security. --> + <name>HOLE1</name> <!-- name of field --> + <config> + <offset>0x1E8</offset> + <size>0x4</size> + </config> + <content format='32bit'>0</content> + </BinField> + <BinField> + <!-- hole 1 size: used for NIST security. --> + <name>HOLE1_SIZE</name> <!-- name of field --> + <config> + <offset>0x1EC</offset> + <size>0x4</size> + </config> + <content format='32bit'>0</content> + </BinField> + + + <BinField> + <!-- hole 2: used for NIST security. --> + <name>HOLE2</name> <!-- name of field --> + <config> + <offset>0x1F0</offset> + <size>0x4</size> + </config> + <content format='32bit'>0xFFFFFFFF</content> + </BinField> + <BinField> + <!-- hole 2 size: used for NIST security. --> + <name>HOLE2_SIZE</name> <!-- name of field --> + <config> + <offset>0x1F4</offset> + <size>0x4</size> + </config> + <content format='32bit'>0</content> + </BinField> + + <BinField> + <!-- hole 3: used for NIST security. --> + <name>HOLE3</name> <!-- name of field --> + <config> + <offset>0x1F8</offset> + <size>0x4</size> + </config> + <content format='32bit'>0</content> + </BinField> + <BinField> + <!-- hole 3 size: used for NIST security. --> + <name>HOLE3_SIZE</name> <!-- name of field --> + <config> + <offset>0x1FC</offset> + <size>0x4</size> + </config> + <content format='32bit'>0</content> + </BinField> + +</Bin_Ecc_Map> diff --git a/meta-nuvoton/recipes-bsp/images/files/UbootHeader_EB.xml b/meta-nuvoton/recipes-bsp/images/files/UbootHeader_EB.xml new file mode 100644 index 000000000..2e648599b --- /dev/null +++ b/meta-nuvoton/recipes-bsp/images/files/UbootHeader_EB.xml @@ -0,0 +1,194 @@ +<!-- SPDX-License-Identifier: GPL-2.0 +# +# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC +# +# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved +#---------------------------------------------------------------------------> + +<?xml version="1.0" encoding="UTF-8"?> + +<Bin_Ecc_Map> + <!-- BMC mandatory fields --> + <ImageProperties> + <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool --> + <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 --> + </ImageProperties> + + <BinField> + <!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or + uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) --> + <name>StartTag</name> <!-- name of field --> + <config> + <offset>0</offset> <!-- offset in the header --> + <size>0x8</size> <!-- size in the header --> + </config> + <content format='bytes'>0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Code destination address, 32-bit aligned: for u-boot should be 0x80005000 so code will run in 0x80005200 as linked for --> + <name>DestAddr</name> <!-- name of field --> + <config> + <offset>0x140</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='32bit'>0x8000</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- BootBlock or u-boot Code size --> + <name>CodeSize</name> <!-- name of field --> + <config> + <offset>0x144</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='FileSize'>u-boot.bin</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- The BootBlock or u-boot binary file --> + <name>Code</name> <!-- name of field --> + <config> + <offset>0x200</offset> <!-- offset in the header --> + <size format='FileSize'>u-boot.bin</size> <!-- size in the header calculated by tool--> + </config> + <content format='FileContent'>u-boot.bin</content> <!-- content the user should fill --> + </BinField> + + <!-- BMC optional fields --> + <BinField> + <!-- Word contents copied by ROM code to FIU0 FIU_DRD_CFG register --> + <name>FIU0_DRD_CFG_Set</name> <!-- name of field --> + <config> + <offset>0x108</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='32bit'>0x030111BC</content> <!-- content the user should fill 0x030032EB --> + </BinField> + + <BinField> + <!-- Defines the clock divide ratio from AHB to FIU0 clock --> + <name>FIU0_Clk_Divider</name> <!-- name of field --> + <config> + <offset>0x10C</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines if FIU0 CS1 is enabled --> + <name>fiu0_cs1_en</name> <!-- name of field --> + <config> + <offset>0x10D</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines if FIU0 CS2 is enabled --> + <name>fiu0_cs2_en</name> <!-- name of field --> + <config> + <offset>0x10E</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines if FIU0 CS3 is enabled --> + <name>fiu0_cs3_en</name> <!-- name of field --> + <config> + <offset>0x10F</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + <!-- BMC optional fields --> + <BinField> + <!-- Word contents copied by ROM code to FIU3 FIU_DRD_CFG register --> + <name>FIU3_DRD_CFG_Set</name> <!-- name of field --> + <config> + <offset>0x110</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='32bit'>0x0</content> <!-- content the user should fill --> + </BinField> + + <!-- BMC optional fields --> + <BinField> + <!-- Word contents copied by ROM code to FIU3 FIU_DRD_CFG register --> + <name>FIU3_DWR_CFG_Set</name> <!-- name of field --> + <config> + <offset>0x114</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='32bit'>0x0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines the clock divide ratio from AHB to FIU3 clock --> + <name>FIU3_Clk_Divider</name> <!-- name of field --> + <config> + <offset>0x118</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + + <BinField> + <!-- Defines if FIU3 CS1 is enabled --> + <name>fiu3_cs1_en</name> <!-- name of field --> + <config> + <offset>0x119</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines if FIU3 CS2 is enabled --> + <name>fiu3_cs2_en</name> <!-- name of field --> + <config> + <offset>0x11A</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Defines if FIU3 CS3 is enabled --> + <name>fiu3_cs3_en</name> <!-- name of field --> + <config> + <offset>0x11B</offset> <!-- offset in the header --> + <size>0x1</size> <!-- size in the header --> + </config> + <content format='bytes'>0x0</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <!-- Version (Major.Minor) --> + <name>Version</name> <!-- name of field --> + <config> + <offset>0x148</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='32bit'>0</content> <!-- content the user should fill --> + </BinField> + + <!-- BMC optional fields --> + <BinField> + <!-- Word contents copied by BB code to FIU0 FIU_DWR_CFG register --> + <name>FIU0_DWR_CFG_Set</name> <!-- name of field --> + <config> + <offset>0x14C</offset> <!-- offset in the header --> + <size>0x4</size> <!-- size in the header --> + </config> + <content format='32bit'>0x03001102</content> <!-- content the user should fill --> + </BinField> + + +</Bin_Ecc_Map> diff --git a/meta-nuvoton/recipes-bsp/images/files/mergedBootBlockAndUboot.xml b/meta-nuvoton/recipes-bsp/images/files/mergedBootBlockAndUboot.xml new file mode 100644 index 000000000..03529dcac --- /dev/null +++ b/meta-nuvoton/recipes-bsp/images/files/mergedBootBlockAndUboot.xml @@ -0,0 +1,35 @@ +<!-- SPDX-License-Identifier: GPL-2.0 +# +# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC +# +# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved +#---------------------------------------------------------------------------> + +<?xml version="1.0" encoding="UTF-8"?> + +<Bin_Ecc_Map> + <!-- BMC mandatory fields --> + <ImageProperties> + <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool --> + <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 --> + </ImageProperties> + + <BinField> + <name>BootBlock</name> <!-- name of field --> + <config> + <offset>0</offset> <!-- offset in the header --> + <size format='FileSize'>Poleg_bootblock.bin.full</size> <!-- size in the header --> + </config> + <content format='FileContent'>Poleg_bootblock.bin.full</content> <!-- content the user should fill --> + </BinField> + + <BinField> + <name>u-boot</name> <!-- name of field --> + <config> + <offset format='FileSize' align='0x1000'>Poleg_bootblock.bin.full</offset> <!-- offset in the header --> + <size format='FileSize'>u-boot.bin.full</size> <!-- size in the header --> + </config> + <content format='FileContent'>u-boot.bin.full</content> <!-- content the user should fill --> + </BinField> + +</Bin_Ecc_Map> diff --git a/meta-nuvoton/recipes-bsp/images/npcm7xx-bingo-native.bb b/meta-nuvoton/recipes-bsp/images/npcm7xx-bingo-native.bb new file mode 100644 index 000000000..1ce19433c --- /dev/null +++ b/meta-nuvoton/recipes-bsp/images/npcm7xx-bingo-native.bb @@ -0,0 +1,20 @@ +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263" + +SRC_URI += "git://github.com/Nuvoton-Israel/bingo" +SRC_URI += "file://BootBlockAndHeader_EB.xml" +SRC_URI += "file://UbootHeader_EB.xml" +SRC_URI += "file://mergedBootBlockAndUboot.xml" + +SRCREV = "4f102ff7851da9fd11965857edd1b3046c187b7a" + +S = "${WORKDIR}/git" + +do_install () { + + install -d "${D}${bindir}" + install deliverables/linux/Release/bingo ${D}${bindir} + install ${WORKDIR}/*.xml ${D}${bindir} +} + +inherit native diff --git a/meta-nuvoton/recipes-bsp/images/npcm7xx-bootblock.bb b/meta-nuvoton/recipes-bsp/images/npcm7xx-bootblock.bb new file mode 100644 index 000000000..85b80708d --- /dev/null +++ b/meta-nuvoton/recipes-bsp/images/npcm7xx-bootblock.bb @@ -0,0 +1,19 @@ +LICENSE = "CLOSED" +LIC_FILES_CHKSUM = "" + +SRCREV = "10.09.05" +FILENAME = "Poleg_bootblock.bin" + +SRC_URI = "git://github.com/Nuvoton-Israel/npcm7xx-bootblock;protocol=git" +SRC_URI[md5sum] = "cf8daa5f4636ed1ff952618e435af028" + +S = "${WORKDIR}/git" + +inherit deploy + +do_deploy () { + install -d ${DEPLOYDIR} + install -m 644 ${FILENAME} ${DEPLOYDIR}/ +} + +addtask deploy before do_build after do_compile diff --git a/meta-nuvoton/recipes-kernel/linux/linux-nuvoton/defconfig b/meta-nuvoton/recipes-kernel/linux/linux-nuvoton/defconfig index e5b6cdf43..207ec6691 100644 --- a/meta-nuvoton/recipes-kernel/linux/linux-nuvoton/defconfig +++ b/meta-nuvoton/recipes-kernel/linux/linux-nuvoton/defconfig @@ -99,7 +99,11 @@ CONFIG_USB_EDM_KBD_MOUSE=m CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_NPCM750=y +CONFIG_EDAC=y +# CONFIG_EDAC_LEGACY_SYSFS is not set +CONFIG_EDAC_NPCM7XX=y CONFIG_IIO=y +CONFIG_RAS=y CONFIG_NPCM_ADC=y CONFIG_IIO_MUX=y CONFIG_MUX_MMIO=y diff --git a/meta-nuvoton/recipes-kernel/linux/linux-nuvoton_git.bb b/meta-nuvoton/recipes-kernel/linux/linux-nuvoton_git.bb index b0c34a71f..aaef9bca8 100644 --- a/meta-nuvoton/recipes-kernel/linux/linux-nuvoton_git.bb +++ b/meta-nuvoton/recipes-kernel/linux/linux-nuvoton_git.bb @@ -1,6 +1,6 @@ KBRANCH ?= "dev-5.1" -LINUX_VERSION ?= "5.1" +LINUX_VERSION ?= "5.1.7" -SRCREV="f869c3d0aad419af31719d2eaf6b2e42a6d68109" +SRCREV="a17b8ac585d7faa27799f425fa4326c7a1e7ae71" require linux-nuvoton.inc |