diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT-reset-mask-to-reset-needed-controller.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT-reset-mask-to-reset-needed-controller.patch | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT-reset-mask-to-reset-needed-controller.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT-reset-mask-to-reset-needed-controller.patch new file mode 100644 index 000000000..b68975c40 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT-reset-mask-to-reset-needed-controller.patch @@ -0,0 +1,78 @@ +From 5179bc2cba159b9167fee90a2c6a7ea2824df8ad Mon Sep 17 00:00:00 2001 +From: Suryakanth Sekar <suryakanth.sekar@linux.intel.com> +Date: Thu, 18 Jun 2020 05:32:48 +0530 +Subject: [PATCH] Apply WDT reset mask to reset needed controller + +Issue: +Whenever BIOS and BMC warm reset happens at a time. +BIOS is not booting. + +Root caused: +BMC resetting the LPC controller during BMC warm reset. +Which cause BIOS hang as BIOS cannot dump the BIOS serial data. + +Fix: +WDT reset mask has been updated from default to proper value, +such that controllers interacting with host will not be reset +during wdt reset operation. +This was missed earlier, causing BIOS to hang whenever BMC resets, +as BIOS was accessing the serial port (LPC controller). +De-coupling LPC controller will make sure BIOS serial port access +is not disturbed. +Reset mask is updated not to reset the following controllers +additionally on the default mask setting. +1. LPC controller +2. PWM controller +3. GPIO controller + +Quick Step to reproduce: +Stop the BMC in uboot and add below bootcmd command +setenv bootcmd "reset" +Do the System power ON or System warm reset. + +Tested: +1. Ran overnight continous BIOS and BMC warm reset on two SUTs. + +2. Ran the TestApp which dump the BIOS serial port continously and +do the BMC reset. + +3. Stop the BMC in uboot and add below bootcmd command +setenv bootcmd "reset" +Do the System Power ON or System warm reset. + +Signed-off-by: Suryakanth Sekar <suryakanth.sekar@linux.intel.com> +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/ast2600/platform.S | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S +index d881ba8565f2..68eb0000922a 100644 +--- a/arch/arm/mach-aspeed/ast2600/platform.S ++++ b/arch/arm/mach-aspeed/ast2600/platform.S +@@ -66,6 +66,9 @@ + #define AST_MAC2_BASE (0x1E680000) + #define AST_MAC2_CTRL2 (AST_MAC2_BASE + 0x058) + ++#define AST_WDT1_BASE 0x1E785000 ++#define AST_WDT1_RESET_MASK2 (AST_WDT1_BASE + 0x020) ++ + #define AST_GPIO_BASE (0x1E780000) + #define AST_GPIOYZ_DATA_VALUE (AST_GPIO_BASE + 0x1E0) + +@@ -264,6 +267,12 @@ wait_lock: + str r1, [r0] + + 1: ++ /* disable LPC, PWM and GPIO2 resets on WDT1 reset */ ++ ldr r0, =AST_WDT1_RESET_MASK2 ++ ldr r1, [r0] ++ bic r1, #0x2A00 ++ str r1, [r0] ++ + /* release display port reset */ + ldr r0, =AST_SCU_SYSRST_CTRL_CLR + movw r1, #0x0000 +-- +2.7.4 + |