diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files')
3 files changed, 125 insertions, 3 deletions
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch index 67123645d..b400aae9e 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch @@ -5,7 +5,7 @@ Subject: [PATCH] IPMI command handler implementation in uboot IPMI command handler implementation in uBoot. Implemented IPMI commands: - 1) Get Device ID + 1) Get Device ID with default Product ID=0 2) Get Self Test Result Tested By: @@ -13,7 +13,7 @@ Ran the above IPMI command Via KCS channel and got proper response. - Get Device ID Req: ipmitool raw 6 1 - Res: 00 23 00 82 03 02 00 57 01 00 7b 00 00 00 00 00 + Res: 00 23 00 82 03 02 00 57 01 00 00 00 00 00 00 00 - Get Self Test Results Req: ipmitool raw 6 4 Res: 56 00 @@ -205,7 +205,7 @@ index 000000000000..04732846ac28 + /* Get Device ID */ + bool operation = 1; /* Firmware operation */ + u8 intel_mfg_id[3] = { 0x57, 0x01, 0x00 }; -+ u8 platform_id[2] = { 0x7B, 0x00 }; ++ u8 platform_id[2] = { 0x00, 0x00 }; + u8 aux_fw_rev[4] = { 0x00, 0x00, 0x00, 0x00 }; + struct get_dev_id *result = (struct get_dev_id *)res; + diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0044-Enable-WDT2-for-causing-reset-in-Kernel-u-boot-hang.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0044-Enable-WDT2-for-causing-reset-in-Kernel-u-boot-hang.patch new file mode 100644 index 000000000..a79fc6e85 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0044-Enable-WDT2-for-causing-reset-in-Kernel-u-boot-hang.patch @@ -0,0 +1,77 @@ +From 6a5cf930c34fe2ba29fa3361b07ae42e1e1a66d3 Mon Sep 17 00:00:00 2001 +From: AKSHAY RAVEENDRAN K <akshay.raveendran.k@intel.com> +Date: Mon, 11 Apr 2022 12:24:33 +0000 +Subject: [PATCH] Enable WDT2 for causing reset in Kernel/u-boot hang + +In the current implementation, WDT1 is enabled as the reset reason +for u-boot/kernel hang recovery. This fix changes the watchdog timer from +WDT1 to WDT2 for the u-boot/kernel hang or panic as WDT2 is expected +here. + +Along with this fix, panic time out value is changed from "-1" to "0" in +kernel configuration file. Which will make the system remain in hang +instead of rebooting immediately. This will allow WDT2 to complete the +time out period and trigger the reset. + +Tested: +1. Triggered a kernel panic using "echo c > /proc/sysrq-trigger" command +and confirmed the reset reason is WDT2 reset. +2. After 3 kernel panics the BMC is booted to u-boot prompt +3. The normal BMC resets(ipmitool raw 6 2) are caused by WDT1 only as +expected. + +Signed-off-by: AKSHAY RAVEENDRAN K <akshay.raveendran.k@intel.com> +--- + arch/arm/dts/ast2600-intel.dts | 2 +- + arch/arm/mach-aspeed/ast2600/platform.S | 11 +++++++---- + 2 files changed, 8 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts +index dba62fd254..b894be2a64 100644 +--- a/arch/arm/dts/ast2600-intel.dts ++++ b/arch/arm/dts/ast2600-intel.dts +@@ -98,7 +98,7 @@ + + &wdt1 { + u-boot,dm-pre-reloc; +- status = "okay"; ++ status = "disabled"; + }; + + &wdt2 { +diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S +index cc1d6b7a61..967c255cd5 100644 +--- a/arch/arm/mach-aspeed/ast2600/platform.S ++++ b/arch/arm/mach-aspeed/ast2600/platform.S +@@ -78,6 +78,9 @@ + #define AST_WDT1_RESET_MASK2 (AST_WDT1_BASE + 0x020) + + #define AST_WDT2_BASE 0x1E785040 ++#define AST_WDT2_RELOAD_VAL (AST_WDT2_BASE + 0x004) ++#define AST_WDT2_RESTART_CTRL (AST_WDT2_BASE + 0x008) ++#define AST_WDT2_CTRL (AST_WDT2_BASE + 0x00C) + #define AST_WDT2_RESET_MASK1 (AST_WDT2_BASE + 0x01C) + #define AST_WDT2_RESET_MASK2 (AST_WDT2_BASE + 0x020) + +@@ -388,14 +391,14 @@ wait_lock: + str r0, [r1] + + #ifdef CONFIG_HW_WATCHDOG +- /* Enable WDT1 to recover u-boot hang */ +- ldr r0, =AST_WDT1_RELOAD_VAL ++ /* Enable WDT2 to recover u-boot hang */ ++ ldr r0, =AST_WDT2_RELOAD_VAL + ldr r1, =0x00500000 @ ~5 seconds + str r1, [r0] +- ldr r0, =AST_WDT1_RESTART_CTRL ++ ldr r0, =AST_WDT2_RESTART_CTRL + ldr r1, =0x00004755 + str r1, [r0] +- ldr r0, =AST_WDT1_CTRL ++ ldr r0, =AST_WDT2_CTRL + ldr r1, =0x00000013 + str r1, [r0] + #endif +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0045-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0045-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch new file mode 100644 index 000000000..5c2b307f3 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0045-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch @@ -0,0 +1,45 @@ +From 59dc87adc78cfcc2a4dba57a777c1c46ef6cd4d8 Mon Sep 17 00:00:00 2001 +From: AKSHAY RAVEENDRAN K <akshay.raveendran.k@intel.com> +Date: Tue, 19 Apr 2022 06:25:32 +0000 +Subject: [PATCH] PFR- Skip counting WDT2 event when EXTRST# is set + +when a kernel/u-boot panic or hang occurs the WDT2 will trigger a BMC +reset and it will increase bootfailure count. If the bootfailure count +is more than 3, the u-boot will abort the booting to BMC. This fix will +remove the bootfailure count incrementing if PFR is provisioned as PFR +CPLD will boot a recovery image anyway if the booting process is not +working as expected and stopping in u-boot is not necessary. + +Tested: +triggered kernel panic 4 times and confirmed that boot process +is not aborted at u-boot in PFR provisioned mode. + +Signed-off-by: AKSHAY RAVEENDRAN K <akshay.raveendran.k@intel.com> +--- + board/aspeed/ast2600_intel/intel.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c +index c0d82bfb4b..5a54051ac7 100644 +--- a/board/aspeed/ast2600_intel/intel.c ++++ b/board/aspeed/ast2600_intel/intel.c +@@ -13,6 +13,7 @@ + #define SYS_PWR_RESET_FLAG BIT(0) /* from scu_info.c */ + #define WATCHDOG_RESET_BIT BIT(20) + #define BOOT_FAILURE_LIMIT 3 ++#define EXTRST_RESET_BIT BIT(1) + + #define SCU_014 0x014 /* Silicon Revision ID */ + #define REV_ID_AST2600A0 0x05000303 /* AST2600 A0 */ +@@ -703,7 +704,7 @@ int board_late_init(void) + + boot_failures = get_boot_failures(); + +- if (gd->reset_reason & WATCHDOG_RESET_BIT) ++ if ((gd->reset_reason & WATCHDOG_RESET_BIT) && !(gd->reset_reason & EXTRST_RESET_BIT)) + set_boot_failures(boot_failures + 1); + else + set_boot_failures(0); +-- +2.17.1 + |