74 files changed, 1894 insertions, 452 deletions
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
index 5d29531d2..28247daa2 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
@@ -1,7 +1,7 @@
-From 7fbf19ba660c72a1d4817780cad5c4ae52cbe0b5 Mon Sep 17 00:00:00 2001
+From 23e6126392ab228c1d6483c02ffc32b15f00777e Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 13:13:57 +0530
-Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic
+Subject: [PATCH 01/63] LOCAL]: Testsuite - builtins tests require fpic
  Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 
 Conflicts:
@@ -12,7 +12,7 @@ Conflicts:
  1 file changed, 8 insertions(+)
 
 diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 9f0b24a..1cb4f97 100644
+index acb9eac..363ce07 100644
 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 @@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
index 503b1ecf9..8e4a2a323 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
@@ -1,7 +1,7 @@
-From 4b675eeabceea22ec51abfa7c37e11a631e58659 Mon Sep 17 00:00:00 2001
+From e9c8884f473eae307945ceabaa1ff03278236c23 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 14:31:10 +0530
-Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
+Subject: [PATCH 02/63] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
  particular testcase fails with a timeout. Instead, fail it at compile-time
  for microblaze. This speeds up the testsuite without removing it from the
  FAIL reports.
@@ -12,7 +12,7 @@ Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
  1 file changed, 4 insertions(+)
 
 diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C
-index 66411cd..d951fee 100644
+index 3862756..db9f990 100644
 --- a/gcc/testsuite/g++.dg/opt/memcpy1.C
 +++ b/gcc/testsuite/g++.dg/opt/memcpy1.C
 @@ -4,6 +4,10 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
index 390584968..ef9944570 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
@@ -1,11 +1,14 @@
-From 03d4d7335be2b2f72c199ab5177685b6dfd1a9d6 Mon Sep 17 00:00:00 2001
+From fb4b4d4ecba04859d52a653d7c453df92014dc38 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 15:28:38 +0530
-Subject: [PATCH 03/54] [LOCAL]: Testsuite - explicitly add -fivopts for tests
+Subject: [PATCH 03/63] [LOCAL]: Testsuite - explicitly add -fivopts for tests
  that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt
  exist in 4.6 branch)
 
 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+Conflicts:
+	gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
 ---
  gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
  gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
@@ -79,13 +82,13 @@ index 5f42857..9bc86ee 100644
  void foo(long);
  
 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-index 0fa5600..94caa44 100644
+index 50d86a0..1e3eacd 100644
 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
 +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
 @@ -1,5 +1,5 @@
  /* { dg-do compile } */
--/* { dg-options "-O2 -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */
-+/* { dg-options "-O2 -fivopts -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */
+-/* { dg-options "-O2 -fopt-info-loop-missed" } */
++/* { dg-options "-O2 -fivopts -fopt-info-loop-missed" } */
  extern void g(void);
  
  void
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
index e16528b6b..a575b518e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
@@ -1,7 +1,7 @@
-From a4c99f7f7775f105eb6f1dfbdf304e6b7e498e2e Mon Sep 17 00:00:00 2001
+From 38022a87b01cf2e36b605d4f6d0faab22a0d2f44 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 15:46:28 +0530
-Subject: [PATCH 04/54] [LOCAL]: For dejagnu static testing on qemu, suppress
+Subject: [PATCH 04/63] [LOCAL]: For dejagnu static testing on qemu, suppress
  warnings about multiple definitions from the test function and libc in line
  with method used by powerpc. Dynamic linking and using a qemu binary which
  understands sysroot resolves all test failures with builtins
@@ -12,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 4 deletions(-)
 
 diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 1cb4f97..bdfa08a 100644
+index 363ce07..56b1a9a 100644
 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 @@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
index 33688f143..18fd6decd 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
@@ -1,7 +1,7 @@
-From 6b0de6811796b6834d426263eaa855b65c9b3389 Mon Sep 17 00:00:00 2001
+From a7dfb5f158f16f88b30aabe903c4fb088889eeef Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 15:50:35 +0530
-Subject: [PATCH 05/54] [Patch, testsuite]: Add MicroBlaze to target-supports
+Subject: [PATCH 05/63] [Patch, testsuite]: Add MicroBlaze to target-supports
  for atomic buil. .tin tests
 
 MicroBlaze added to supported targets for atomic builtin tests.
@@ -19,10 +19,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index c591acd..94353cc 100644
+index cda0f3d..0a69659e 100644
 --- a/gcc/testsuite/lib/target-supports.exp
 +++ b/gcc/testsuite/lib/target-supports.exp
-@@ -7428,6 +7428,7 @@ proc check_effective_target_sync_int_long { } {
+@@ -6829,6 +6829,7 @@ proc check_effective_target_sync_int_long { } {
  		 && [check_effective_target_arm_acq_rel])
  	     || [istarget bfin*-*linux*]
  	     || [istarget hppa*-*linux*]
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
index b428d121c..b428d121c 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
index 3e2368f27..e4a86dc4e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
@@ -1,7 +1,7 @@
-From 0d2cca275f3e85ae42dac7888d862975d65ffb36 Mon Sep 17 00:00:00 2001
+From e23b1a424cfd852f7a33f29c0b80d867ca533c3b Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 16:20:01 +0530
-Subject: [PATCH 06/54] [Patch, testsuite]: Update MicroBlaze strings test for
+Subject: [PATCH 06/63] [Patch, testsuite]: Update MicroBlaze strings test for
  new scan-assembly output resulting in use of $LC label
 
 ChangeLog/testsuite
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
index bcd5dbade..8c43de053 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
@@ -1,7 +1,7 @@
-From b6f828da3caa827d8ccc08bbf260a2a01b2b2613 Mon Sep 17 00:00:00 2001
+From c210044f15df2433438b6b74e5c2bcf79458c2e4 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:14:15 +0530
-Subject: [PATCH 07/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
+Subject: [PATCH 07/63] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
  in regex match Extend regex pattern to include optional ext at the end of
  .weak to match the MicroBlaze weak label .weakext
 
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
index 6232535d2..d02be316f 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
@@ -1,7 +1,7 @@
-From d27a2545486da9c6a4d3d5ca06b4affb83f8d0a1 Mon Sep 17 00:00:00 2001
+From 283d8576d2599b3c38814e7c70e3f36ed51df9da Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:34:27 +0530
-Subject: [PATCH 08/54] [Patch, testsuite]: Add MicroBlaze to
+Subject: [PATCH 08/63] [Patch, testsuite]: Add MicroBlaze to
  check_profiling_available Testsuite, add microblaze*-*-* target in
  check_profiling_available inline with other archs setting
  profiling_available_saved to 0
@@ -12,10 +12,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index 94353cc..ecfbe4d 100644
+index 0a69659e..d47819c 100644
 --- a/gcc/testsuite/lib/target-supports.exp
 +++ b/gcc/testsuite/lib/target-supports.exp
-@@ -676,6 +676,7 @@ proc check_profiling_available { test_what } {
+@@ -678,6 +678,7 @@ proc check_profiling_available { test_what } {
  	     || [istarget m68k-*-elf]
  	     || [istarget m68k-*-uclinux*]
  	     || [istarget mips*-*-elf*]
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
index db730f438..ae24c0805 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
@@ -1,7 +1,7 @@
-From 8711bdfe27bce04d35ba93a1d18ccccd61371829 Mon Sep 17 00:00:00 2001
+From 1905061b279e6fe5fd9861fc490fd4075edac4a8 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:41:43 +0530
-Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In
+Subject: [PATCH 09/63] [Patch, microblaze]: Fix atomic side effects. In
  atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
  during optimization. Previously, the outputs were considered unused; this
  generated assembly code with undefined side effects after invocation of the
@@ -9,19 +9,22 @@ Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In
 
 Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
 ---
  gcc/config/microblaze/microblaze.md |  3 +++
  gcc/config/microblaze/sync.md       | 21 +++++++++++++--------
  2 files changed, 16 insertions(+), 8 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index f698e54..93f5fa2 100644
+index 183afff..7a40c53 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -41,6 +41,9 @@
-   (UNSPEC_CMP		104)    ;; signed compare
-   (UNSPEC_CMPU		105)    ;; unsigned compare
+@@ -43,6 +43,9 @@
    (UNSPEC_TLS           106)    ;; jump table
+   (UNSPEC_SET_TEXT      107)    ;; set text start
+   (UNSPEC_TEXT          108)    ;; data text relative
 +  (UNSPECV_CAS_BOOL     201)    ;; compare and swap (bool)
 +  (UNSPECV_CAS_VAL      202)    ;; compare and swap (val)
 +  (UNSPECV_CAS_MEM      203)    ;; compare and swap (mem)
@@ -29,7 +32,7 @@ index f698e54..93f5fa2 100644
  
  (define_c_enum "unspec" [
 diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index b34bd54..8e694e9 100644
+index 6f16ca6..bebab5c 100644
 --- a/gcc/config/microblaze/sync.md
 +++ b/gcc/config/microblaze/sync.md
 @@ -18,14 +18,19 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
index 5058529ad..07a431774 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
@@ -1,7 +1,7 @@
-From 92015c19e5d1baabd62067bf1cfc4522e85d1b25 Mon Sep 17 00:00:00 2001
+From 65bc1969bd652df4bf9d01d30547a947da293550 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:45:45 +0530
-Subject: [PATCH 10/54] [Patch, microblaze]: Fix atomic boolean return value.
+Subject: [PATCH 10/63] [Patch, microblaze]: Fix atomic boolean return value.
  In atomic_compare_and_swapsi, fix boolean return value. Previously, it
  contained zero if successful and non-zero if unsuccessful.
 
@@ -12,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 4 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index 8e694e9..8ddb10d 100644
+index bebab5c..72eac09 100644
 --- a/gcc/config/microblaze/sync.md
 +++ b/gcc/config/microblaze/sync.md
 @@ -34,15 +34,16 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
index 2451c9385..b9ba239f3 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
@@ -1,7 +1,7 @@
-From 658476aef537c0c2d031eb1c7a001f00c1d9bf7b Mon Sep 17 00:00:00 2001
+From 4e4409f10b450ec9254e69445ffeb8d116906d16 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:50:17 +0530
-Subject: [PATCH 11/54] [Patch, microblaze]: Fix the Microblaze crash with
+Subject: [PATCH 11/63] [Patch, microblaze]: Fix the Microblaze crash with
  msmall-divides flag Compiler is crashing when we use msmall-divides and
  mxl-barrel-shift flag. This is because when use above flags
  microblaze_expand_divide function will be called for division operation. In
@@ -15,10 +15,10 @@ Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
  1 file changed, 1 insertion(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 9a4a287..cbe8cb7 100644
+index 55c1bec..ae45038 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3575,8 +3575,7 @@ microblaze_expand_divide (rtx operands[])
+@@ -3715,8 +3715,7 @@ microblaze_expand_divide (rtx operands[])
    mem_rtx = gen_rtx_MEM (QImode,
                              gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
index b58df8731..fc47bae6a 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
@@ -1,7 +1,7 @@
-From 64f1a238641616c9cca5823d7ca99e76a7c2a490 Mon Sep 17 00:00:00 2001
+From 6dbeb53f0185dd587ece39d624d193768633a7ab Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:52:56 +0530
-Subject: [PATCH 12/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
+Subject: [PATCH 12/63] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
  ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
  optimization is used. lshrsi3_with_size_opt is being removed as it has
  conflicts with unsigned int variables
@@ -12,10 +12,10 @@ Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
  1 file changed, 21 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 93f5fa2..fe90a14 100644
+index 7a40c53..3d2636e 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -1506,6 +1506,27 @@
+@@ -1508,6 +1508,27 @@
    (set_attr "length"	"4,4")]
  )
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
index 6af0f10e2..3b4b4c708 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
@@ -1,7 +1,7 @@
-From ed23e22fb25a2d3dc357c0743f51b2735fc46a6a Mon Sep 17 00:00:00 2001
+From 53ab5a3fec283aeb9d2efeb632d423b774192e65 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 17:50:03 +0530
-Subject: [PATCH 13/54] [Patch, microblaze]: Fixed missing save of r18 in
+Subject: [PATCH 13/63] [Patch, microblaze]: Fixed missing save of r18 in
  fast_interrupt. Register 18 is used as a clobber register, and must be stored
  when entering a fast_interrupt. Before this fix, register 18 was only saved
  if it was used directly in the interrupt function.
@@ -24,10 +24,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index cbe8cb7..6f0b4f4 100644
+index ae45038..c834b49 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -1967,7 +1967,7 @@ microblaze_must_save_register (int regno)
+@@ -2043,7 +2043,7 @@ microblaze_must_save_register (int regno)
      {
        if (df_regs_ever_live_p (regno) 
  	  || regno == MB_ABI_MSR_SAVE_REG
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
index f47265b07..889a1e69a 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
@@ -1,7 +1,7 @@
-From 582558f3c18d096885ab24e645899f310b148b5c Mon Sep 17 00:00:00 2001
+From cbf1854e3569122ee1143e6716ff68275c26aced Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 10:57:19 +0530
-Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls
+Subject: [PATCH 14/63] [Patch, microblaze]: Use bralid for profiler calls
  Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 0d3718f..88e0351 100644
+index fa0806e..0a435b8 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -486,7 +486,7 @@ typedef struct microblaze_args
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0015-Patch-microblaze-Disable-fivopts-by-default.patch
index acfa083f2..0ada80eb7 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0015-Patch-microblaze-Disable-fivopts-by-default.patch
@@ -1,7 +1,7 @@
-From b60068cbdd3c830e541fbd35f2ed119245911461 Mon Sep 17 00:00:00 2001
+From 604cae83ce9d2942568178966f69614acbbcbefd Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 11:10:21 +0530
-Subject: [PATCH 15/54] [Patch, microblaze]: Disable fivopts by default Turn
+Subject: [PATCH 15/63] [Patch, microblaze]: Disable fivopts by default Turn
  off ivopts by default. Interferes with cse.
 
 Changelog
@@ -18,7 +18,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 9 insertions(+)
 
 diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 3e75675..fe45f2e 100644
+index c30bdef..9b6ef21 100644
 --- a/gcc/common/config/microblaze/microblaze-common.c
 +++ b/gcc/common/config/microblaze/microblaze-common.c
 @@ -24,6 +24,15 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0016-Patch-microblaze-Removed-moddi3-routinue.patch
index dbd7b2e2c..87bc16686 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0016-Patch-microblaze-Removed-moddi3-routinue.patch
@@ -1,10 +1,13 @@
-From 640628680ff6f028ad6d5fef2e41da29664f036f Mon Sep 17 00:00:00 2001
+From 14ddb3217fbb84c48903124ec6a3614b4707630d Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 17:36:16 +0530
-Subject: [PATCH 16/54] [Patch, microblaze]: Removed moddi3 routinue Using the
+Subject: [PATCH 16/63] [Patch, microblaze]: Removed moddi3 routinue Using the
  default moddi3 function as the existing implementation has many bugs
 
 Signed-off-by:Nagaraju <nmekala@xilix.com>
+
+Conflicts:
+	libgcc/config/microblaze/moddi3.S
 ---
  libgcc/config/microblaze/moddi3.S     | 121 ----------------------------------
  libgcc/config/microblaze/t-microblaze |   3 +-
@@ -13,13 +16,13 @@ Signed-off-by:Nagaraju <nmekala@xilix.com>
 
 diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
 deleted file mode 100644
-index a8f17d7..0000000
+index abfe4fc..0000000
 --- a/libgcc/config/microblaze/moddi3.S
 +++ /dev/null
 @@ -1,121 +0,0 @@
 -###################################
 -# 
--#  Copyright (C) 2009-2018 Free Software Foundation, Inc.
+-#  Copyright (C) 2009-2019 Free Software Foundation, Inc.
 -#
 -#  Contributed by Michael Eager <eager@eagercon.com>.
 -#
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
index 6fb1b32fe..ca1c2d1c3 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
@@ -1,7 +1,7 @@
-From c0e74b79cc1db2f68dd560154225da1e5ddfd920 Mon Sep 17 00:00:00 2001
+From 032e50c1b267306338cff4d136db88f08350de72 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 14:41:58 +0530
-Subject: [PATCH 17/54] [Patch, microblaze]: Add INIT_PRIORITY support Added
+Subject: [PATCH 17/63] [Patch, microblaze]: Add INIT_PRIORITY support Added
  TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
 
 These macros allows users to control the order of initialization
@@ -26,10 +26,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 53 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 6f0b4f4..53b44df 100644
+index c834b49..c54b96b 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2554,6 +2554,53 @@ print_operand_address (FILE * file, rtx addr)
+@@ -2642,6 +2642,53 @@ print_operand_address (FILE * file, rtx addr)
      }
  }
  
@@ -83,7 +83,7 @@ index 6f0b4f4..53b44df 100644
  /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
     is used, so that we don't emit an .extern for it in 
     microblaze_asm_file_end.  */
-@@ -3841,6 +3888,12 @@ microblaze_starting_frame_offset (void)
+@@ -3981,6 +4028,12 @@ microblaze_starting_frame_offset (void)
  #undef TARGET_ATTRIBUTE_TABLE
  #define TARGET_ATTRIBUTE_TABLE          microblaze_attribute_table
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
index ab2473a37..de35f2860 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
@@ -1,7 +1,7 @@
-From 2cba68c3e27ffaea77cc5469233cf4dcb9383142 Mon Sep 17 00:00:00 2001
+From 6db9d068e32a424ac04c27e963d1e58cb3ef8bdf Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 15:23:57 +0530
-Subject: [PATCH 18/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel
+Subject: [PATCH 18/63] [Patch, microblaze]: Add optimized lshrsi3 When barrel
  shifter is not present, the immediate value is greater than #5 and
  optimization is -OS, the compiler will generate shift operation using loop.
 
@@ -26,10 +26,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index fe90a14..c063ffc 100644
+index 3d2636e..aa2eda3 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -1616,6 +1616,27 @@
+@@ -1618,6 +1618,27 @@
    (set_attr "length"	"4,4")]
  )
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0019-Patch-microblaze-Modified-trap-instruction.patch
index 5afcff434..dc9b61cf2 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0019-Patch-microblaze-Modified-trap-instruction.patch
@@ -1,7 +1,7 @@
-From e8b05b5105655d276c93864ab90e15bfbe46cf74 Mon Sep 17 00:00:00 2001
+From 614bacc058b94c7b12cd40fde1b19b4709870f3b Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 15:42:15 +0530
-Subject: [PATCH 19/54] [Patch, microblaze]: Modified trap instruction The
+Subject: [PATCH 19/63] [Patch, microblaze]: Modified trap instruction The
  instruction was wrongly written to brki r0,-1 it should be bri r0. Modified
  with the correct instruction
 
@@ -12,10 +12,10 @@ Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index c063ffc..7bbdbe1 100644
+index aa2eda3..3c80760 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2344,7 +2344,7 @@
+@@ -2348,7 +2348,7 @@
  (define_insn "trap"
    [(trap_if (const_int 1) (const_int 0))]
    ""
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
index 6e07ac4fc..b60a4e95b 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
@@ -1,7 +1,7 @@
-From 0cc6aabbd3f7b331c3995f11efec545499297358 Mon Sep 17 00:00:00 2001
+From 372bbc75146166df9b82ca5e8f236971b7cef16e Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 16:42:44 +0530
-Subject: [PATCH 20/54] [Patch, microblaze]: Reducing Stack space for arguments
+Subject: [PATCH 20/63] [Patch, microblaze]: Reducing Stack space for arguments
  Currently in Microblaze target stack space for arguments in register is being
  allocated even if there are no arguments in the function. This patch will
  optimize the extra 24 bytes that are being allocated.
@@ -22,10 +22,10 @@ ChangeLog:
  3 files changed, 136 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 4cbba0c..f8a56f7 100644
+index 1f5ca80..6647cbc 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -58,6 +58,7 @@ extern int symbol_mentioned_p (rtx);
+@@ -59,6 +59,7 @@ extern int symbol_mentioned_p (rtx);
  extern int label_mentioned_p (rtx);
  extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
  extern void microblaze_eh_return (rtx op0);
@@ -34,10 +34,10 @@ index 4cbba0c..f8a56f7 100644
  
  /* Declare functions in microblaze-c.c.  */
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 53b44df..0dec362 100644
+index c54b96b..0ce9d13 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -1989,6 +1989,138 @@ microblaze_must_save_register (int regno)
+@@ -2065,6 +2065,138 @@ microblaze_must_save_register (int regno)
    return 0;
  }
  
@@ -176,7 +176,7 @@ index 53b44df..0dec362 100644
  /* Return the bytes needed to compute the frame pointer from the current
     stack pointer.
  
-@@ -3298,7 +3430,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+@@ -3411,7 +3543,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
    emit_insn (gen_indirect_jump (temp2));
  
    /* Run just enough of rest_of_compilation.  This sequence was
@@ -186,7 +186,7 @@ index 53b44df..0dec362 100644
    shorten_branches (insn);
    final_start_function (insn, file, 1);
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 88e0351..9f74ec8 100644
+index 0a435b8..346e47b 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info;
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
index b04ee5802..c79f9552e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
@@ -1,7 +1,7 @@
-From f846bd900d5277dd9defb5fe0625f97e3417ee61 Mon Sep 17 00:00:00 2001
+From 1c226901aec38e2e824177418dcd82b6cd49ffca Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:04:37 +0530
-Subject: [PATCH 21/54] [Patch, microblaze]: Add cbranchsi4_reg This patch
+Subject: [PATCH 21/63] [Patch, microblaze]: Add cbranchsi4_reg This patch
  optimizes the generation of  pcmpne/pcmpeq instruction if the compare
  instruction has no immediate values.For the immediate values the xor
  instruction is generated
@@ -31,10 +31,10 @@ Conflicts:
  8 files changed, 19 insertions(+), 19 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index f8a56f7..c39e2e9 100644
+index 6647cbc..bdc9b69 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -32,7 +32,7 @@ extern int microblaze_expand_shift (rtx *);
+@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
  extern bool microblaze_expand_move (machine_mode, rtx *);
  extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
  extern void microblaze_expand_divide (rtx *);
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
index beeb80fda..c3822d06b 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
@@ -1,7 +1,7 @@
-From 7d70a287544dd915b66a5658a3857ebecb8b3583 Mon Sep 17 00:00:00 2001
+From 791d65feae4f3cab47833579bc6f523e54194cbd Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:11:04 +0530
-Subject: [PATCH 22/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
+Subject: [PATCH 22/63] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
  The changes are made in the patch for the inline expansion of the fsqrt
  builtin with fqrt instruction. The sqrt math function takes double as
  argument and return double as argument. The pattern is selected while
@@ -29,10 +29,10 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
  1 file changed, 14 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7bbdbe1..3a53e24 100644
+index 3c80760..1fb5582 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -449,6 +449,20 @@
+@@ -451,6 +451,20 @@
    (set_attr "mode"      "SF")
    (set_attr "length"    "4")])
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
index 8f5bed52a..a314170f5 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
@@ -1,7 +1,7 @@
-From a28768eec0a9d5137196bed8e8c6d284cf4c3cbc Mon Sep 17 00:00:00 2001
+From 2c4a1d46e4f1b2342f899d6741d09dbf7cc87aa2 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:33:31 +0530
-Subject: [PATCH 23/54] [Patch] OPT: Update heuristics for loop-invariant for
+Subject: [PATCH 23/63] [Patch] OPT: Update heuristics for loop-invariant for
  address arithme. .tic.
 
 The changes are made in the patch to update the heuristics
@@ -26,10 +26,10 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
  1 file changed, 2 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index bd31a51..8e22ca0 100644
+index b880ead..fd7a019 100644
 --- a/gcc/loop-invariant.c
 +++ b/gcc/loop-invariant.c
-@@ -1466,10 +1466,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
+@@ -1465,10 +1465,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
  
    if (! flag_ira_loop_pressure)
      {
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
index 85a749e58..a786ba091 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
@@ -1,7 +1,7 @@
-From be9c512be09fa4ef67870ab0456eb3781394dac3 Mon Sep 17 00:00:00 2001
+From c2b64f2f7a06231d8da0a53c6761939583ac56da Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 18:07:24 +0530
-Subject: [PATCH 24/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
+Subject: [PATCH 24/63] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
  insn definitions Change adddi3 to handle DI immediates as the second operand,
  this requires modification to the output template however reduces the need to
  specify seperate templates for 16-bit positive/negative immediate operands.
@@ -23,10 +23,10 @@ Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
  1 file changed, 6 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 3a53e24..949e103 100644
+index 1fb5582..216219b 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -500,17 +500,16 @@
+@@ -502,17 +502,16 @@
  ;; Adding 2 DI operands in register or reg/imm
  
  (define_insn "adddi3"
@@ -49,7 +49,7 @@ index 3a53e24..949e103 100644
  
  ;;----------------------------------------------------------------
  ;; Subtraction
-@@ -547,7 +546,7 @@
+@@ -549,7 +548,7 @@
  (define_insn "subdi3"
    [(set (match_operand:DI 0 "register_operand" "=&d")
  	(minus:DI (match_operand:DI 1 "register_operand" "d")
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
index 17f254488..98310b368 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
@@ -1,7 +1,7 @@
-From c8ee051fa3e0ad05b19eb6141a7cb72245b412b7 Mon Sep 17 00:00:00 2001
+From c7e5c253b1e7800bc5ec8cc69850118ed938e22f Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 18:18:41 +0530
-Subject: [PATCH 25/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns
+Subject: [PATCH 25/63] [Patch, microblaze]: Update ashlsi3 & movsf patterns
  This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
  of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
  patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
@@ -27,10 +27,10 @@ ChangeLog:
  2 files changed, 9 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0dec362..daf0269 100644
+index 0ce9d13..7669668 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2531,7 +2531,7 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2608,7 +2608,7 @@ print_operand (FILE * file, rtx op, int letter)
  	  unsigned long value_long;
  	  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
  				       value_long);
@@ -40,10 +40,10 @@ index 0dec362..daf0269 100644
        else
  	{
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 949e103..bc675ca 100644
+index 216219b..4bc209c 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -1366,7 +1366,10 @@
+@@ -1368,7 +1368,10 @@
                     (match_operand:SI 2 "immediate_operand" "I")))] 
    "!TARGET_SOFT_MUL 
     && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
@@ -55,7 +55,7 @@ index 949e103..bc675ca 100644
    ;; This MUL will not generate an imm. Can go into a delay slot.
    [(set_attr "type"	"arith")
     (set_attr "mode"	"SI")
-@@ -1378,7 +1381,10 @@
+@@ -1380,7 +1383,10 @@
  	(ashift:SI (match_operand:SI 1 "register_operand"  "d")
                     (match_operand:SI 2 "immediate_operand" "I")))] 
    "!TARGET_SOFT_MUL"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
index 506714bd3..ba80ce457 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
@@ -1,7 +1,7 @@
-From 64e76f3be6ad78044ea2b89b555a07758c2b2950 Mon Sep 17 00:00:00 2001
+From c3b633b0ee8d228a7d70a02b574822aba9a0fd93 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 19:50:34 +0530
-Subject: [PATCH 26/54] [Patch, microblaze]: 8-stage pipeline for microblaze
+Subject: [PATCH 26/63] [Patch, microblaze]: 8-stage pipeline for microblaze
  This patch adds the support for the 8-stage pipeline. The new 8-stage
  pipeline reduces the latencies of float & integer division drastically
 
@@ -28,11 +28,11 @@ ChangeLog:
  4 files changed, 96 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index daf0269..3832d16 100644
+index 7669668..ae7d5dd 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -1772,6 +1772,19 @@ microblaze_option_override (void)
-           warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a");
+@@ -1848,6 +1848,19 @@ microblaze_option_override (void)
+ 		   "%<-mcpu=v8.30.a%>");
          TARGET_REORDER = 0;
      }
 +  ver = ver_int - microblaze_version_to_int("v10.0");
@@ -50,9 +50,9 @@ index daf0269..3832d16 100644
 +    }
  
    if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
-     error ("-mxl-multiply-high requires -mno-xl-soft-mul");
+     error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 9f74ec8..2ac5aeec 100644
+index 346e47b..bf7f3b4 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -27,7 +27,8 @@
@@ -66,7 +66,7 @@ index 9f74ec8..2ac5aeec 100644
  
  #define MICROBLAZE_MASK_NO_UNSAFE_DELAY         0x00000001
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index bc675ca..6395533 100644
+index 4bc209c..b7c16ac 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -35,6 +35,7 @@
@@ -77,7 +77,7 @@ index bc675ca..6395533 100644
    (UNSPEC_SET_GOT       101)    ;;
    (UNSPEC_GOTOFF        102)    ;; GOT offset
    (UNSPEC_PLT           103)    ;; jump table
-@@ -80,7 +81,7 @@
+@@ -82,7 +83,7 @@
  ;; bshift 	Shift operations
  
  (define_attr "type"
@@ -86,7 +86,7 @@ index bc675ca..6395533 100644
    (const_string "unknown"))
  
  ;; Main data type used by the insn
-@@ -222,6 +223,80 @@
+@@ -224,6 +225,80 @@
  ;;-----------------------------------------------------------------
  
  
@@ -167,7 +167,7 @@ index bc675ca..6395533 100644
  ;;----------------------------------------------------------------
  ;; Microblaze 5-stage pipeline description (v5.00.a and later)
  ;;----------------------------------------------------------------                 
-@@ -468,7 +543,7 @@
+@@ -470,7 +545,7 @@
          (fix:SI (match_operand:SF 1 "register_operand" "d")))]
    "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
    "fint\t%0,%1"
@@ -177,10 +177,10 @@ index bc675ca..6395533 100644
    (set_attr "length"    "4")])
  
 diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index 8242998..c8e6f00 100644
+index 2e46941..d23f376 100644
 --- a/gcc/config/microblaze/microblaze.opt
 +++ b/gcc/config/microblaze/microblaze.opt
-@@ -129,3 +129,7 @@ Use hardware prefetch instruction
+@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
  
  mxl-mode-xilkernel
  Target
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
index 95b9b2aa3..330b54948 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
@@ -1,7 +1,7 @@
-From 5147c831c6a78d9b95138b679bb2ca7624abc3a1 Mon Sep 17 00:00:00 2001
+From 650cbdea7bc810e2bd0ebc5eb5647ed513498670 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 11:08:40 +0530
-Subject: [PATCH 27/54] [Patch,rtl Optimization]: Better register pressure
+Subject: [PATCH 27/63] [Patch,rtl Optimization]: Better register pressure
  estimate for loop . .invariant code motion
 
 Calculate the loop liveness used for regs for calculating the register pressure
@@ -41,7 +41,7 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com.
  2 files changed, 50 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
-index 3af0b2d..123dc6b 100644
+index 6dbe96f..ec5cba2 100644
 --- a/gcc/cfgloopanal.c
 +++ b/gcc/cfgloopanal.c
 @@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
@@ -56,10 +56,10 @@ index 3af0b2d..123dc6b 100644
         them.  */
      cost = target_reg_cost [speed] * n_new;
 diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index 8e22ca0..c9ec8df 100644
+index fd7a019..ad54297 100644
 --- a/gcc/loop-invariant.c
 +++ b/gcc/loop-invariant.c
-@@ -1520,7 +1520,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
+@@ -1519,7 +1519,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
  	size_cost = 0;
      }
  
@@ -68,7 +68,7 @@ index 8e22ca0..c9ec8df 100644
  }
  
  /* Finds invariant with best gain for moving.  Returns the gain, stores
-@@ -1614,22 +1614,53 @@ find_invariants_to_move (bool speed, bool call_p)
+@@ -1613,22 +1613,53 @@ find_invariants_to_move (bool speed, bool call_p)
      /* REGS_USED is actually never used when the flag is on.  */
      regs_used = 0;
    else
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
index 3643ff19d..b5ee2c8cf 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
@@ -1,7 +1,7 @@
-From 2715b235b3db423bf35b9304a2ba5daa86b1680e Mon Sep 17 00:00:00 2001
+From 8f8c6cd35a2cf79449c0155fa865a665d730e541 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 11:25:48 +0530
-Subject: [PATCH 28/54] [Patch, microblaze]: Correct the const high double
+Subject: [PATCH 28/63] [Patch, microblaze]: Correct the const high double
  immediate value With this patch the loading of the DI mode immediate values
  will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
  functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
@@ -24,10 +24,10 @@ ChangeLog:
  create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 3832d16..29cd54f 100644
+index ae7d5dd..002d7a5 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2517,14 +2517,18 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2594,14 +2594,18 @@ print_operand (FILE * file, rtx op, int letter)
    else if (letter == 'h' || letter == 'j')
      {
        long val[2];
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
index b4b9d2ecb..cbfc98de6 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
@@ -1,7 +1,7 @@
-From 7e025a0b22eee87bf9597267918bd16fc87c85c2 Mon Sep 17 00:00:00 2001
+From 30402c3bcfeb8a93656957b22558997b65d69cb8 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 11:49:58 +0530
-Subject: [PATCH 29/54] [Fix, microblaze]: Fix internal compiler error with
+Subject: [PATCH 29/63] [Fix, microblaze]: Fix internal compiler error with
  msmall-divides This patch will fix the internal error
  microblaze_expand_divide function which comes because of rtx PLUS where the
  mem_rtx is of type SI and the operand is of type QImode. This patch modifies
@@ -19,10 +19,10 @@ ChangeLog:
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 29cd54f..f8a417c 100644
+index 002d7a5..c662952 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3769,7 +3769,7 @@ microblaze_expand_divide (rtx operands[])
+@@ -3909,7 +3909,7 @@ microblaze_expand_divide (rtx operands[])
    emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
    emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
    mem_rtx = gen_rtx_MEM (QImode,
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
index 52fd4beab..fce063596 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
@@ -1,7 +1,7 @@
-From 27a69d1873221747121360d0a1dffc4336a1d0cc Mon Sep 17 00:00:00 2001
+From 5ac80cf926c4dc96cbfd189f02c9250865b52dd3 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 12:03:39 +0530
-Subject: [PATCH 30/54] [patch,microblaze]: Fix the calculation of high word in
+Subject: [PATCH 30/63] [patch,microblaze]: Fix the calculation of high word in
  a long long 6. .4-bit
 
 This patch will change the calculation of high word in a long long 64-bit.
@@ -27,10 +27,10 @@ ChangeLog:
  1 file changed, 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index f8a417c..70d8d03 100644
+index c662952..8013a2c 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2535,9 +2535,6 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2612,9 +2612,6 @@ print_operand (FILE * file, rtx op, int letter)
          {
  	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
  	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
index 571445237..cbf64d978 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
@@ -1,7 +1,7 @@
-From 35569bb20a5bb881f7f275d901a0be3408b16622 Mon Sep 17 00:00:00 2001
+From 45deb5bd3ae8c3db360ef181c9873e37d2288848 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 12:14:51 +0530
-Subject: [PATCH 31/54] [Patch, microblaze]: Add new bit-field instructions
+Subject: [PATCH 31/63] [Patch, microblaze]: Add new bit-field instructions
  This patches adds new bsefi and bsifi instructions. BSEFI- The instruction
  shall extract a bit field from a register and place it right-adjusted in the
  destination register. The other bits in the destination register shall be set
@@ -20,10 +20,10 @@ ChangeLog:
  1 file changed, 73 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6395533..5a2dd13 100644
+index b7c16ac..67b298a 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -980,6 +980,8 @@
+@@ -982,6 +982,8 @@
    (set_attr "mode"	"DI")
    (set_attr "length"	"20,20,20")])
  
@@ -32,7 +32,7 @@ index 6395533..5a2dd13 100644
  ;;----------------------------------------------------------------
  ;; Data movement
  ;;----------------------------------------------------------------
-@@ -1774,6 +1776,7 @@
+@@ -1776,6 +1778,7 @@
    (set_attr "length"   "28")]
  )
  
@@ -40,7 +40,7 @@ index 6395533..5a2dd13 100644
  ;;----------------------------------------------------------------
  ;; Setting a register from an integer comparison. 
  ;;----------------------------------------------------------------
-@@ -2473,4 +2476,74 @@
+@@ -2489,4 +2492,74 @@
    DONE;
  }")
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
index dce1bc58b..86df58b3f 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
@@ -1,7 +1,7 @@
-From 3db8f0c3124d3001d3c10e6d400943f3ec57616b Mon Sep 17 00:00:00 2001
+From bc95cc12b2c4d96ea709eefc4b99181b8c40b19c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 12:42:10 +0530
-Subject: [PATCH 32/54] [Patch, microblaze]: Fix bug in MB version calculation
+Subject: [PATCH 32/63] [Patch, microblaze]: Fix bug in MB version calculation
  This patch fixes the bug in microblaze_version_to_int function. Earlier the
  conversion of vXX.YY.Z to int has a bug which is fixed now.
 
@@ -12,10 +12,10 @@ Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
  1 file changed, 70 insertions(+), 77 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 70d8d03..30a0fcf 100644
+index 8013a2c..3f68ef0 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -238,6 +238,63 @@ section *sdata2_section;
+@@ -239,6 +239,63 @@ section *sdata2_section;
  #define TARGET_HAVE_TLS true
  #endif
  
@@ -79,7 +79,7 @@ index 70d8d03..30a0fcf 100644
  /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
  static bool
  microblaze_const_double_ok (rtx op, machine_mode mode)
-@@ -1266,8 +1323,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+@@ -1338,8 +1395,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
        {
  	if (TARGET_BARREL_SHIFT)
  	  {
@@ -89,7 +89,7 @@ index 70d8d03..30a0fcf 100644
  	      *total = COSTS_N_INSNS (1);
  	    else
  	      *total = COSTS_N_INSNS (2);
-@@ -1328,8 +1384,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+@@ -1400,8 +1456,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
  	  }
  	else if (!TARGET_SOFT_MUL)
  	  {
@@ -99,7 +99,7 @@ index 70d8d03..30a0fcf 100644
  	      *total = COSTS_N_INSNS (1);
  	    else
  	      *total = COSTS_N_INSNS (3);
-@@ -1609,72 +1664,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
+@@ -1682,72 +1737,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
    return 0;
  }
  
@@ -173,7 +173,7 @@ index 70d8d03..30a0fcf 100644
  
    microblaze_section_threshold = (global_options_set.x_g_switch_value
  				  ? g_switch_value
-@@ -1695,13 +1691,13 @@ microblaze_option_override (void)
+@@ -1768,13 +1764,13 @@ microblaze_option_override (void)
    /* Check the MicroBlaze CPU version for any special action to be done.  */
    if (microblaze_select_cpu == NULL)
      microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
@@ -182,7 +182,7 @@ index 70d8d03..30a0fcf 100644
 +  ver_int = microblaze_version_to_int (microblaze_select_cpu);
 +  if (ver_int == -1)
      {
-       error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu);
+       error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu);
      }
  
 -  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
@@ -190,7 +190,7 @@ index 70d8d03..30a0fcf 100644
    if (ver < 0)
      {
        /* No hardware exceptions in earlier versions. So no worries.  */
-@@ -1712,8 +1708,7 @@ microblaze_option_override (void)
+@@ -1785,8 +1781,7 @@ microblaze_option_override (void)
        microblaze_pipe = MICROBLAZE_PIPE_3;
      }
    else if (ver == 0
@@ -200,7 +200,7 @@ index 70d8d03..30a0fcf 100644
      {
  #if 0
        microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
-@@ -1730,11 +1725,9 @@ microblaze_option_override (void)
+@@ -1803,11 +1798,9 @@ microblaze_option_override (void)
  #endif
        microblaze_no_unsafe_delay = 0;
        microblaze_pipe = MICROBLAZE_PIPE_5;
@@ -215,7 +215,7 @@ index 70d8d03..30a0fcf 100644
  	{
  	  /* Pattern compares are to be turned on by default only when 
   	     compiling for MB v5.00.'z'.  */
-@@ -1742,7 +1735,7 @@ microblaze_option_override (void)
+@@ -1815,7 +1808,7 @@ microblaze_option_override (void)
  	}
      }
  
@@ -224,8 +224,8 @@ index 70d8d03..30a0fcf 100644
    if (ver < 0)
      {
        if (TARGET_MULTIPLY_HIGH)
-@@ -1750,7 +1743,7 @@ microblaze_option_override (void)
- 		 "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater");
+@@ -1824,7 +1817,7 @@ microblaze_option_override (void)
+ 		 "%<-mcpu=v6.00.a%> or greater");
      }
  
 -  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
@@ -233,7 +233,7 @@ index 70d8d03..30a0fcf 100644
    microblaze_has_clz = 1;
    if (ver < 0)
      {
-@@ -1759,7 +1752,7 @@ microblaze_option_override (void)
+@@ -1833,7 +1826,7 @@ microblaze_option_override (void)
      }
  
    /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified.  */
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
index 15111477a..68f70ae8d 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
@@ -1,7 +1,7 @@
-From f3e259923788176ebb323155cc089e68c6de0895 Mon Sep 17 00:00:00 2001
+From 51da0572e0650378e422030b26d1258c8fc76df6 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 13:57:48 +0530
-Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field
+Subject: [PATCH 33/63] Fixing the bug in the bit-field instruction. Bit field
  instruction should be generated only if mcpu >10.0
 
 ---
@@ -10,10 +10,10 @@ Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field
  2 files changed, 5 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 30a0fcf..835e906 100644
+index 3f68ef0..a37f08eea 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -163,6 +163,9 @@ int microblaze_no_unsafe_delay;
+@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
  /* Set to one if the targeted core has the CLZ insn.  */
  int microblaze_has_clz = 0;
  
@@ -24,7 +24,7 @@ index 30a0fcf..835e906 100644
     version having only a particular type of pipeline. There can still be 
     options on the CPU to scale pipeline features up or down. :( 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 2ac5aeec..991d0f7 100644
+index bf7f3b4..1d05e6e 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
index f22f2f3fb..04326205d 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
@@ -1,7 +1,7 @@
-From 52cf8e91f06ce9259d4d94bb8ea5cb327825b806 Mon Sep 17 00:00:00 2001
+From 132b913b721f66c5db17f62dd5559bbca11bb875 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 20:57:10 +0530
-Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal
+Subject: [PATCH 34/63] [Patch, microblaze]: Macros used in Xilinx internal
  patches has been removed in gcc 6.2 version so modified the code accordingly.
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal
  1 file changed, 3 insertions(+), 5 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 835e906..2e3b4c9 100644
+index a37f08eea..71640e5 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2520,11 +2520,9 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2597,11 +2597,9 @@ print_operand (FILE * file, rtx op, int letter)
  	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
  	  else
  	    {
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0035-Fixing-the-issue-with-the-builtin_alloc.patch
index 00d67bcf6..91ac0d027 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0035-Fixing-the-issue-with-the-builtin_alloc.patch
@@ -1,7 +1,7 @@
-From 727b0f7ae03279177559f5d85d8920352bd853b2 Mon Sep 17 00:00:00 2001
+From e672184af6a43b773131181270c7a8c5c5273bd8 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Thu, 23 Feb 2017 17:09:04 +0530
-Subject: [PATCH 35/54] Fixing the issue with the builtin_alloc. register r18
+Subject: [PATCH 35/63] Fixing the issue with the builtin_alloc. register r18
  was not properly handling the stack pattern which was resolved by using free
  available register
 
@@ -11,10 +11,10 @@ signed-off-by:nagaraju mekala <nmekala@xilinx.com>
  1 file changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 5a2dd13..8072ffc 100644
+index 67b298a..7bae957 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2076,10 +2076,10 @@
+@@ -2078,10 +2078,10 @@
    ""
    { 
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
@@ -27,7 +27,7 @@ index 5a2dd13..8072ffc 100644
      if (GET_CODE (operands[1]) != CONST_INT)
      {
          neg_op0 = gen_reg_rtx (Pmode);
-@@ -2088,9 +2088,9 @@
+@@ -2090,9 +2090,9 @@
          neg_op0 = GEN_INT (- INTVAL (operands[1]));
  
      emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
index 54ccd9a0c..7079789fb 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
@@ -1,7 +1,7 @@
-From 7156e379a67fa47a5fb9ede1448c0d528dbda65b Mon Sep 17 00:00:00 2001
+From ac30efb4a5f5b6d289fdd27b268c2095d60dcb42 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 2 Mar 2017 19:02:31 +0530
-Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before
+Subject: [PATCH 36/63] [Patch,Microblaze]:reverting the cost check before
  propagating constants.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before
  1 file changed, 4 insertions(+)
 
 diff --git a/gcc/cprop.c b/gcc/cprop.c
-index e4df509..deb706b 100644
+index 65c0130..42bcc81 100644
 --- a/gcc/cprop.c
 +++ b/gcc/cprop.c
 @@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
index 26b685a58..ba0f8e808 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
@@ -1,7 +1,7 @@
-From 149cf4619622d27641a2886cd8bf38a49ad88f87 Mon Sep 17 00:00:00 2001
+From f436198b817f33d56aaddb88ff629378498de489 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 19 Feb 2018 18:06:16 +0530
-Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield
+Subject: [PATCH 37/63] [Patch,Microblaze]: update in constraints for bitfield
  insert and extract instructions.
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield
  1 file changed, 7 insertions(+), 36 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 8072ffc..9bb87ec 100644
+index 7bae957..6101387 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2476,33 +2476,17 @@
+@@ -2492,33 +2492,17 @@
    DONE;
  }")
  
@@ -51,7 +51,7 @@ index 8072ffc..9bb87ec 100644
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
  			 (match_operand:SI 2 "immediate_operand" "I")
-@@ -2519,21 +2503,8 @@
+@@ -2535,21 +2519,8 @@
  			 (match_operand:SI 2 "immediate_operand" "I"))
  	(match_operand:SI 3 "register_operand" "r"))]
   "TARGET_HAS_BITFIELD"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
index d8ae6c155..2b90880fb 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
@@ -1,7 +1,7 @@
-From 5494699756f8e1dba6848fcf09780a031139c232 Mon Sep 17 00:00:00 2001
+From 89aa1907ab0abad38e394f46f7e5f577bdb26498 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 4 Jun 2018 10:10:18 +0530
-Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for
+Subject: [PATCH 38/63] [Patch,Microblaze] : Removed fsqrt generation for
  double values.
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for
  1 file changed, 14 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 9bb87ec..a93ddd0 100644
+index 6101387..eb01221 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -524,20 +524,6 @@
+@@ -526,20 +526,6 @@
    (set_attr "mode"      "SF")
    (set_attr "length"    "4")])
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0039-Intial-commit-of-64-bit-Microblaze.patch
index 88497a8ef..f524cba27 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0039-Intial-commit-of-64-bit-Microblaze.patch
@@ -1,22 +1,24 @@
-From 6e8b37bf54646c38fb4071d542a60ea92715df9b Mon Sep 17 00:00:00 2001
+From 68359cc8e82f63d01a77c39c68e782e6757cd71e Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 3 Apr 2018 16:48:39 +0530
-Subject: [PATCH 39/54] Intial commit of 64-bit Microblaze
+Subject: [PATCH 39/63] Intial commit of 64-bit Microblaze
 
+Conflicts:
+	gcc/config/microblaze/microblaze.opt
 ---
  gcc/config/microblaze/microblaze-protos.h |   1 +
  gcc/config/microblaze/microblaze.c        | 109 +++++++--
  gcc/config/microblaze/microblaze.h        |   4 +-
  gcc/config/microblaze/microblaze.md       | 370 +++++++++++++++++++++++++++++-
- gcc/config/microblaze/microblaze.opt      |   9 +-
+ gcc/config/microblaze/microblaze.opt      |   7 +-
  gcc/config/microblaze/t-microblaze        |   7 +-
- 6 files changed, 461 insertions(+), 39 deletions(-)
+ 6 files changed, 460 insertions(+), 38 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index c39e2e9..a5ed62e 100644
+index bdc9b69..7d6c189 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -35,6 +35,7 @@ extern void microblaze_expand_divide (rtx *);
+@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
  extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
  extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
  extern void microblaze_expand_conditional_branch_sf (rtx *); 
@@ -25,10 +27,10 @@ index c39e2e9..a5ed62e 100644
  extern void print_operand (FILE *, rtx, int);
  extern void print_operand_address (FILE *, rtx);
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 2e3b4c9..2079ae9 100644
+index 71640e5..f740f5c 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3457,11 +3457,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+@@ -3570,11 +3570,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
    op0 = operands[0];
    op1 = operands[1];
  
@@ -43,7 +45,7 @@ index 2e3b4c9..2079ae9 100644
        emit_move_insn (op0, temp);
        return true;
      }
-@@ -3499,12 +3499,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+@@ -3639,12 +3639,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
  	          && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
  		      || !SMALL_INT (p1)))))
  	{
@@ -58,7 +60,7 @@ index 2e3b4c9..2079ae9 100644
  	  return true;
  	}
      }
-@@ -3635,7 +3635,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3775,7 +3775,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
    rtx cmp_op0 = operands[1];
    rtx cmp_op1 = operands[2];
    rtx label1 = operands[3];
@@ -67,7 +69,7 @@ index 2e3b4c9..2079ae9 100644
    rtx condition;
  
    gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
-@@ -3644,23 +3644,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3784,23 +3784,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
    if (cmp_op1 == const0_rtx)
      {
        comp_reg = cmp_op0;
@@ -110,7 +112,7 @@ index 2e3b4c9..2079ae9 100644
      }
  }
  
-@@ -3671,7 +3684,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3811,7 +3824,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
    rtx cmp_op0 = operands[1];
    rtx cmp_op1 = operands[2];
    rtx label1 = operands[3];
@@ -119,7 +121,7 @@ index 2e3b4c9..2079ae9 100644
    rtx condition;
  
    gcc_assert ((GET_CODE (cmp_op0) == REG)
-@@ -3682,30 +3695,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3822,30 +3835,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
      {
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code),
@@ -195,7 +197,7 @@ index 2e3b4c9..2079ae9 100644
      }
  }
  
-@@ -3722,6 +3768,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+@@ -3862,6 +3908,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
    emit_jump_insn (gen_condjump (condition, operands[3]));
  }
  
@@ -216,7 +218,7 @@ index 2e3b4c9..2079ae9 100644
  
  static bool
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 991d0f7..72fbee5 100644
+index 1d05e6e..2ca44f5 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
@@ -245,10 +247,10 @@ index 991d0f7..72fbee5 100644
  #define FLOAT_TYPE_SIZE         32
  #define DOUBLE_TYPE_SIZE        64
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a93ddd0..6976b37 100644
+index eb01221..dbb592e 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -495,7 +495,6 @@
+@@ -497,7 +497,6 @@
    (set_attr "mode"      "SF")
    (set_attr "length"    "4")])
  
@@ -256,7 +258,7 @@ index a93ddd0..6976b37 100644
  (define_insn "divsf3"
    [(set (match_operand:SF 0 "register_operand" "=d")
          (div:SF (match_operand:SF 1 "register_operand" "d")
-@@ -506,6 +505,7 @@
+@@ -508,6 +507,7 @@
    (set_attr "mode"      "SF")
    (set_attr "length"    "4")])
  
@@ -264,7 +266,7 @@ index a93ddd0..6976b37 100644
  (define_insn "sqrtsf2"
    [(set (match_operand:SF 0 "register_operand" "=d")
          (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
-@@ -560,6 +560,18 @@
+@@ -562,6 +562,18 @@
  
  ;; Adding 2 DI operands in register or reg/imm
  
@@ -283,7 +285,7 @@ index a93ddd0..6976b37 100644
  (define_insn "adddi3"
    [(set (match_operand:DI 0 "register_operand" "=d,d")
  	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
-@@ -604,6 +616,18 @@
+@@ -606,6 +618,18 @@
  ;; Double Precision Subtraction
  ;;----------------------------------------------------------------
  
@@ -302,7 +304,7 @@ index a93ddd0..6976b37 100644
  (define_insn "subdi3"
    [(set (match_operand:DI 0 "register_operand" "=&d")
  	(minus:DI (match_operand:DI 1 "register_operand" "d")
-@@ -793,6 +817,15 @@
+@@ -795,6 +819,15 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -318,7 +320,7 @@ index a93ddd0..6976b37 100644
  (define_insn "negdi2"
    [(set (match_operand:DI 0 "register_operand" "=d")
  	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -812,6 +845,15 @@
+@@ -814,6 +847,15 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -334,7 +336,7 @@ index a93ddd0..6976b37 100644
  (define_insn "*one_cmpldi2"
    [(set (match_operand:DI 0 "register_operand" "=d")
  	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -838,6 +880,20 @@
+@@ -840,6 +882,20 @@
  ;; Logical
  ;;----------------------------------------------------------------
  
@@ -355,7 +357,7 @@ index a93ddd0..6976b37 100644
  (define_insn "andsi3"
    [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
  	(and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
-@@ -853,6 +909,18 @@
+@@ -855,6 +911,18 @@
    (set_attr "length"	"4,8,8,8")])
  
  
@@ -374,7 +376,7 @@ index a93ddd0..6976b37 100644
  (define_insn "iorsi3"
    [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
  	(ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
-@@ -867,6 +935,19 @@
+@@ -869,6 +937,19 @@
    (set_attr "mode"	"SI,SI,SI,SI")
    (set_attr "length"	"4,8,8,8")])
  
@@ -394,7 +396,7 @@ index a93ddd0..6976b37 100644
  (define_insn "xorsi3"
    [(set (match_operand:SI 0 "register_operand" "=d,d,d")
  	(xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
-@@ -935,6 +1016,26 @@
+@@ -937,6 +1018,26 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -421,7 +423,7 @@ index a93ddd0..6976b37 100644
  (define_insn "extendhisi2"
    [(set (match_operand:SI 0 "register_operand" "=d")
  	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
-@@ -944,6 +1045,16 @@
+@@ -946,6 +1047,16 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -438,7 +440,7 @@ index a93ddd0..6976b37 100644
  ;; Those for integer source operand are ordered
  ;; widest source type first.
  
-@@ -1009,7 +1120,6 @@
+@@ -1011,7 +1122,6 @@
  )
  
  
@@ -446,7 +448,7 @@ index a93ddd0..6976b37 100644
  (define_insn "*movdi_internal"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
  	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
-@@ -1421,6 +1531,36 @@
+@@ -1423,6 +1533,36 @@
    (set_attr "length"	"4,4")]
  )
  
@@ -483,7 +485,7 @@ index a93ddd0..6976b37 100644
  ;; The following patterns apply when there is no barrel shifter present
  
  (define_insn "*ashlsi3_with_mul_delay"
-@@ -1546,6 +1686,36 @@
+@@ -1548,6 +1688,36 @@
  ;;----------------------------------------------------------------
  ;; 32-bit right shifts
  ;;----------------------------------------------------------------
@@ -520,7 +522,7 @@ index a93ddd0..6976b37 100644
  (define_expand "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
  	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -1655,6 +1825,36 @@
+@@ -1657,6 +1827,36 @@
  ;;----------------------------------------------------------------
  ;; 32-bit right shifts (logical)
  ;;----------------------------------------------------------------
@@ -557,7 +559,7 @@ index a93ddd0..6976b37 100644
  
  (define_expand "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
-@@ -1801,6 +2001,8 @@
+@@ -1803,6 +2003,8 @@
    (set_attr "length"	"4")]
  )              
  
@@ -566,7 +568,7 @@ index a93ddd0..6976b37 100644
  ;;----------------------------------------------------------------
  ;; Setting a register from an floating point comparison. 
  ;;----------------------------------------------------------------
-@@ -1816,6 +2018,18 @@
+@@ -1818,6 +2020,18 @@
     (set_attr "length"    "4")]
  )
  
@@ -585,7 +587,7 @@ index a93ddd0..6976b37 100644
  ;;----------------------------------------------------------------
  ;; Conditional branches
  ;;----------------------------------------------------------------
-@@ -1928,6 +2142,115 @@
+@@ -1930,6 +2144,115 @@
     (set_attr "length"   "12")]
  )
  
@@ -701,7 +703,7 @@ index a93ddd0..6976b37 100644
  ;;----------------------------------------------------------------
  ;; Unconditional branches
  ;;----------------------------------------------------------------
-@@ -2462,17 +2785,33 @@
+@@ -2478,17 +2801,33 @@
    DONE;
  }")
  
@@ -740,7 +742,7 @@ index a93ddd0..6976b37 100644
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
  			 (match_operand:SI 2 "immediate_operand" "I")
-@@ -2489,8 +2828,21 @@
+@@ -2505,8 +2844,21 @@
  			 (match_operand:SI 2 "immediate_operand" "I"))
  	(match_operand:SI 3 "register_operand" "r"))]
   "TARGET_HAS_BITFIELD"
@@ -765,18 +767,10 @@ index a93ddd0..6976b37 100644
  (define_insn "insv_32"
    [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
 diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index c8e6f00..cdcae00 100644
+index d23f376..f316e27 100644
 --- a/gcc/config/microblaze/microblaze.opt
 +++ b/gcc/config/microblaze/microblaze.opt
-@@ -125,11 +125,16 @@ Description for mxl-mode-novectors.
- 
- mxl-prefetch
- Target Mask(PREFETCH)
--Use hardware prefetch instruction
-+Use hardware prefetch instruction.
- 
- mxl-mode-xilkernel
- Target
+@@ -136,4 +136,9 @@ Target
  
  mxl-frequency
  Target Mask(AREA_OPTIMIZED_2)
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
index 1157a82fc..a973f4cd4 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
@@ -1,7 +1,7 @@
-From 5526d87787d61990be3187b230fae4d0591d0651 Mon Sep 17 00:00:00 2001
+From 95615e1bfae642dc4f5f1b03e1ffaea4f16aa99c Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 4 Apr 2018 16:41:41 +0530
-Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing
+Subject: [PATCH 40/63] Added load store pattern movdi and also adding missing
  files
 
 ---
@@ -11,7 +11,7 @@ Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing
  3 files changed, 33 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index ae14944..a06b4d8 100644
+index 5e1d79a..69bcb24 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -52,6 +52,11 @@
@@ -27,10 +27,10 @@ index ae14944..a06b4d8 100644
  
  (define_constraint "G"
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6976b37..0cd0441 100644
+index dbb592e..eb52957 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -1120,6 +1120,32 @@
+@@ -1122,6 +1122,32 @@
  )
  
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0041-Intial-commit-for-64bit-MB-sources.patch
index 411958e74..b022eb77e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0041-Intial-commit-for-64bit-MB-sources.patch
@@ -1,7 +1,7 @@
-From eee9b7f7423823b133d6a5e5382863502433bdc6 Mon Sep 17 00:00:00 2001
+From 7c68b1c9771f09f7cc53410248e8432c562d24bf Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 27 Jul 2018 15:23:41 +0530
-Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the
+Subject: [PATCH 41/63] Intial commit for 64bit-MB sources. Need to cleanup the
  code later.
 
 ---
@@ -29,7 +29,7 @@ Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the
  create mode 100644 libgcc/config/microblaze/umoddi3.S
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index a06b4d8..867a7b5 100644
+index 69bcb24..2fce91e 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -55,7 +55,7 @@
@@ -42,7 +42,7 @@ index a06b4d8..867a7b5 100644
  ;; Define floating point constraints
  
 diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index 7b020b5..d8a1d13 100644
+index cd21319..d2b0c76 100644
 --- a/gcc/config/microblaze/microblaze-c.c
 +++ b/gcc/config/microblaze/microblaze-c.c
 @@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
@@ -57,10 +57,10 @@ index 7b020b5..d8a1d13 100644
 +    }
  }  
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 2079ae9..ba7ade4 100644
+index f740f5c..d5ff7af 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -382,10 +382,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
+@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
  	{
  	  return 1;
  	}
@@ -73,7 +73,7 @@ index 2079ae9..ba7ade4 100644
        else
  	return 0;
  
-@@ -433,7 +433,7 @@ double_memory_operand (rtx op, machine_mode mode)
+@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode)
      return 1;
  
    return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
@@ -82,7 +82,7 @@ index 2079ae9..ba7ade4 100644
  			   plus_constant (Pmode, addr, 4));
  }
  
-@@ -680,7 +680,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
+@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
           /* Load the addend.  */
           addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
  				  UNSPEC_TLS);
@@ -91,7 +91,7 @@ index 2079ae9..ba7ade4 100644
           dest = gen_rtx_PLUS (Pmode, dest, addend);
           break;
  
-@@ -698,7 +698,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
+@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
  
    if (XINT (x, 1) == UNSPEC_GOTOFF)
      {
@@ -100,7 +100,7 @@ index 2079ae9..ba7ade4 100644
        info->type = ADDRESS_GOTOFF;
      }
    else if (XINT (x, 1) == UNSPEC_PLT)
-@@ -1230,8 +1230,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
+@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
    emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
  
    /* Emit the test & branch.  */
@@ -118,7 +118,7 @@ index 2079ae9..ba7ade4 100644
  
    /* Mop up any left-over bytes.  */
    if (leftover)
-@@ -1561,14 +1569,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
+@@ -1634,14 +1642,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
        break;
  
      case E_DFmode:
@@ -141,7 +141,7 @@ index 2079ae9..ba7ade4 100644
        break;
  
      case E_QImode:
-@@ -2219,7 +2233,7 @@ compute_frame_size (HOST_WIDE_INT size)
+@@ -2295,7 +2309,7 @@ compute_frame_size (HOST_WIDE_INT size)
  
  	  if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
  	    /* Don't account for link register. It is accounted specially below.  */
@@ -150,7 +150,7 @@ index 2079ae9..ba7ade4 100644
  
  	  mask |= (1L << (regno - GP_REG_FIRST));
  	}
-@@ -2487,7 +2501,7 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2564,7 +2578,7 @@ print_operand (FILE * file, rtx op, int letter)
  
        if ((letter == 'M' && !WORDS_BIG_ENDIAN)
  	  || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
@@ -159,7 +159,7 @@ index 2079ae9..ba7ade4 100644
  
        fprintf (file, "%s", reg_names[regnum]);
      }
-@@ -2513,6 +2527,7 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2590,6 +2604,7 @@ print_operand (FILE * file, rtx op, int letter)
    else if (letter == 'h' || letter == 'j')
      {
        long val[2];
@@ -167,7 +167,7 @@ index 2079ae9..ba7ade4 100644
        long l[2];
        if (code == CONST_DOUBLE)
  	{
-@@ -2525,12 +2540,12 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2602,12 +2617,12 @@ print_operand (FILE * file, rtx op, int letter)
                val[0] = l[WORDS_BIG_ENDIAN != 0];
  	    }
  	}
@@ -184,7 +184,7 @@ index 2079ae9..ba7ade4 100644
      }
    else if (code == CONST_DOUBLE)
      {
-@@ -2713,7 +2728,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
+@@ -2801,7 +2816,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
  
      switch_to_section (get_section (section, 0, NULL));
      assemble_align (POINTER_SIZE);
@@ -196,7 +196,7 @@ index 2079ae9..ba7ade4 100644
      output_addr_const (asm_out_file, symbol);
      fputs ("\n", asm_out_file);
  }
-@@ -2736,7 +2754,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
+@@ -2824,7 +2842,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
  
      switch_to_section (get_section (section, 0, NULL));
      assemble_align (POINTER_SIZE);
@@ -208,7 +208,7 @@ index 2079ae9..ba7ade4 100644
      output_addr_const (asm_out_file, symbol);
      fputs ("\n", asm_out_file);
  }
-@@ -2802,7 +2823,7 @@ save_restore_insns (int prologue)
+@@ -2890,7 +2911,7 @@ save_restore_insns (int prologue)
    /* For interrupt_handlers, need to save/restore the MSR.  */
    if (microblaze_is_interrupt_variant ())
      {
@@ -217,7 +217,7 @@ index 2079ae9..ba7ade4 100644
  				 gen_rtx_PLUS (Pmode, base_reg_rtx,
  					       GEN_INT (current_frame_info.
  							gp_offset -
-@@ -2810,8 +2831,8 @@ save_restore_insns (int prologue)
+@@ -2898,8 +2919,8 @@ save_restore_insns (int prologue)
  
        /* Do not optimize in flow analysis.  */
        MEM_VOLATILE_P (isr_mem_rtx) = 1;
@@ -228,7 +228,7 @@ index 2079ae9..ba7ade4 100644
      }
  
    if (microblaze_is_interrupt_variant () && !prologue)
-@@ -2819,8 +2840,8 @@ save_restore_insns (int prologue)
+@@ -2907,8 +2928,8 @@ save_restore_insns (int prologue)
        emit_move_insn (isr_reg_rtx, isr_mem_rtx);
        emit_move_insn (isr_msr_rtx, isr_reg_rtx);
        /* Do not optimize in flow analysis.  */
@@ -239,7 +239,7 @@ index 2079ae9..ba7ade4 100644
      }
  
    for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-@@ -2831,9 +2852,9 @@ save_restore_insns (int prologue)
+@@ -2919,9 +2940,9 @@ save_restore_insns (int prologue)
  	    /* Don't handle here. Already handled as the first register.  */
  	    continue;
  
@@ -251,7 +251,7 @@ index 2079ae9..ba7ade4 100644
  	  if (microblaze_is_interrupt_variant () || save_volatiles)
  	    /* Do not optimize in flow analysis.  */
  	    MEM_VOLATILE_P (mem_rtx) = 1;
-@@ -2848,7 +2869,7 @@ save_restore_insns (int prologue)
+@@ -2936,7 +2957,7 @@ save_restore_insns (int prologue)
  	      insn = emit_move_insn (reg_rtx, mem_rtx);
  	    }
  
@@ -260,7 +260,7 @@ index 2079ae9..ba7ade4 100644
  	}
      }
  
-@@ -2858,8 +2879,8 @@ save_restore_insns (int prologue)
+@@ -2946,8 +2967,8 @@ save_restore_insns (int prologue)
        emit_move_insn (isr_mem_rtx, isr_reg_rtx);
  
        /* Do not optimize in flow analysis.  */
@@ -271,7 +271,7 @@ index 2079ae9..ba7ade4 100644
      }
  
    /* Done saving and restoring */
-@@ -2949,7 +2970,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
+@@ -3037,7 +3058,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
  
    switch_to_section (s);
    assemble_align (POINTER_SIZE);
@@ -283,7 +283,7 @@ index 2079ae9..ba7ade4 100644
    output_addr_const (asm_out_file, symbol);
    fputs ("\n", asm_out_file);
  }
-@@ -3095,10 +3119,10 @@ microblaze_expand_prologue (void)
+@@ -3182,10 +3206,10 @@ microblaze_expand_prologue (void)
  	{
  	  if (offset != 0)
  	    ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
@@ -295,9 +295,9 @@ index 2079ae9..ba7ade4 100644
 -	  offset += GET_MODE_SIZE (SImode);
 +	  offset += GET_MODE_SIZE (Pmode);
  	}
- 
      }
-@@ -3108,15 +3132,23 @@ microblaze_expand_prologue (void)
+ 
+@@ -3194,15 +3218,23 @@ microblaze_expand_prologue (void)
        rtx fsiz_rtx = GEN_INT (fsiz);
  
        rtx_insn *insn = NULL;
@@ -323,7 +323,7 @@ index 2079ae9..ba7ade4 100644
  				 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
  					       const0_rtx));
  
-@@ -3124,7 +3156,7 @@ microblaze_expand_prologue (void)
+@@ -3210,7 +3242,7 @@ microblaze_expand_prologue (void)
  	    /* Do not optimize in flow analysis.  */
  	    MEM_VOLATILE_P (mem_rtx) = 1;
  
@@ -332,7 +332,7 @@ index 2079ae9..ba7ade4 100644
  	  insn = emit_move_insn (mem_rtx, reg_rtx);
  	  RTX_FRAME_RELATED_P (insn) = 1;
  	}
-@@ -3224,12 +3256,12 @@ microblaze_expand_epilogue (void)
+@@ -3320,12 +3352,12 @@ microblaze_expand_epilogue (void)
        if (!crtl->is_leaf || interrupt_handler)
  	{
  	  mem_rtx =
@@ -347,7 +347,7 @@ index 2079ae9..ba7ade4 100644
  	  emit_move_insn (reg_rtx, mem_rtx);
  	}
  
-@@ -3245,15 +3277,25 @@ microblaze_expand_epilogue (void)
+@@ -3341,15 +3373,25 @@ microblaze_expand_epilogue (void)
        /* _restore_ registers for epilogue.  */
        save_restore_insns (0);
        emit_insn (gen_blockage ());
@@ -377,7 +377,7 @@ index 2079ae9..ba7ade4 100644
    emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
  						    MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  }
-@@ -3402,9 +3444,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+@@ -3515,9 +3557,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
    else
      this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
  
@@ -394,7 +394,7 @@ index 2079ae9..ba7ade4 100644
  
    /* Apply the offset from the vtable, if required.  */
    if (vcall_offset)
-@@ -3417,7 +3464,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+@@ -3530,7 +3577,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
      rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
      emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
  
@@ -406,7 +406,7 @@ index 2079ae9..ba7ade4 100644
    }
  
    /* Generate a tail call to the target function.  */
-@@ -3564,7 +3614,7 @@ microblaze_eh_return (rtx op0)
+@@ -3704,7 +3754,7 @@ microblaze_eh_return (rtx op0)
  /* Queue an .ident string in the queue of top-level asm statements.
     If the string size is below the threshold, put it into .sdata2.
     If the front-end is done, we must be being called from toplev.c.
@@ -415,7 +415,7 @@ index 2079ae9..ba7ade4 100644
  void 
  microblaze_asm_output_ident (const char *string)
  {
-@@ -3619,9 +3669,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+@@ -3759,9 +3809,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
    emit_block_move (m_tramp, assemble_trampoline_template (),
  		   GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
  
@@ -427,7 +427,7 @@ index 2079ae9..ba7ade4 100644
    emit_move_insn (mem, fnaddr);
  }
  
-@@ -3645,7 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3785,7 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
      {
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
@@ -436,7 +436,7 @@ index 2079ae9..ba7ade4 100644
          emit_jump_insn (gen_condjump (condition, label1));
        else
          emit_jump_insn (gen_long_condjump (condition, label1));
-@@ -3764,7 +3814,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+@@ -3904,7 +3954,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
    rtx comp_reg = gen_reg_rtx (SImode);
  
    emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
@@ -445,7 +445,7 @@ index 2079ae9..ba7ade4 100644
    emit_jump_insn (gen_condjump (condition, operands[3]));
  }
  
-@@ -3774,10 +3824,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+@@ -3914,10 +3964,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
    rtx condition;
    rtx cmp_op0 = XEXP (operands[0], 0);
    rtx cmp_op1 = XEXP (operands[0], 1);
@@ -458,7 +458,7 @@ index 2079ae9..ba7ade4 100644
    emit_jump_insn (gen_long_condjump (condition, operands[3]));
  }
  
-@@ -3798,8 +3848,8 @@ microblaze_expand_divide (rtx operands[])
+@@ -3938,8 +3988,8 @@ microblaze_expand_divide (rtx operands[])
  {
    /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15).  */
  
@@ -469,7 +469,7 @@ index 2079ae9..ba7ade4 100644
    rtx regqi = gen_reg_rtx (QImode);
    rtx_code_label *div_label = gen_label_rtx ();
    rtx_code_label *div_end_label = gen_label_rtx ();
-@@ -3807,17 +3857,31 @@ microblaze_expand_divide (rtx operands[])
+@@ -3947,17 +3997,31 @@ microblaze_expand_divide (rtx operands[])
    rtx mem_rtx;
    rtx ret;
    rtx_insn *jump, *cjump, *insn;
@@ -508,7 +508,7 @@ index 2079ae9..ba7ade4 100644
    mem_rtx = gen_rtx_MEM (QImode,
                              gen_rtx_PLUS (QImode, regt1, div_table_rtx));
  
-@@ -3964,7 +4028,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+@@ -4104,7 +4168,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
                {
                  insn =
                    emit_insn_before (gen_iprefetch
@@ -517,7 +517,7 @@ index 2079ae9..ba7ade4 100644
                                      before_4);
                  recog_memoized (insn);
                  INSN_LOCATION (insn) = INSN_LOCATION (before_4);
-@@ -3974,7 +4038,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+@@ -4114,7 +4178,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
             }
         }
  }
@@ -546,7 +546,7 @@ index 2079ae9..ba7ade4 100644
  /* Insert instruction prefetch instruction at the fall
     through path of the function call.  */
  
-@@ -4127,6 +4211,17 @@ microblaze_starting_frame_offset (void)
+@@ -4267,6 +4351,17 @@ microblaze_starting_frame_offset (void)
  #undef TARGET_LRA_P
  #define TARGET_LRA_P hook_bool_void_false
  
@@ -564,7 +564,7 @@ index 2079ae9..ba7ade4 100644
  #undef TARGET_FRAME_POINTER_REQUIRED
  #define TARGET_FRAME_POINTER_REQUIRED	microblaze_frame_pointer_required
  
-@@ -4136,6 +4231,9 @@ microblaze_starting_frame_offset (void)
+@@ -4276,6 +4371,9 @@ microblaze_starting_frame_offset (void)
  #undef  TARGET_TRAMPOLINE_INIT
  #define TARGET_TRAMPOLINE_INIT		microblaze_trampoline_init
  
@@ -575,7 +575,7 @@ index 2079ae9..ba7ade4 100644
  #define TARGET_PROMOTE_FUNCTION_MODE 	default_promote_function_mode_always_promote
  
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 72fbee5..1e60513 100644
+index 2ca44f5..a23fd4e 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
@@ -710,7 +710,7 @@ index 72fbee5..1e60513 100644
  
  #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
  
-@@ -533,13 +551,13 @@ typedef struct microblaze_args
+@@ -529,13 +547,13 @@ typedef struct microblaze_args
     addresses which require two reload registers.  */
  #define LEGITIMATE_PIC_OPERAND_P(X)  microblaze_legitimate_pic_operand (X)
  
@@ -726,7 +726,7 @@ index 72fbee5..1e60513 100644
  #define MAX_MOVE_MAX				8
  
  #define SLOW_BYTE_ACCESS			1
-@@ -549,7 +567,7 @@ typedef struct microblaze_args
+@@ -545,7 +563,7 @@ typedef struct microblaze_args
  
  #define SHIFT_COUNT_TRUNCATED			1
  
@@ -735,7 +735,7 @@ index 72fbee5..1e60513 100644
  
  #define FUNCTION_MODE   SImode
  
-@@ -711,6 +729,7 @@ do {									\
+@@ -707,6 +725,7 @@ do {									\
  
  #undef TARGET_ASM_OUTPUT_IDENT
  #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
@@ -744,7 +744,7 @@ index 72fbee5..1e60513 100644
  /* Default to -G 8 */
  #ifndef MICROBLAZE_DEFAULT_GVALUE
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 0cd0441..0f41ac6 100644
+index eb52957..77627a7 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -26,6 +26,7 @@
@@ -755,7 +755,7 @@ index 0cd0441..0f41ac6 100644
    (R_SP        1)       ;; Stack pointer reg
    (R_SR       15)       ;; Sub-routine return addr reg
    (R_IR       14)       ;; Interrupt return addr reg
-@@ -539,6 +540,7 @@
+@@ -541,6 +542,7 @@
  
  ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
  ;; Leave carry as is
@@ -763,7 +763,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "addsi3"
    [(set (match_operand:SI 0 "register_operand" "=d,d,d")
  	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
-@@ -560,23 +562,38 @@
+@@ -562,23 +564,38 @@
  
  ;; Adding 2 DI operands in register or reg/imm
  
@@ -810,7 +810,7 @@ index 0cd0441..0f41ac6 100644
    "@
    add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
    addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
-@@ -603,7 +620,7 @@
+@@ -605,7 +622,7 @@
  (define_insn "iprefetch"
    [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
     (clobber (mem:BLK (scratch)))]
@@ -819,7 +819,7 @@ index 0cd0441..0f41ac6 100644
    {
      operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
      return "mfs\t%2,rpc\n\twic\t%2,r0";
-@@ -616,23 +633,33 @@
+@@ -618,23 +635,33 @@
  ;; Double Precision Subtraction
  ;;----------------------------------------------------------------
  
@@ -863,7 +863,7 @@ index 0cd0441..0f41ac6 100644
    "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
    [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
-@@ -661,7 +688,7 @@
+@@ -663,7 +690,7 @@
          (mult:DI
           (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
           (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
@@ -872,7 +872,7 @@ index 0cd0441..0f41ac6 100644
    "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
    [(set_attr "type"     "no_delay_arith")
     (set_attr "mode"     "DI")
-@@ -672,7 +699,7 @@
+@@ -674,7 +701,7 @@
          (mult:DI
           (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
           (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
@@ -881,7 +881,7 @@ index 0cd0441..0f41ac6 100644
    "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
    [(set_attr "type"     "no_delay_arith")
     (set_attr "mode"     "DI")
-@@ -683,7 +710,7 @@
+@@ -685,7 +712,7 @@
          (mult:DI
           (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
           (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
@@ -890,7 +890,7 @@ index 0cd0441..0f41ac6 100644
    "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
    [(set_attr "type"     "no_delay_arith")
     (set_attr "mode"     "DI")
-@@ -787,7 +814,7 @@
+@@ -789,7 +816,7 @@
                          (match_operand:SI 4 "arith_operand")])
                        (label_ref (match_operand 5))
                        (pc)))]
@@ -899,7 +899,7 @@ index 0cd0441..0f41ac6 100644
     [(set (match_dup 1) (match_dup 3))]
  
    {
-@@ -817,6 +844,15 @@
+@@ -819,6 +846,15 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -915,7 +915,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "negdi2_long"
    [(set (match_operand:DI 0 "register_operand" "=d")
  	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -845,16 +881,24 @@
+@@ -847,16 +883,24 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -944,7 +944,7 @@ index 0cd0441..0f41ac6 100644
    [(set (match_operand:DI 0 "register_operand" "=d")
  	(not:DI (match_operand:DI 1 "register_operand" "d")))]
    ""
-@@ -869,7 +913,8 @@
+@@ -871,7 +915,8 @@
  	(not:DI (match_operand:DI 1 "register_operand" "")))]
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -954,7 +954,7 @@ index 0cd0441..0f41ac6 100644
  
    [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
    (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
-@@ -881,18 +926,17 @@
+@@ -883,18 +928,17 @@
  ;;----------------------------------------------------------------
  
  (define_insn "anddi3"
@@ -981,7 +981,7 @@ index 0cd0441..0f41ac6 100644
  
  (define_insn "andsi3"
    [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-@@ -917,7 +961,7 @@
+@@ -919,7 +963,7 @@
    "@
     orl\t%0,%1,%2
     orli\t%0,%1,%2 #andl1"
@@ -990,7 +990,7 @@ index 0cd0441..0f41ac6 100644
    (set_attr "mode"	"DI,DI")
    (set_attr "length"	"4,4")])
  
-@@ -943,7 +987,7 @@
+@@ -945,7 +989,7 @@
    "@
     xorl\t%0,%1,%2
     xorli\t%0,%1,%2 #andl1"
@@ -999,7 +999,7 @@ index 0cd0441..0f41ac6 100644
    (set_attr "mode"	"DI,DI")
    (set_attr "length"	"4,4")])
  
-@@ -1016,26 +1060,6 @@
+@@ -1018,26 +1062,6 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"4")])
  
@@ -1026,7 +1026,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "extendhisi2"
    [(set (match_operand:SI 0 "register_operand" "=d")
  	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
-@@ -1058,6 +1082,27 @@
+@@ -1060,6 +1084,27 @@
  ;; Those for integer source operand are ordered
  ;; widest source type first.
  
@@ -1054,7 +1054,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "extendsidi2"
    [(set (match_operand:DI 0 "register_operand" "=d,d,d")
  	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-@@ -1088,68 +1133,117 @@
+@@ -1090,68 +1135,117 @@
  ;; Unlike most other insns, the move insns can't be split with
  ;; different predicates, because register spilling and other parts of
  ;; the compiler, have memoized the insn number already.
@@ -1208,7 +1208,7 @@ index 0cd0441..0f41ac6 100644
    { 
      switch (which_alternative)
      {
-@@ -1181,7 +1275,8 @@
+@@ -1183,7 +1277,8 @@
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
@@ -1218,7 +1218,7 @@ index 0cd0441..0f41ac6 100644
  
    [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
    (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-@@ -1193,12 +1288,22 @@
+@@ -1195,12 +1290,22 @@
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
@@ -1242,7 +1242,7 @@ index 0cd0441..0f41ac6 100644
  ;; Unlike most other insns, the move insns can't be split with
  ;; different predicates, because register spilling and other parts of
  ;; the compiler, have memoized the insn number already.
-@@ -1270,6 +1375,8 @@
+@@ -1272,6 +1377,8 @@
    (set_attr "length"	"4,4,8,4,8,4,8")])
  
  
@@ -1251,7 +1251,7 @@ index 0cd0441..0f41ac6 100644
  ;; 16-bit Integer moves
  
  ;; Unlike most other insns, the move insns can't be split with
-@@ -1302,8 +1409,8 @@
+@@ -1304,8 +1411,8 @@
    "@
     addik\t%0,r0,%1\t# %X1
     addk\t%0,%1,r0
@@ -1262,7 +1262,7 @@ index 0cd0441..0f41ac6 100644
     sh%i0\t%z1,%0
     sh%i0\t%z1,%0"
    [(set_attr "type"	"arith,move,load,no_delay_load,store,no_delay_store")
-@@ -1346,7 +1453,7 @@
+@@ -1348,7 +1455,7 @@
     lbu%i1\t%0,%1
     lbu%i1\t%0,%1
     sb%i0\t%z1,%0
@@ -1271,7 +1271,7 @@ index 0cd0441..0f41ac6 100644
    [(set_attr "type"	"arith,arith,move,load,no_delay_load,store,no_delay_store")
    (set_attr "mode"	"QI")
    (set_attr "length"	"4,4,8,4,8,4,8")])
-@@ -1419,7 +1526,7 @@
+@@ -1421,7 +1528,7 @@
     addik\t%0,r0,%F1
     lw%i1\t%0,%1
     sw%i0\t%z1,%0
@@ -1280,7 +1280,7 @@ index 0cd0441..0f41ac6 100644
    [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
    (set_attr "mode"      "SF")
    (set_attr "length"    "4,4,4,4,4,4,4")])
-@@ -1458,6 +1565,33 @@
+@@ -1460,6 +1567,33 @@
  ;; movdf_internal
  ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
  ;;
@@ -1314,7 +1314,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "*movdf_internal"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
          (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
-@@ -1492,7 +1626,8 @@
+@@ -1494,7 +1628,8 @@
    "reload_completed
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
@@ -1324,7 +1324,7 @@ index 0cd0441..0f41ac6 100644
    [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
    (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
    "")
-@@ -1503,7 +1638,8 @@
+@@ -1505,7 +1640,8 @@
    "reload_completed
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
@@ -1334,7 +1334,7 @@ index 0cd0441..0f41ac6 100644
    [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
    (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
    "")
-@@ -2003,6 +2139,31 @@ else
+@@ -2005,6 +2141,31 @@ else
    "
  )
  
@@ -1366,7 +1366,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "seq_internal_pat" 
    [(set (match_operand:SI 0 "register_operand" "=d")
  	(eq:SI 
-@@ -2063,8 +2224,8 @@ else
+@@ -2065,8 +2226,8 @@ else
  (define_expand "cbranchsi4"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
@@ -1377,7 +1377,7 @@ index 0cd0441..0f41ac6 100644
                        (label_ref (match_operand 3 ""))
                        (pc)))]
    ""
-@@ -2076,13 +2237,13 @@ else
+@@ -2078,13 +2239,13 @@ else
  (define_expand "cbranchsi4_reg"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
@@ -1394,7 +1394,7 @@ index 0cd0441..0f41ac6 100644
    DONE;
  })
  
-@@ -2107,6 +2268,26 @@ else
+@@ -2109,6 +2270,26 @@ else
  		      (label_ref (match_operand 1))
  		      (pc)))])
  
@@ -1421,7 +1421,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "branch_zero"
    [(set (pc)
  	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-@@ -2127,6 +2308,47 @@ else
+@@ -2129,6 +2310,47 @@ else
     (set_attr "length"	"4")]
  )
  
@@ -1469,7 +1469,7 @@ index 0cd0441..0f41ac6 100644
  (define_insn "branch_compare"
    [(set (pc)
          (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2310,7 +2532,7 @@ else
+@@ -2312,7 +2534,7 @@ else
  ;; Indirect jumps. Jump to register values. Assuming absolute jumps
  
  (define_insn "indirect_jump_internal1"
@@ -1478,16 +1478,16 @@ index 0cd0441..0f41ac6 100644
    ""
    "bra%?\t%0"
    [(set_attr "type"	"jump")
-@@ -2323,7 +2545,7 @@ else
+@@ -2325,7 +2547,7 @@ else
    (use (label_ref (match_operand 1 "" "")))]
    ""
    {
 -    gcc_assert (GET_MODE (operands[0]) == Pmode);
 +    //gcc_assert (GET_MODE (operands[0]) == Pmode);
  
-     if (!flag_pic)
+     if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
        emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-@@ -2335,7 +2557,7 @@ else
+@@ -2337,7 +2559,7 @@ else
  
  (define_insn "tablejump_internal1"
    [(set (pc)
@@ -1496,7 +1496,7 @@ index 0cd0441..0f41ac6 100644
    (use (label_ref (match_operand 1 "" "")))]
    ""
    "bra%?\t%0 "
-@@ -2345,9 +2567,9 @@ else
+@@ -2347,9 +2569,9 @@ else
  
  (define_expand "tablejump_internal3"
    [(parallel [(set (pc)
@@ -1509,7 +1509,7 @@ index 0cd0441..0f41ac6 100644
    ""
    ""
  )
-@@ -2408,7 +2630,7 @@ else
+@@ -2410,7 +2632,7 @@ else
  	(minus (reg 1) (match_operand 1 "register_operand" "")))
     (set (reg 1)
  	(minus (reg 1) (match_dup 1)))]
@@ -1518,7 +1518,7 @@ index 0cd0441..0f41ac6 100644
    { 
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
      rtx reg = gen_reg_rtx (Pmode);
-@@ -2433,7 +2655,7 @@ else
+@@ -2435,7 +2657,7 @@ else
  (define_expand "save_stack_block"
    [(match_operand 0 "register_operand" "")
     (match_operand 1 "register_operand" "")]
@@ -1527,7 +1527,7 @@ index 0cd0441..0f41ac6 100644
    {
      emit_move_insn (operands[0], operands[1]);
      DONE;
-@@ -2443,7 +2665,7 @@ else
+@@ -2445,7 +2667,7 @@ else
  (define_expand "restore_stack_block"
    [(match_operand 0 "register_operand" "")
     (match_operand 1 "register_operand" "")]
@@ -1536,7 +1536,7 @@ index 0cd0441..0f41ac6 100644
    {
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
      rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-@@ -2490,7 +2712,7 @@ else
+@@ -2492,7 +2714,7 @@ else
  
  (define_insn "<optab>_internal"
    [(any_return)
@@ -1545,7 +1545,7 @@ index 0cd0441..0f41ac6 100644
    ""
    {
      if (microblaze_is_break_handler ())
-@@ -2523,7 +2745,7 @@ else
+@@ -2525,7 +2747,7 @@ else
  (define_expand "call"
    [(parallel [(call (match_operand 0 "memory_operand" "m")
  		    (match_operand 1 "" "i"))
@@ -1554,7 +1554,7 @@ index 0cd0441..0f41ac6 100644
               (use (match_operand 2 "" ""))
               (use (match_operand 3 "" ""))])]
    ""
-@@ -2543,12 +2765,12 @@ else
+@@ -2546,12 +2768,12 @@ else
  
      if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
        emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
@@ -1569,7 +1569,7 @@ index 0cd0441..0f41ac6 100644
  				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  
          DONE;
-@@ -2558,7 +2780,7 @@ else
+@@ -2561,7 +2783,7 @@ else
  (define_expand "call_internal0"
    [(parallel [(call (match_operand 0 "" "")
  		    (match_operand 1 "" ""))
@@ -1578,7 +1578,7 @@ index 0cd0441..0f41ac6 100644
    ""
    {
    }
-@@ -2567,18 +2789,34 @@ else
+@@ -2570,18 +2792,34 @@ else
  (define_expand "call_internal_plt0"
    [(parallel [(call (match_operand 0 "" "")
  		    (match_operand 1 "" ""))
@@ -1619,7 +1619,7 @@ index 0cd0441..0f41ac6 100644
    "flag_pic"
    {
      register rtx target2 = gen_rtx_REG (Pmode, 
-@@ -2590,10 +2828,41 @@ else
+@@ -2593,10 +2831,41 @@ else
    (set_attr "mode"	"none")
    (set_attr "length"	"4")])
  
@@ -1663,7 +1663,7 @@ index 0cd0441..0f41ac6 100644
    ""
    {
      register rtx target = operands[0];
-@@ -2627,7 +2896,7 @@ else
+@@ -2630,7 +2899,7 @@ else
    [(parallel [(set (match_operand 0 "register_operand" "=d")
  		   (call (match_operand 1 "memory_operand" "m")
  			 (match_operand 2 "" "i")))
@@ -1672,7 +1672,7 @@ index 0cd0441..0f41ac6 100644
               (use (match_operand 3 "" ""))])] ;; next_arg_reg
    ""
    {
-@@ -2647,13 +2916,13 @@ else
+@@ -2651,13 +2920,13 @@ else
      if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
        emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
  			operands[2],
@@ -1688,7 +1688,7 @@ index 0cd0441..0f41ac6 100644
  				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  
      DONE;
-@@ -2665,7 +2934,7 @@ else
+@@ -2669,7 +2938,7 @@ else
    [(parallel [(set (match_operand 0 "" "")
  		   (call (match_operand 1 "" "")
  			 (match_operand 2 "" "")))
@@ -1697,7 +1697,7 @@ index 0cd0441..0f41ac6 100644
               ])]
    ""
    {}
-@@ -2675,18 +2944,35 @@ else
+@@ -2679,18 +2948,35 @@ else
    [(parallel[(set (match_operand 0 "" "")
                    (call (match_operand 1 "" "")
                          (match_operand 2 "" "")))
@@ -1739,7 +1739,7 @@ index 0cd0441..0f41ac6 100644
    "flag_pic"
    { 
      register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-@@ -2698,11 +2984,46 @@ else
+@@ -2702,11 +2988,46 @@ else
    (set_attr "mode"	"none")
    (set_attr "length"	"4")])
  
@@ -1788,7 +1788,7 @@ index 0cd0441..0f41ac6 100644
    ""
    { 
      register rtx target = operands[1];
-@@ -2864,7 +3185,6 @@ else
+@@ -2880,7 +3201,6 @@ else
  
    ;;if (!register_operand (operands[0], VOIDmode))
    ;;  FAIL;
@@ -1816,7 +1816,7 @@ index 7671f63..9fc80b1 100644
  # Extra files
  microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
 diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index 2e15be4..3386520 100644
+index ee380ee..1811327 100644
 --- a/libgcc/config/microblaze/crti.S
 +++ b/libgcc/config/microblaze/crti.S
 @@ -40,7 +40,7 @@
@@ -1836,7 +1836,7 @@ index 2e15be4..3386520 100644
 +    addik   r1, r1, -16
      sw      r15, r0, r1
 diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index cd5fd9e..04e73d7 100644
+index 00d398a..60a4648 100644
 --- a/libgcc/config/microblaze/crtn.S
 +++ b/libgcc/config/microblaze/crtn.S
 @@ -33,9 +33,9 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0042-re-arrangement-of-the-compare-branches.patch
index c33b247bf..3afb76299 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0042-re-arrangement-of-the-compare-branches.patch
@@ -1,7 +1,7 @@
-From 9e45ca7bd65fe327e01e93d3c539c9d8cf049b79 Mon Sep 17 00:00:00 2001
+From 31062878a2c1773a1fc94242ad29e6d03e4828b1 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 3 Aug 2018 15:41:39 +0530
-Subject: [PATCH 42/54] re-arrangement of the compare branches
+Subject: [PATCH 42/63] re-arrangement of the compare branches
 
 ---
  gcc/config/microblaze/microblaze.c  |  28 ++-----
@@ -9,10 +9,10 @@ Subject: [PATCH 42/54] re-arrangement of the compare branches
  2 files changed, 73 insertions(+), 96 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index ba7ade4..fab79d9 100644
+index d5ff7af..dd46d93 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3695,11 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3835,11 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
      {
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
@@ -25,7 +25,7 @@ index ba7ade4..fab79d9 100644
      }
  
    else if (code == EQ || code == NE)
-@@ -3710,10 +3706,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3850,10 +3846,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
        else
          emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
        condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
@@ -37,7 +37,7 @@ index ba7ade4..fab79d9 100644
      }
    else
      {
-@@ -3746,10 +3739,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3886,10 +3879,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code),
                                    mode, comp_reg, const0_rtx);
@@ -49,7 +49,7 @@ index ba7ade4..fab79d9 100644
      }
    else if (code == EQ)
      {
-@@ -3764,10 +3754,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3904,10 +3894,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
                                             cmp_op1));
  	}
        condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
@@ -61,7 +61,7 @@ index ba7ade4..fab79d9 100644
   
      }
    else if (code == NE)
-@@ -3783,10 +3770,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3923,10 +3910,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
                                             cmp_op1));
  	}
        condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
@@ -73,7 +73,7 @@ index ba7ade4..fab79d9 100644
      }
    else
      {
-@@ -3828,7 +3812,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+@@ -3968,7 +3952,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
  
    emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
    condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
@@ -83,10 +83,10 @@ index ba7ade4..fab79d9 100644
  
  /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 0f41ac6..2213d6e 100644
+index 77627a7..edb7aab 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2268,7 +2268,27 @@ else
+@@ -2270,7 +2270,27 @@ else
  		      (label_ref (match_operand 1))
  		      (pc)))])
  
@@ -115,7 +115,7 @@ index 0f41ac6..2213d6e 100644
    [(set (pc)
  	(if_then_else (match_operator 0 "ordered_comparison_operator"
    				 [(match_operand 1 "register_operand" "d")
-@@ -2279,9 +2299,9 @@ else
+@@ -2281,9 +2301,9 @@ else
    "TARGET_MB_64"
    {
      if (operands[3] == pc_rtx) 
@@ -127,7 +127,7 @@ index 0f41ac6..2213d6e 100644
    }
    [(set_attr "type"	"branch")
     (set_attr "mode"	"none")
-@@ -2310,9 +2330,9 @@ else
+@@ -2312,9 +2332,9 @@ else
  
  (define_insn "branch_compare64"
    [(set (pc)
@@ -140,7 +140,7 @@ index 0f41ac6..2213d6e 100644
                                           ])
                        (label_ref (match_operand 3))
                        (pc)))
-@@ -2349,6 +2369,47 @@ else
+@@ -2351,6 +2371,47 @@ else
     (set_attr "length"   "12")]
  )
  
@@ -188,7 +188,7 @@ index 0f41ac6..2213d6e 100644
  (define_insn "branch_compare"
    [(set (pc)
          (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2431,74 +2492,6 @@ else
+@@ -2433,74 +2494,6 @@ else
  
  })
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
index d1cf45798..f40748991 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
@@ -1,7 +1,7 @@
-From 0c132e74714d217108d65fca630ab497a0d8821a Mon Sep 17 00:00:00 2001
+From 7ab47599c2bec80d622883b3e220827dce89c598 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 8 Aug 2018 17:37:26 +0530
-Subject: [PATCH 43/54] [Patch,Microblaze] :  previous commit broke the
+Subject: [PATCH 43/63] [Patch,Microblaze] :  previous commit broke the
  handling of SI Branch compare for Microblaze 32-bit..
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 43/54] [Patch,Microblaze] :  previous commit broke the
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 2213d6e..53ea401 100644
+index edb7aab..fb22edb 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2224,8 +2224,8 @@ else
+@@ -2226,8 +2226,8 @@ else
  (define_expand "cbranchsi4"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
index 68791cb24..ad287e573 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
@@ -1,7 +1,7 @@
-From 259ed1ee33625964f5bc394ae660103b6c35510f Mon Sep 17 00:00:00 2001
+From 23622921a153258de469ff10db4926b83ff0c432 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 11 Sep 2018 13:43:48 +0530
-Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ...
+Subject: [PATCH 44/63] [Patch, Microblaze] : Support of multilibs with m64 ...
 
 ---
  gcc/config/microblaze/microblaze-c.c  |  1 +
@@ -10,7 +10,7 @@ Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ...
  3 files changed, 10 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index d8a1d13..6586575 100644
+index d2b0c76..6670091 100644
 --- a/gcc/config/microblaze/microblaze-c.c
 +++ b/gcc/config/microblaze/microblaze-c.c
 @@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
@@ -22,7 +22,7 @@ index d8a1d13..6586575 100644
        builtin_define ("__microblaze64__");
        builtin_define ("__MICROBLAZE64__");
 diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 9fc80b1..35ab965 100644
+index 9fc80b1..35ab9654 100644
 --- a/gcc/config/microblaze/t-microblaze
 +++ b/gcc/config/microblaze/t-microblaze
 @@ -1,12 +1,9 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0045-Fixed-issues-like.patch
index 8c0bde713..3f5f78271 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0045-Fixed-issues-like.patch
@@ -1,7 +1,7 @@
-From 654582846ebf847b52e769eb6e015c8e486461d6 Mon Sep 17 00:00:00 2001
+From 6e6fcbe5fafcbebaf63ff071ad947966af0c1559 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 11 Sep 2018 14:58:00 +0530
-Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
+Subject: [PATCH 45/63] Fixed issues like: 1 Interrupt alignment issue 2 Sign
  extension issue
 
 ---
@@ -10,10 +10,10 @@ Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
  2 files changed, 11 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index fab79d9..6b6ca61 100644
+index dd46d93..bfa667b 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2241,9 +2241,14 @@ compute_frame_size (HOST_WIDE_INT size)
+@@ -2317,9 +2317,14 @@ compute_frame_size (HOST_WIDE_INT size)
  
    total_size += gp_reg_size;
  
@@ -30,7 +30,7 @@ index fab79d9..6b6ca61 100644
  
    /* No space to be allocated for link register in leaf functions with no other
       stack requirements.  */
-@@ -2527,7 +2532,6 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2604,7 +2609,6 @@ print_operand (FILE * file, rtx op, int letter)
    else if (letter == 'h' || letter == 'j')
      {
        long val[2];
@@ -38,7 +38,7 @@ index fab79d9..6b6ca61 100644
        long l[2];
        if (code == CONST_DOUBLE)
  	{
-@@ -2542,10 +2546,10 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2619,10 +2623,10 @@ print_operand (FILE * file, rtx op, int letter)
  	}
        else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
          {
@@ -53,10 +53,10 @@ index fab79d9..6b6ca61 100644
    else if (code == CONST_DOUBLE)
      {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 53ea401..3a6943b 100644
+index fb22edb..4a8fbab 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -1094,7 +1094,7 @@
+@@ -1096,7 +1096,7 @@
        case 1:
        case 2:
          {
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0046-Fixed-below-issues.patch
index 22bb5b2f9..fc2fe3b57 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0046-Fixed-below-issues.patch
@@ -1,22 +1,27 @@
-From 48f9f9a1c6809b14e7cfdd2343df92c0de18d730 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 28 Sep 2018 11:59:12 +0530
-Subject: [PATCH 46/54] Fixed below issues: - Floating point print issues in
- 64bit mode - Dejagnu Jump related issues - Added dbl instruction
+From 7c911a5ae8cf4a7496c059374f170f1919c00f6d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 26 Nov 2019 17:26:15 +0530
+Subject: [PATCH 46/63] Fixed below issues:
 
+- Floating point print issues in 64bit mode
+- Dejagnu Jump related issues
+- Added dbl instruction
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
 ---
- gcc/config/microblaze/microblaze.c  | 12 ++++-
+ gcc/config/microblaze/microblaze.c  | 12 +++++-
  gcc/config/microblaze/microblaze.h  |  7 +++
- gcc/config/microblaze/microblaze.md | 89 ++++++++++++++++++++++++++++++-------
- libgcc/config/microblaze/crti.S     | 24 +++++++++-
+ gcc/config/microblaze/microblaze.md | 86 +++++++++++++++++++++++++++++++------
+ libgcc/config/microblaze/crti.S     | 24 ++++++++++-
  libgcc/config/microblaze/crtn.S     | 13 ++++++
- 5 files changed, 127 insertions(+), 18 deletions(-)
+ 5 files changed, 125 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 6b6ca61..33d183e 100644
+index bfa667b..220e03d 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2536,7 +2536,12 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2613,7 +2613,12 @@ print_operand (FILE * file, rtx op, int letter)
        if (code == CONST_DOUBLE)
  	{
  	  if (GET_MODE (op) == DFmode)
@@ -30,7 +35,7 @@ index 6b6ca61..33d183e 100644
  	  else
  	    {
                REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-@@ -3874,7 +3879,10 @@ microblaze_expand_divide (rtx operands[])
+@@ -4014,7 +4019,10 @@ microblaze_expand_divide (rtx operands[])
                              gen_rtx_PLUS (QImode, regt1, div_table_rtx));
  
    insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
@@ -43,10 +48,10 @@ index 6b6ca61..33d183e 100644
    LABEL_NUSES (div_end_label) = 1; 
    emit_barrier ();
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 1e60513..e34f549 100644
+index a23fd4e..7497cfb 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
-@@ -892,10 +892,17 @@ do {									 \
+@@ -888,10 +888,17 @@ do {									 \
  /* We do this to save a few 10s of code space that would be taken up
     by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
     definition in crtstuff.c.  */
@@ -65,10 +70,10 @@ index 1e60513..e34f549 100644
  /* We need to group -lm as well, since some Newlib math functions 
     reference __errno!  */
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 3a6943b..2669a28 100644
+index 4a8fbab..65ec32c 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -525,6 +525,15 @@
+@@ -527,6 +527,15 @@
    (set_attr "mode"      "SF")
    (set_attr "length"    "4")])
  
@@ -84,7 +89,7 @@ index 3a6943b..2669a28 100644
  (define_insn "fix_truncsfsi2"
    [(set (match_operand:SI 0 "register_operand" "=d")
          (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-@@ -1298,7 +1307,7 @@
+@@ -1300,7 +1309,7 @@
  (define_insn "movdi_long_int"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
  	(match_operand:DI 1 "general_operand"      "i"))]
@@ -93,7 +98,7 @@ index 3a6943b..2669a28 100644
    "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
    [(set_attr "type"	"no_delay_arith")
    (set_attr "mode"	"DI")
-@@ -1581,7 +1590,7 @@
+@@ -1583,7 +1592,7 @@
            return "ll%i1\t%0,%1";
        case 3:
        {
@@ -102,7 +107,7 @@ index 3a6943b..2669a28 100644
        }
        case 5:
  	return "sl%i0\t%1,%0";
-@@ -2371,9 +2380,9 @@ else
+@@ -2373,9 +2382,9 @@ else
  
  (define_insn "long_branch_compare"
    [(set (pc)
@@ -115,7 +120,7 @@ index 3a6943b..2669a28 100644
                                           ])
                        (label_ref (match_operand 3))
                        (pc)))
-@@ -2495,6 +2504,20 @@ else
+@@ -2497,6 +2506,20 @@ else
  ;;----------------------------------------------------------------
  ;; Unconditional branches
  ;;----------------------------------------------------------------
@@ -136,28 +141,24 @@ index 3a6943b..2669a28 100644
  (define_insn "jump"
    [(set (pc)
  	(label_ref (match_operand 0 "" "")))]
-@@ -2538,19 +2561,28 @@ else
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
+@@ -2542,17 +2565,25 @@ else
    {
--    //gcc_assert (GET_MODE (operands[0]) == Pmode);
--
-+    gcc_assert (GET_MODE (operands[0]) == Pmode);
-+    
-     if (!flag_pic)
+     //gcc_assert (GET_MODE (operands[0]) == Pmode);
+ 
+-    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
 -      emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
 -    else
 -      emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-+      {
-+ 	if (!TARGET_MB_64)
++    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) {
++        if (!TARGET_MB_64)
 +          emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-+	else
++        else
 +          emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
 +      }
 +    else {
-+ 	if (!TARGET_MB_64)
++        if (!TARGET_MB_64)
 +          emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-+	else
++        else
 +          emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
 +      }
      DONE;
@@ -171,7 +172,7 @@ index 3a6943b..2669a28 100644
    (use (label_ref (match_operand 1 "" "")))]
    ""
    "bra%?\t%0 "
-@@ -2558,11 +2590,21 @@ else
+@@ -2560,11 +2591,21 @@ else
    (set_attr "mode"	"none")
    (set_attr "length"	"4")])
  
@@ -196,7 +197,7 @@ index 3a6943b..2669a28 100644
    ""
    ""
  )
-@@ -2593,6 +2635,23 @@ else
+@@ -2595,6 +2636,23 @@ else
    ""
  )
  
@@ -220,7 +221,7 @@ index 3a6943b..2669a28 100644
  ;;----------------------------------------------------------------
  ;; Function prologue/epilogue and stack allocation
  ;;----------------------------------------------------------------
-@@ -3097,7 +3156,7 @@ else
+@@ -3101,7 +3159,7 @@ else
  ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
  ;; between "mfs" and "addik" instructions.
  (define_insn "set_got"
@@ -230,7 +231,7 @@ index 3a6943b..2669a28 100644
    ""
    "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
 diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index 3386520..3d4cde2 100644
+index 1811327..a661319 100644
 --- a/libgcc/config/microblaze/crti.S
 +++ b/libgcc/config/microblaze/crti.S
 @@ -33,11 +33,32 @@
@@ -273,7 +274,7 @@ index 3386520..3d4cde2 100644
      sw      r15, r0, r1
 +#endif
 diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index 04e73d7..c262ce0 100644
+index 60a4648..d72507b 100644
 --- a/libgcc/config/microblaze/crtn.S
 +++ b/libgcc/config/microblaze/crtn.S
 @@ -29,7 +29,19 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0047-Added-double-arith-instructions.patch
index f28d9f516..1b7ac28b1 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0047-Added-double-arith-instructions.patch
@@ -1,7 +1,7 @@
-From b09721c830dd0831f50084e2e64920f83618e3f4 Mon Sep 17 00:00:00 2001
+From 0f310964ff1c19cbc3404ec7ceba286d6de315c0 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 9 Oct 2018 10:07:08 +0530
-Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack
+Subject: [PATCH 47/63] -Added double arith instructions -Fixed prologue stack
  pointer decrement issue
 
 ---
@@ -10,10 +10,10 @@ Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack
  2 files changed, 76 insertions(+), 9 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 2669a28..dca61d6 100644
+index 65ec32c..c199b27 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -525,6 +525,66 @@
+@@ -527,6 +527,66 @@
    (set_attr "mode"      "SF")
    (set_attr "length"    "4")])
  
@@ -80,7 +80,7 @@ index 2669a28..dca61d6 100644
  (define_insn "floatdidf2"
    [(set (match_operand:DF 0 "register_operand" "=d")
          (float:DF (match_operand:DI 1 "register_operand" "d")))]
-@@ -534,13 +594,13 @@
+@@ -536,13 +596,13 @@
    (set_attr "mode"      "DF")
    (set_attr "length"    "4")])
  
@@ -101,7 +101,7 @@ index 2669a28..dca61d6 100644
    (set_attr "length"    "4")])
  
  ;;----------------------------------------------------------------
-@@ -658,8 +718,8 @@
+@@ -660,8 +720,8 @@
    "TARGET_MB_64"
    "@
     rsubl\t%0,%2,%1
@@ -113,7 +113,7 @@ index 2669a28..dca61d6 100644
    (set_attr "mode"	"DI")
    (set_attr "length"	"4,4,4")])
 diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 35ab965..dfef45c 100644
+index 35ab9654..dfef45c 100644
 --- a/gcc/config/microblaze/t-microblaze
 +++ b/gcc/config/microblaze/t-microblaze
 @@ -1,6 +1,13 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
index 9a214d55a..c00b0a2ba 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -1,7 +1,7 @@
-From 1ed548dd5993b8c3e58ef393467bdeea49c437be Mon Sep 17 00:00:00 2001
+From b63cd2a410b9350fa67ed3ca348dcca349da4e44 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 12 Oct 2018 16:07:36 +0530
-Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap
+Subject: [PATCH 48/63] Fixed the issue in the delay slot with swap
  instructions
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap
  1 file changed, 6 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index dca61d6..d037843 100644
+index c199b27..d6370d8 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -441,6 +441,9 @@
+@@ -443,6 +443,9 @@
          (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
    "TARGET_REORDER"
    "swapb %0, %1"
@@ -22,7 +22,7 @@ index dca61d6..d037843 100644
  )
  
  (define_insn "bswaphi2"
-@@ -449,6 +452,9 @@
+@@ -451,6 +454,9 @@
    "TARGET_REORDER"
    "swapb %0, %1
     swaph %0, %0"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
index a682bc19d..7e92df2e9 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -1,7 +1,7 @@
-From 1c889b64454f63f164f34d79d891d91b0bb4731f Mon Sep 17 00:00:00 2001
+From f39f36cb0f0466343ef4ead50261b58595af708c Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Sat, 13 Oct 2018 21:12:43 +0530
-Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith
+Subject: [PATCH 49/63] Fixed the load store issue with the 32bit arith
  libraries
 
 ---
@@ -13,7 +13,7 @@ Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith
  5 files changed, 98 insertions(+), 4 deletions(-)
 
 diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index 663d398..7e7d875 100644
+index 24b94b9..2765e42 100644
 --- a/libgcc/config/microblaze/divsi3.S
 +++ b/libgcc/config/microblaze/divsi3.S
 @@ -41,6 +41,17 @@
@@ -70,7 +70,7 @@ index 663d398..7e7d875 100644
  	.size	__divsi3, . - __divsi3
  
 diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 71b56e30..7e85064 100644
+index 87372f5..7e61453 100644
 --- a/libgcc/config/microblaze/modsi3.S
 +++ b/libgcc/config/microblaze/modsi3.S
 @@ -41,6 +41,17 @@
@@ -128,7 +128,7 @@ index 71b56e30..7e85064 100644
  	.size	__modsi3, . - __modsi3
  
 diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index 40b0b15..31a73c2 100644
+index 8c3f788..e28c69a 100644
 --- a/libgcc/config/microblaze/mulsi3.S
 +++ b/libgcc/config/microblaze/mulsi3.S
 @@ -41,6 +41,9 @@
@@ -142,7 +142,7 @@ index 40b0b15..31a73c2 100644
  	.frame	r1,0,r15
  	add	r3,r0,r0
 diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index 2aef8ed..94adb6a 100644
+index 5d726ad..b1e44b6 100644
 --- a/libgcc/config/microblaze/udivsi3.S
 +++ b/libgcc/config/microblaze/udivsi3.S
 @@ -41,6 +41,16 @@
@@ -197,7 +197,7 @@ index 2aef8ed..94adb6a 100644
          .end __udivsi3
  	.size	__udivsi3, . - __udivsi3
 diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index a2582d0..00b3bdf 100644
+index b29d7e1..8804b99 100644
 --- a/libgcc/config/microblaze/umodsi3.S
 +++ b/libgcc/config/microblaze/umodsi3.S
 @@ -41,6 +41,16 @@
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
index 95a26db2c..ba717327e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -1,14 +1,14 @@
-From 751a01ce1eeaffcd41c504b9bf44868345b45da0 Mon Sep 17 00:00:00 2001
+From 51886f40b6bccea22277f8dcc971706d7c24bdd0 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Mon, 15 Oct 2018 12:00:10 +0530
-Subject: [PATCH 50/54] extending the Dwarf support to 64bit Microblaze
+Subject: [PATCH 50/63] extending the Dwarf support to 64bit Microblaze
 
 ---
  gcc/config/microblaze/microblaze.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index e34f549..0a5ff0a 100644
+index 7497cfb..bd5e216 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0051-fixing-the-typo-errors-in-umodsi3-file.patch
index 574037ecf..a0758b319 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0051-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -1,14 +1,14 @@
-From 295046d0a63148fb5a685ae2bd7a06489274c72a Mon Sep 17 00:00:00 2001
+From a8978d71c8b5adfa59430443611bd785a4d54ef9 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 16 Oct 2018 07:55:46 +0530
-Subject: [PATCH 51/54] fixing the typo errors in umodsi3 file
+Subject: [PATCH 51/63] fixing the typo errors in umodsi3 file
 
 ---
  libgcc/config/microblaze/umodsi3.S | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 00b3bdf..9bf65c3 100644
+index 8804b99..1b3070e 100644
 --- a/libgcc/config/microblaze/umodsi3.S
 +++ b/libgcc/config/microblaze/umodsi3.S
 @@ -47,9 +47,9 @@ __umodsi3:
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
index 95d39bb28..d0b534bcb 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -1,14 +1,14 @@
-From d55eff09f175ddbc66e4e800fa5650ce9e2f599e Mon Sep 17 00:00:00 2001
+From 328bd339c292b63d2068a132a245bdc037815d6b Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 17 Oct 2018 16:56:14 +0530
-Subject: [PATCH 52/54] fixing the 32bit LTO related issue9(1014024)
+Subject: [PATCH 52/63] fixing the 32bit LTO related issue9(1014024)
 
 ---
  gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
  1 file changed, 14 insertions(+), 10 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 0a5ff0a..740b8d9 100644
+index bd5e216..ab541f7 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
index e992075b9..f8ac364c3 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -1,7 +1,7 @@
-From 3e7161218dc8b4dd84ad8d31f6dbaa7c256e7a82 Mon Sep 17 00:00:00 2001
+From 3f65f0432d42f4d469fbb10828f1683cd30a5d84 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 19 Oct 2018 14:26:25 +0530
-Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of
+Subject: [PATCH 53/63] Fixed the missing stack adjustment in prologue of
  modsi3 function
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of
  1 file changed, 1 insertion(+)
 
 diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 7e85064..46ff34a 100644
+index 7e61453..b0e6cad 100644
 --- a/libgcc/config/microblaze/modsi3.S
 +++ b/libgcc/config/microblaze/modsi3.S
 @@ -119,6 +119,7 @@ $LaRETURN_HERE:
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
index afb88d350..0e7045060 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
@@ -1,7 +1,7 @@
-From a89b3e6902d7835129ad178f6af896eba15c5d5e Mon Sep 17 00:00:00 2001
+From 0dbb2b7bfe466c18d54aec680208fd1459619bc1 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 24 Oct 2018 18:31:04 +0530
-Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong
+Subject: [PATCH 54/63] [Patch,Microblaze] : corrected SPN for dlong
  instruction mapping.
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index d037843..cbd7e77 100644
+index d6370d8..6b6b7c6 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -600,9 +600,9 @@
+@@ -602,9 +602,9 @@
    (set_attr "mode"      "DF")
    (set_attr "length"    "4")])
  
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
index 4c694723d..285547222 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -1,7 +1,7 @@
-From 76e231f92afd8fda13d6ae18ef3aef0ea6096489 Mon Sep 17 00:00:00 2001
+From a56b23ae244eee1da6d6595d3a6477085d77271e Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Thu, 29 Nov 2018 17:55:08 +0530
-Subject: [PATCH 55/57] fixing the long & long long mingw toolchain issue
+Subject: [PATCH 55/63] fixing the long & long long mingw toolchain issue
 
 ---
  gcc/config/microblaze/constraints.md | 2 +-
@@ -9,7 +9,7 @@ Subject: [PATCH 55/57] fixing the long & long long mingw toolchain issue
  2 files changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index 867a7b5..27c6bfc 100644
+index 2fce91e..9a5aa6b 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -55,7 +55,7 @@
@@ -22,10 +22,10 @@ index 867a7b5..27c6bfc 100644
  ;; Define floating point constraints
  
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index cbd7e77..e03b835 100644
+index 6b6b7c6..a1dc41f 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -646,8 +646,8 @@
+@@ -648,8 +648,8 @@
    if (TARGET_MB_64) 
     {
       if (GET_CODE (operands[2]) == CONST_INT &&
@@ -36,7 +36,7 @@ index cbd7e77..e03b835 100644
        FAIL;
     }
  })
-@@ -1264,7 +1264,7 @@
+@@ -1266,7 +1266,7 @@
  	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
    "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
             (GET_CODE (operands[1]) == CONST_INT && 
@@ -45,7 +45,7 @@ index cbd7e77..e03b835 100644
    "@
     addlk\t%0,r0,r0\t
     addlik\t%0,r0,%1\t #N1 %X1
-@@ -1298,7 +1298,7 @@
+@@ -1300,7 +1300,7 @@
       case 1:
       case 2:
          if (GET_CODE (operands[1]) == CONST_INT && 
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-microblaze_linker_script_xilinx_ld.patch
index c009c92d2..c009c92d2 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-microblaze_linker_script_xilinx_ld.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 000000000..a419216c5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
+From e13b1b70972511a642512cbc7093ed21e5a9e141 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 14 Mar 2019 18:11:04 +0530
+Subject: [PATCH 56/63] Fix the MB-64 bug of handling QI objects
+
+---
+ gcc/config/microblaze/microblaze.md | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index a1dc41f..bb96e2d 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2347,11 +2347,11 @@ else
+ 
+ (define_insn "branch_zero_64"
+   [(set (pc)
+-	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
+   				 [(match_operand:SI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand:SI 2 "pc_or_label_operand" "")
+-                      (match_operand:SI 3 "pc_or_label_operand" "")))
++                      (match_operand 2 "pc_or_label_operand" "")
++                      (match_operand 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+@@ -2367,11 +2367,11 @@ else
+ 
+ (define_insn "long_branch_zero"
+   [(set (pc)
+-	(if_then_else (match_operator 0 "ordered_comparison_operator"
+-  				 [(match_operand 1 "register_operand" "d")
++	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
++				 [(match_operand:DI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand 2 "pc_or_label_operand" "")
+-                      (match_operand 3 "pc_or_label_operand" "")))
++                      (match_operand:DI 2 "pc_or_label_operand" "")
++                      (match_operand:DI 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch
new file mode 100644
index 000000000..ff5247703
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch
@@ -0,0 +1,36 @@
+From f30b99b5b8d3f2a8d8e4973cd155a4b9f1849039 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 14 Mar 2019 18:08:06 +0530
+Subject: [PATCH 56/57] fix the lto-wrapper issue on windows
+
+---
+ libiberty/simple-object.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/libiberty/simple-object.c b/libiberty/simple-object.c
+index 42aa6ac..d2465c6 100644
+--- a/libiberty/simple-object.c
++++ b/libiberty/simple-object.c
+@@ -44,6 +44,10 @@ Boston, MA 02110-1301, USA.  */
+ #define SEEK_SET 0
+ #endif
+ 
++#ifndef O_BINARY
++#define O_BINARY 0
++#endif
++
+ #include "simple-object-common.h"
+ 
+ /* The known object file formats.  */
+@@ -326,7 +330,7 @@ simple_object_copy_lto_debug_sections (simple_object_read *sobj,
+       return errmsg;
+     }
+ 
+-  outfd = creat (dest, 00777);
++  outfd = open (dest, O_CREAT|O_WRONLY|O_TRUNC|O_BINARY, 00777);
+   if (outfd == -1)
+     {
+       *err = errno;
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
index a5a2039d9..a5a2039d9 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 000000000..940009de8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
+From 1387d4fedb397f78b08ad33204a3fcf2bd63f183 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Fri, 29 Mar 2019 12:08:39 +0530
+Subject: [PATCH 57/63] [Patch,Microblaze] : We will check the possibility of
+ peephole2 optimization,if we can then we will fix the compiler issue.
+
+---
+ gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
+ 1 file changed, 38 insertions(+), 25 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index bb96e2d..830ef77 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -882,31 +882,44 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-(define_peephole2
+-  [(set (match_operand:SI 0 "register_operand")
+-        (fix:SI (match_operand:SF 1 "register_operand")))
+-   (set (pc)
+-        (if_then_else (match_operator 2 "ordered_comparison_operator"
+-                       [(match_operand:SI 3 "register_operand")
+-                        (match_operand:SI 4 "arith_operand")])
+-                      (label_ref (match_operand 5))
+-                      (pc)))]
+-   "TARGET_HARD_FLOAT && !TARGET_MB_64"
+-   [(set (match_dup 1) (match_dup 3))]
+-
+-  {
+-    rtx condition;
+-    rtx cmp_op0 = operands[3];
+-    rtx cmp_op1 = operands[4];
+-    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+-
+-    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
+-    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+-    emit_jump_insn (gen_condjump (condition, operands[5]));
+-  }
+-)
++;; peephole2 optimization will be done only if fint and if-then-else
++;; are dependent.added condition for the same.
++;; if they are dependent then gcc is giving "flow control insn inside a basic block" 
++;; testcase:
++;;        volatile float vec = 1.0;
++;;        volatile int ci = 2;
++;;        register int cj = (int)(vec);
++;;//        ci=cj;
++;;//      if (ci <0) {
++;;        if (cj < 0) {
++;;                ci = 0;
++;;        }
++;; commenting for now.we will check the possibility of this optimization later
++
++;;(define_peephole2
++;;  [(set (match_operand:SI 0 "register_operand")
++;;        (fix:SI (match_operand:SF 1 "register_operand")))
++;;   (set (pc)
++;;        (if_then_else (match_operator 2 "ordered_comparison_operator"
++;;                       [(match_operand:SI 3 "register_operand")
++;;                        (match_operand:SI 4 "arith_operand")])
++;;                      (label_ref (match_operand 5))
++;;                      (pc)))]
++;;   "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
++;;  [(set (match_dup 1) (match_dup 3))]
++;;  {
++;;    rtx condition;
++;;    rtx cmp_op0 = operands[3];
++;;    rtx cmp_op1 = operands[4];
++;;    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++;;
++;;    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
++;;    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
++;;    emit_jump_insn (gen_condjump (condition, operands[5]));
++;;  }
++;;)
+ 
+ ;;----------------------------------------------------------------
+ ;; Negation and one's complement
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
index 8bc47a430..8bc47a430 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
new file mode 100644
index 000000000..69b498984
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
@@ -0,0 +1,51 @@
+From 8e7d7f3d2e103c34bbb28afe1338107b9fd824f0 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 16 Apr 2019 17:20:24 +0530
+Subject: [PATCH 58/63] Reverting the patch as kernel boot is not working with
+ this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
+ before propagating constants."
+
+This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
+---
+ gcc/cprop.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/gcc/cprop.c b/gcc/cprop.c
+index 42bcc81..65c0130 100644
+--- a/gcc/cprop.c
++++ b/gcc/cprop.c
+@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+   int success = 0;
+   rtx set = single_set (insn);
+ 
+-#if 0
+   bool check_rtx_costs = true;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int old_cost = set ? set_rtx_cost (set, speed) : 0;
+@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 	  && (GET_CODE (XEXP (note, 0)) == CONST
+ 	      || CONSTANT_P (XEXP (note, 0)))))
+     check_rtx_costs = false;
+-#endif
+ 
+   /* Usually we substitute easy stuff, so we won't copy everything.
+      We however need to take care to not duplicate non-trivial CONST
+@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 
+   validate_replace_src_group (from, to, insn);
+ 
+-#if 0
+   /* If TO is a constant, check the cost of the set after propagation
+      to the cost of the set before the propagation.  If the cost is
+      higher, then do not replace FROM with TO.  */
+@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+       return false;
+     }
+ 
+-#endif
+ 
+   if (num_changes_pending () && apply_change_group ())
+     success = 1;
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 000000000..2e5703304
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
+From e1a10a708f209704a3921cf66dd3ff4d0814befc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 17 Apr 2019 12:36:16 +0530
+Subject: [PATCH 59/63] [Patch,MicroBlaze]: fixed typos in mul,div and mod
+ assembly files.
+
+---
+ libgcc/config/microblaze/divsi3.S  | 47 ++++++++++++++++++++++++++----
+ libgcc/config/microblaze/modsi3.S  | 40 +++++++++++++++++++++++---
+ libgcc/config/microblaze/mulsi3.S  | 33 +++++++++++++++++++++-
+ libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
+ libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
+ 5 files changed, 212 insertions(+), 20 deletions(-)
+
+diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
+index 2765e42..bd56522 100644
+--- a/libgcc/config/microblaze/divsi3.S
++++ b/libgcc/config/microblaze/divsi3.S
+@@ -46,7 +46,7 @@
+ __divsi3:
+ 	.frame	r1,0,r15	
+ 
+-	ADDIK   r1,r1,-32
++	ADDLIK   r1,r1,-32
+ 	SLI     r28,r1,0
+ 	SLI     r29,r1,8
+ 	SLI     r30,r1,16
+@@ -61,13 +61,23 @@ __divsi3:
+ 	SWI     r30,r1,8
+ 	SWI     r31,r1,12
+ #endif
+-	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+-	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
+-	BGEID   r5,$LaR5_Pos 
++#ifdef __arch64__
++	BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++	BEAGEID   r5,$LaR5_Pos
++#else
++        BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BGEID   r5,$LaR5_Pos
++#endif
+ 	XOR     r28,r5,r6               # Get the sign of the result
+ 	RSUBI   r5,r5,0                 # Make r5 positive
+ $LaR5_Pos:
+-	BGEI    r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI    r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI   r6,r6,0                 # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK   r30,r0,0                # Clear mod
+@@ -76,26 +86,51 @@ $LaR6_Pos:
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0: 
+-        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#else
++        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30             # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30              # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31              # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++#else
+ 	BEQi    r29,$LaLOOP_END
++#endif
+ 	ADD     r3,r3,r3                # Shift in the '1' into div
++#ifdef __arch64__
++        BREAI     $LaDIV2                 # Div2
++#else
+ 	BRI     $LaDIV2                 # Div2
++#endif
+ $LaLOOP_END:
++#ifdef __arch64__
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAID    $LaRETURN_HERE
++#else
+ 	BGEI    r28,$LaRETURN_HERE
+ 	BRID    $LaRETURN_HERE
++#endif
+ 	RSUBI   r3,r3,0                 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index b0e6cad..3632fad 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -62,40 +62,72 @@ __modsi3:
+ 	swi	r31,r1,12
+ #endif
+ 
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BEAGEId   r5,$LaR5_Pos
++#else
+ 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
+ 	BGEId	r5,$LaR5_Pos 
++#endif
+ 	ADD	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
+ 	RSUBI	r5,r5,0	                # Make r5 positive
+ $LaR5_Pos:
+-	BGEI	r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI	r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI	r6,r6,0	    # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK	r3,r0,0      # Clear mod
+ 	ADDIK	r30,r0,0     # clear div
+-	BLTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++#ifdef __arch64__
++	BEALTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
+ 			     # the first bit search.
++#else
++        BLTId   r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++                             # the first bit search.
++#endif
+ 	ADDIK	r29,r0,32    # Initialize the loop count
+    # First part try to find the first '1' in the r5
+ $LaDIV1:
+ 	ADD	r5,r5,r5         # left shift logical r5
+-	BGEID	r5,$LaDIV1       #
++#ifdef __arch64__
++	BEAGEID	r5,$LaDIV1       #
++#else
++        BGEID   r5,$LaDIV1       #
++#endif
+ 	ADDIK	r29,r29,-1
+ $LaDIV2:
+ 	ADD	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
+ 	ADDC	r3,r3,r3         # Move that bit into the Mod register
+ 	rSUB	r31,r6,r3        # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTi    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTi	r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR	r3,r0,r31       # Move the r31 to mod since the result was positive
+ 	ADDIK	r30,r30,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK	r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30         # Shift in the '1' into div
++        BREAI     $LaDIV2          # Div2
++$LaLOOP_END:
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAId    $LaRETURN_HERE
++#else
+ 	BEQi	r29,$LaLOOP_END
+ 	ADD	r30,r30,r30         # Shift in the '1' into div
+ 	BRI	$LaDIV2          # Div2
+ $LaLOOP_END:
+ 	BGEI	r28,$LaRETURN_HERE
+ 	BRId	$LaRETURN_HERE
++#endif
+ 	rsubi	r3,r3,0 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+@@ -108,7 +140,7 @@ $LaRETURN_HERE:
+ 	lli	r29,r1,8
+ 	lli	r30,r1,16
+ 	lli	r31,r1,24
+-	addik	r1,r1,32
++	addlik	r1,r1,32
+ 	rtsd	r15,8
+ 	nop
+ #else
+diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
+index e28c69a..991dbcd 100644
+--- a/libgcc/config/microblaze/mulsi3.S
++++ b/libgcc/config/microblaze/mulsi3.S
+@@ -43,7 +43,37 @@
+ 	.type	__mulsi3,@function
+ #ifdef __arch64__
+         .align 3
+-#endif
++__mulsi3:
++        .frame  r1,0,r15
++        add     r3,r0,r0
++        BEAEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
++        BEAEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
++        BEAGEId   r5,$L_R5_Pos
++        XOR     r4,r5,r6                  # Get the sign of the result
++        RSUBI   r5,r5,0                   # Make r5 positive
++$L_R5_Pos:
++        BEAGEI    r6,$L_R6_Pos
++        RSUBI   r6,r6,0                   # Make r6 positive
++$L_R6_Pos:
++        breai     $L1
++$L2:
++        add     r5,r5,r5
++$L1:
++        srl     r6,r6
++        addc    r7,r0,r0
++        beaeqi    r7,$L2
++        beaneid   r6,$L2
++        add     r3,r3,r5
++        bealti    r4,$L_NegateResult
++        rtsd    r15,8
++        nop
++$L_NegateResult:
++        rtsd    r15,8
++        rsub    r3,r3,r0
++$L_Result_Is_Zero:
++        rtsd    r15,8
++        addi    r3,r0,0
++#else
+ __mulsi3:
+ 	.frame	r1,0,r15
+ 	add	r3,r0,r0
+@@ -74,5 +104,6 @@ $L_NegateResult:
+ $L_Result_Is_Zero:
+ 	rtsd	r15,8
+ 	addi	r3,r0,0
++#endif
+ 	.end __mulsi3
+ 	.size	__mulsi3, . - __mulsi3
+diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
+index b1e44b6..42b086e 100644
+--- a/libgcc/config/microblaze/udivsi3.S
++++ b/libgcc/config/microblaze/udivsi3.S
+@@ -59,52 +59,96 @@ __udivsi3:
+ 	SWI     r30,r1,4
+ 	SWI     r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
++        BEAEQID   r5,$LaResult_Is_Zero        # Result is Zero
++#else
+ 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
+ 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
++#endif
+ 	ADDIK   r30,r0,0                    # Clear mod
+ 	ADDIK   r29,r0,32                   # Initialize the loop count
+ 
+         # Check if r6 and r5 are equal # if yes, return 1
+ 	RSUB 	r18,r5,r6
++#ifdef __arch64__
++        BEAEQID   r18,$LaRETURN_HERE
++#else
+ 	BEQID	r18,$LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
+ 	XOR	r18,r5,r6
+-	BGEID	r18,16
++#ifdef __arch64__
++	BEAGEID	r18,16
++#else
++        BGEID   r18,16
++#endif
+ 	ADD	r3,r0,r0                    # We would anyways clear r3
++#ifdef __arch64__
++        BEALTI    r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
++        BREAI     $LCheckr6
++        RSUB    r18,r6,r5                   # MICROBLAZEcmp
++        BEALTI    r18,$LaRETURN_HERE
++#else
+ 	BLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
+ 	BRI	$LCheckr6
+ 	RSUB	r18,r6,r5                   # MICROBLAZEcmp
+ 	BLTI	r18,$LaRETURN_HERE
+-
++#endif
+         # If r6 [bit 31] is set, then return result as 1
+ $LCheckr6:
+-	BGTI	r6,$LaDIV0
+-	BRID	$LaRETURN_HERE
++#ifdef __arch64__
++	BEAGTI	r6,$LaDIV0
++	BREAID	$LaRETURN_HERE
++#else
++        BGTI    r6,$LaDIV0
++        BRID    $LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0:
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2
++#else
+ 	BLTI    r5,$LaDIV2	
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                    # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30                 # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30                  # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+     	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31                  # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r3,r3,r3 # Shift in the '1' into div
++        BREAI     $LaDIV2   # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++#else
+ 	BEQi    r29,$LaLOOP_END
+ 	ADD     r3,r3,r3 # Shift in the '1' into div
+ 	BRI     $LaDIV2   # Div2
+ $LaLOOP_END:
+ 	BRI     $LaRETURN_HERE
++#endif
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
+@@ -115,7 +159,7 @@ $LaRETURN_HERE:
+ 	LLI     r29,r1,0
+ 	LLI     r30,r1,8
+ 	LLI     r31,r1,16
+-	ADDIK   r1,r1,24
++	ADDLIK   r1,r1,24
+ 	RTSD    r15,8
+ 	NOP
+ #else
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 1b3070e..91430a6 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -46,7 +46,7 @@
+ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+-	addik	r1,r1,-24
++	addlik	r1,r1,-24
+ 	sli	r29,r1,0
+ 	sli	r30,r1,8
+ 	sli	r31,r1,16
+@@ -59,27 +59,77 @@ __umodsi3:
+ 	swi	r30,r1,4
+ 	swi	r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
++        BEAEQId   r5,$LaResult_Is_Zero     # Result is Zero
++#else
+ 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
+ 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
++#endif
+ 	ADDIK 	r3,r0,0                  # Clear div
+ 	ADDIK 	r30,r0,0     	# clear mod
+ 	ADDIK 	r29,r0,32       # Initialize the loop count
+ 
+ # Check if r6 and r5 are equal # if yes, return 0
+ 	rsub 	r18,r5,r6
+-	beqi	r18,$LaRETURN_HERE
+ 
++#ifdef __arch64__
++	beaeqi    r18,$LaRETURN_HERE
++#else
++	beqi	r18,$LaRETURN_HERE
++#endif
+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
+ 	xor	r18,r5,r6
++#ifdef __arch64__
++        beageid   r18,16
++        addik   r3,r5,0
++        bealti    r6,$LaRETURN_HERE
++        breai     $LCheckr6
++        rsub    r18,r5,r6 # MICROBLAZEcmp
++        beagti    r18,$LaRETURN_HERE
++#else
+ 	bgeid	r18,16
+ 	addik	r3,r5,0
+ 	blti	r6,$LaRETURN_HERE
+ 	bri	$LCheckr6
+ 	rsub	r18,r5,r6 # MICROBLAZEcmp
+ 	bgti	r18,$LaRETURN_HERE
+-
++#endif
+ # If r6 [bit 31] is set, then return result as r5-r6
+ $LCheckr6:
++#ifdef __arch64__
++        beagtid   r6,$LaDIV0
++        addik   r3,r0,0
++        addik   r18,r0,0x7fffffff
++        and     r5,r5,r18
++        and     r6,r6,r18
++        breaid    $LaRETURN_HERE
++        rsub    r3,r6,r5
++# First part: try to find the first '1' in the r5
++$LaDIV0:
++        BEALTI    r5,$LaDIV2
++$LaDIV1:
++        ADD     r5,r5,r5     # left shift logical r5
++        BEAGEID   r5,$LaDIV1   #
++        ADDIK   r29,r29,-1
++$LaDIV2:
++        ADD     r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
++        ADDC    r3,r3,r3     # Move that bit into the Mod register
++        rSUB    r31,r6,r3    # Try to subtract (r3 a r6)
++        BEALTi    r31,$LaMOD_TOO_SMALL
++        OR      r3,r0,r31    # Move the r31 to mod since the result was positive
++        ADDIK   r30,r30,1
++$LaMOD_TOO_SMALL:
++        ADDIK   r29,r29,-1
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30 # Shift in the '1' into div
++        BREAI     $LaDIV2     # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++        or      r3,r0,r0   # set result to 0
++#else
+ 	bgtid	r6,$LaDIV0
+ 	addik	r3,r0,0
+ 	addik	r18,r0,0x7fffffff
+@@ -111,7 +161,7 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or 	r3,r0,r0   # set result to 0
+-
++#endif
+ #ifdef __arch64__
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
index be4dfad5c..be4dfad5c 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 000000000..9f8786694
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
+From f0332f119c3cbe95886dae77c4b5a9b9907b4b17 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 18 Apr 2019 16:00:37 +0530
+Subject: [PATCH 60/63] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
+ 17 14:11:00 2019 +0530
+
+    [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
+    By default MB-64 is generatting barrel-shift instructions. It has been
+    removed from default. Barrel-shift instructions will be generated only if
+    barrel-shifter is enabled. Similarly to double instructions as well.
+
+    Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c  |   2 +-
+ gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
+ 2 files changed, 252 insertions(+), 19 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 220e03d..5c09452 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -4008,7 +4008,7 @@ microblaze_expand_divide (rtx operands[])
+   emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
+ 
+   if (TARGET_MB_64) {
+-      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
+       emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
+     }
+   else  {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 830ef77..3e7c647 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -547,7 +547,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (plus:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dadd\t%0,%1,%2"
+   [(set_attr "type"     "fadd")
+   (set_attr "mode"      "DF")
+@@ -557,7 +557,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (minus:DF (match_operand:DF 1 "register_operand" "d")
+                   (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "drsub\t%0,%2,%1"
+   [(set_attr "type"     "frsub")
+   (set_attr "mode"      "DF")
+@@ -567,7 +567,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (mult:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dmul\t%0,%1,%2"
+   [(set_attr "type"     "fmul")
+   (set_attr "mode"      "DF")
+@@ -577,7 +577,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (div:DF (match_operand:DF 1 "register_operand" "d")
+                 (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "ddiv\t%0,%2,%1"
+   [(set_attr "type"     "fdiv")
+   (set_attr "mode"      "DF")
+@@ -587,7 +587,7 @@
+ (define_insn "sqrtdf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dsqrt\t%0,%1"
+   [(set_attr "type"     "fsqrt")
+   (set_attr "mode"      "DF")
+@@ -596,7 +596,7 @@
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (float:DF (match_operand:DI 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dbl\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DF")
+@@ -605,7 +605,7 @@
+ (define_insn "fix_truncdfdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+         (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dlong\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DI")
+@@ -1301,6 +1301,34 @@
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "*movdi_internal2_bshift"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
++	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++        return "addlk\t%0,%1,r0";
++     case 1:
++     case 2:
++        if (GET_CODE (operands[1]) == CONST_INT &&
++	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
++	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++        else
++	  return "addlik\t%0,r0,%1";
++     case 3:
++     case 4:
++       return "ll%i1\t%0,%1";
++     case 5:
++     case 6:
++       return "sl%i0\t%z1,%0";
++     }
++   }
++  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,4,12,4,8,4,8")])
++
+ (define_insn "*movdi_internal2"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
+ 	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
+@@ -1314,7 +1342,15 @@
+      case 2:
+         if (GET_CODE (operands[1]) == CONST_INT && 
+ 	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
+- 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++          {
++            operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++            output_asm_insn ("addlik\t%0,r0,%h1", operands);
++            output_asm_insn ("addlik\t%2,r0,32", operands);
++            output_asm_insn ("addlik\t%2,%2,-1", operands);
++            output_asm_insn ("beaneid\t%2,.-8", operands);
++            output_asm_insn ("addlk\t%0,%0,%0", operands);
++            return "addlik\t%0,%0,%j1 #li => la";
++          }
+         else	
+ 	  return "addlik\t%0,r0,%1";
+      case 3:
+@@ -1388,7 +1424,7 @@
+ (define_insn "movdi_long_int"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ 	(match_operand:DI 1 "general_operand"      "i"))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+   [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+@@ -1655,6 +1691,33 @@
+ ;; movdf_internal
+ ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
+ ;;
++(define_insn "*movdf_internal_64_bshift"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
++        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++	return "addlk\t%0,%1,r0";
++      case 1:
++	return "addlk\t%0,r0,r0";
++      case 2:
++      case 4:
++          return "ll%i1\t%0,%1";
++      case 3:
++      {
++	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++      }
++      case 5:
++	return "sl%i0\t%1,%0";
++    }
++    gcc_unreachable ();
++  }
++  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4,4,4,16,4,4")])
++
+ (define_insn "*movdf_internal_64"
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
+         (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
+@@ -1671,7 +1734,13 @@
+           return "ll%i1\t%0,%1";
+       case 3:
+       {
+-	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++	operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++	output_asm_insn ("addlik\t%0,r0,%h1", operands);
++	output_asm_insn ("addlik\t%2,r0,32", operands);
++	output_asm_insn ("addlik\t%2,%2,-1", operands);
++	output_asm_insn ("beaneid\t%2,.-8", operands);
++	output_asm_insn ("addlk\t%0,%0,%0", operands);
++	return "addlik\t%0,%0,%j1 #li => la";
+       }
+       case 5:
+ 	return "sl%i0\t%1,%0";
+@@ -1791,11 +1860,21 @@
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1805,7 +1884,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+   bsllli\t%0,%1,%2
+   bslll\t%0,%1,%2"
+@@ -1813,6 +1892,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+ )
++
++(define_insn "ashldi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++   (set_attr "mode"    "DI")
++   (set_attr "length"  "20")]
++)
++
++(define_insn "ashldi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ ;; The following patterns apply when there is no barrel shifter present
+ 
+ (define_insn "*ashlsi3_with_mul_delay"
+@@ -1946,11 +2070,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1960,7 +2094,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrai\t%0,%1,%2
+    bslra\t%0,%1,%2"
+@@ -1968,6 +2102,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+   )
++
++(define_insn "ashrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "arith")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "ashrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "ashrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2085,11 +2264,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -2099,7 +2288,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrli\t%0,%1,%2
+    bslrl\t%0,%1,%2"
+@@ -2108,6 +2297,50 @@ else
+   (set_attr "length"	"4,4")]
+   )
+ 
++(define_insn "lshrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "lshrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "SI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "lshrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2235,7 +2468,7 @@ else
+ 	(eq:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmpleq\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"DI")
+@@ -2247,7 +2480,7 @@ else
+ 	(ne:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmplne\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
index 1548faada..1548faada 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch
index 690bc7273..690bc7273 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
new file mode 100644
index 000000000..d3ed669c9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -0,0 +1,41 @@
+From 11766e4f7aaad3f217944079335c71525b72201c Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 8 May 2019 14:12:03 +0530
+Subject: [PATCH 61/63] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
+ disable fivopts by default
+
+Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
+
+ * gcc/common/config/microblaze/microblaze-common.c
+   (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+---
+ gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index 9b6ef21..3cae2a6 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -27,13 +27,15 @@
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
+ static const struct default_options microblaze_option_optimization_table[] =
+   {
+-    /* Turn off ivopts by default. It messes up cse. */
++    /* Turn off ivopts by default. It messes up cse. 
++    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
+     { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
+-    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+     { OPT_LEVELS_NONE, 0, NULL, 0 }
+   };
+ 
+ #undef TARGET_DEFAULT_TARGET_FLAGS
+ #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
+ 
++#undef TARGET_OPTION_OPTIMIZATION_TABLE
++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
+ struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
new file mode 100644
index 000000000..ca1a2b9fc
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -0,0 +1,107 @@
+From bb65903ab6293a47d154764a585f6c53b5fcf853 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:16:53 +0530
+Subject: [PATCH 62/63] Added new MB-64 single register arithmetic instructions
+
+---
+ gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 3e7c647..4d40cc5 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -654,6 +654,18 @@
+    }
+ })
+ 
++(define_insn "adddi3_int"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++  (plus:DI (match_operand:DI 1 "register_operand" "%0")
++                 (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++  addlik\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")]
++)
++
+ (define_insn "*adddi3_long"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+@@ -719,6 +731,18 @@
+ {
+ }")
+ 
++(define_insn "subdi316imm"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (minus:DI (match_operand:DI 1 "register_operand" "d")
++                  (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
++  "@
++   addlik\t%0,-%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
++
+ (define_insn "subsidi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
+@@ -1015,6 +1039,17 @@
+ ;; Logical
+ ;;----------------------------------------------------------------
+ 
++(define_insn "anddi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (and:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   andli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
+ (define_insn "anddi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
+@@ -1042,6 +1077,16 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "iordi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (ior:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   orli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
+ 
+ (define_insn "iordi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+@@ -1069,6 +1114,17 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "xordi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (xor:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   xorli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
+ (define_insn "xordi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
index e7dfa89c1..e7dfa89c1 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
new file mode 100644
index 000000000..edf6a0f34
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
@@ -0,0 +1,44 @@
+From d4b23a1dd0564bcf67b5b88a68d62eb49bdab15d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:55:22 +0530
+Subject: [PATCH 63/63] [Patch,MicroBlaze] : Added support for 64 bit Immediate
+ values.
+
+---
+ gcc/config/microblaze/constraints.md | 4 ++--
+ gcc/config/microblaze/microblaze.md  | 3 +--
+ 2 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 9a5aa6b..e87a90f 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -53,9 +53,9 @@
+        (match_test "ival > 0 && ival < 0x10000")))
+ 
+ (define_constraint "K"
+-  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
++  "A constant in the range  -9223372036854775808 to 9223372036854775807 (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
++       (match_test "ival > (long long)-9223372036854775808  && ival < (long long)9223372036854775807")))
+ 
+ ;; Define floating point constraints
+ 
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 4d40cc5..6e74503 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1334,8 +1334,7 @@
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
+ 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
+   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
+-           (GET_CODE (operands[1]) == CONST_INT && 
+-                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
++           (GET_CODE (operands[1]) == CONST_INT))"
+   "@
+    addlk\t%0,r0,r0\t
+    addlik\t%0,r0,%1\t #N1 %X1
+-- 
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
new file mode 100644
index 000000000..41c90353b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
@@ -0,0 +1,77 @@
+From 5f54efe1e7d9604b45ddddd510ce439477d0e94f Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 9 Jan 2020 12:30:41 +0530
+Subject: [PATCH] [Patch, microblaze]: Fix Compiler crash with
+ -freg-struct-return This patch fixes a bug in MB GCC regarding the passing
+ struct values in registers. Currently we are only handling SImode With this
+ patch all other modes are handled properly
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+---
+ gcc/config/microblaze/microblaze.c | 11 ++++++++++-
+ gcc/config/microblaze/microblaze.h | 19 -------------------
+ 2 files changed, 10 insertions(+), 20 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 5c09452..beccd12 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -4046,7 +4046,16 @@ microblaze_function_value (const_tree valtype,
+ 			   const_tree func ATTRIBUTE_UNUSED,
+ 			   bool outgoing ATTRIBUTE_UNUSED)
+ {
+-  return LIBCALL_VALUE (TYPE_MODE (valtype));
++  return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN);
++}
++
++#undef  TARGET_LIBCALL_VALUE
++#define TARGET_LIBCALL_VALUE microblaze_libcall_value
++
++rtx
++microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
++{
++  return gen_rtx_REG (mode, GP_RETURN);
+ }
+ 
+ /* Implement TARGET_SCHED_ADJUST_COST.  */
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index ab541f7..100e7b2 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
+ 
+ #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
+ 
+-#ifndef __arch64__
+-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
+-  if (GET_MODE_CLASS (MODE) == MODE_INT         \
+-      && GET_MODE_SIZE (MODE) < 4)              \
+-    (MODE) = SImode;
+-#endif
+-
+ /* Standard register usage.  */
+ 
+ /* On the MicroBlaze, we have 32 integer registers */
+@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info;
+ 
+ #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
+ 
+-#ifdef __aarch64__
+-#define LIBCALL_VALUE(MODE)						\
+-  gen_rtx_REG (MODE,GP_RETURN)
+-#else								
+-#define LIBCALL_VALUE(MODE)						\
+-  gen_rtx_REG (								\
+-	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+-	     || GET_MODE_SIZE (MODE) >= 4)				\
+-	    ? (MODE)							\
+-	    : SImode), GP_RETURN)
+-#endif
+-
+ /* 1 if N is a possible register number for a function value.
+    On the MicroBlaze, R2 R3 are the only register thus used.
+    Currently, R2 are only implemented  here (C has no complex type)  */
+-- 
+1.8.3.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_10.%.bbappend
index d6a819126..f05a400f9 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_10.%.bbappend
@@ -1,7 +1,7 @@
 # Add MicroBlaze Patches (only when using MicroBlaze)
-FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-8:"
+FILESEXTRAPATHS_append_microblaze := ":${THISDIR}/gcc-9"
 SRC_URI_append_microblaze = " \
-file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
+        file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
         file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \
         file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \
         file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
@@ -56,10 +56,13 @@ file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
         file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
         file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
         file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-        file://0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
-        file://0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
-        file://0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \
-        file://0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
-        file://0061-Author-Nagaraju-nmekala-xilinx.com.patch \
-        file://0055-microblaze_linker_script_xilinx_ld.patch \
+        file://0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
+        file://0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
+        file://0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \
+        file://0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
+        file://0060-Author-Nagaraju-nmekala-xilinx.com.patch \
+        file://0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
+        file://0062-Added-new-MB-64-single-register-arithmetic-instructi.patch \
+        file://0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
+        file://0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
 "