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Diffstat (limited to 'meta-xilinx/meta-xilinx-bsp')
213 files changed, 0 insertions, 23928 deletions
diff --git a/meta-xilinx/meta-xilinx-bsp/COPYING.MIT b/meta-xilinx/meta-xilinx-bsp/COPYING.MIT deleted file mode 100644 index 89de35479..000000000 --- a/meta-xilinx/meta-xilinx-bsp/COPYING.MIT +++ /dev/null @@ -1,17 +0,0 @@ -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. diff --git a/meta-xilinx/meta-xilinx-bsp/README.booting.md b/meta-xilinx/meta-xilinx-bsp/README.booting.md deleted file mode 100644 index dc48f6b22..000000000 --- a/meta-xilinx/meta-xilinx-bsp/README.booting.md +++ /dev/null @@ -1,266 +0,0 @@ -Booting meta-xilinx boards -========================== - -Contents --------- - -* [Loading via JTAG](#loading-via-jtag) - * [XSDB](#xsdb) - * [Load Bitstream](#load-bitstream) - * [Load U-Boot (MicroBlaze)](#load-u-boot-microblaze) - * [Load U-Boot (Zynq)](#load-u-boot-zynq) - * [U-Boot Console](#u-boot-console) - * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree) - * [Booting via U-Boot](#booting-via-u-boot) -* [Loading via SD](#loading-via-sd) - * [Preparing SD/MMC](#preparing-sdmmc) - * [Installing U-Boot](#installing-u-boot) - * [Installing Kernel and Device Tree](#installing-kernel-and-device-tree) - * [Installing Root Filesystem](#installing-root-filesystem) - * [U-Boot Configuration File](#u-boot-configuration-file) - * [Booting](#booting) -* [Loading via TFTP](#loading-via-tftp) - * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree-1) - * [Booting via U-Boot](#booting-via-u-boot-1) - - -Loading via JTAG ----------------- -This boot flow requires the use of the Xilinx tools, specifically XSDB and the -associated JTAG device drivers. This also requires access to the JTAG interface -on the board, a number of Xilinx and third-party boards come with on-board JTAG -modules. - -### XSDB -Start `xsdb` and connect. Ensure that the target chip is visible. - - $ xsdb - xsdb% connect - xsdb% targets - -### Load Bitstream -**(Note: This step is only required for platforms which have a bitstream e.g. -MicroBlaze.)** - -Download the bitstream for the system using XSDB with the `fpga -f` command. If -a bitstream is available from meta-xilinx is will be located in the -`deploy/images/<machine-name>/` directory. - - xsdb% fpga -f download.bit - -### Load U-Boot (MicroBlaze) -Download `u-boot.elf` to the target CPU via the use of XSDB. - - xsdb% targets -set -filter {name =~ "MicroBlaze*"} - xsdb% rst - xsdb% dow u-boot.elf - xsdb% con - -### Load U-Boot (Zynq) -Ensure the board is configured to boot from JTAG. The Zynq platform requires the -loading of SPL first, this can be done by loading the `u-boot-spl.bin` and -executing it at location `0x0`. `u-boot-spl.bin` is not output to the deploy -directory by default, it can be obtained from the work directory for U-Boot -(`git/spl/u-boot-spl.bin`) or can be extracted from `boot.bin` using -`dd if=boot.bin of=u-boot-spl.bin bs=1 skip=2240`. - - xsdb% targets -set -filter {name =~ "ARM*#0"} - xsdb% dow -data u-boot-spl.bin 0x0 - xsdb% rwr pc 0x0 - xsdb% con - -On the UART console the following should appear, indicating SPL was loaded. - - U-Boot SPL 2016.01 - Trying to boot from unknown boot device - SPL: Unsupported Boot Device! - SPL: failed to boot from all boot devices - ### ERROR ### Please RESET the board ### - -Once SPL has loaded U-Boot can now be loaded into memory and executed. Download -`u-boot.elf` to the target. - - xsdb% stop - xsdb% dow u-boot.elf - xsdb% con - -### U-Boot Console -U-Boot will load and the console will be available on the UART interface. - - ... - Hit any key to stop autoboot: 0 - U-Boot> - -### Kernel, Root Filesystem and Device Tree -Whilst it is possible to load the images via JTAG this connection is slow and -this process can take a long time to execute (more than 10 minutes). If your -system has ethernet it is recommended that you use TFTP to load these images -using U-Boot. - -Once U-Boot has been loaded, pause the execution using XSDB and use the `dow` -command to load the images into the targets memory. Once the images are loaded -continue the execution and return to the U-Boot console. - -MicroBlaze (kc705-microblazeel): - - xsdb% stop - xsdb% dow -data linux.bin.ub 0x85000000 - xsdb% dow -data core-image-minimal-kc705-microblazeel.cpio.gz.u-boot 0x86000000 - xsdb% dow -data kc705-microblazeel.dtb 0x84000000 - xsdb% con - -Zynq: - - xsdb% stop - xsdb% dow -data uImage 0x2000000 - xsdb% dow -data core-image-minimal-<machine name>.cpio.gz.u-boot 0x3000000 - xsdb% dow -data <machine name>.dtb 0x2A00000 - xsdb% con - -### Booting via U-Boot -At the U-Boot console use the `bootm` command to execute the kernel. - -MicroBlaze (kc705-microblazeel): - - U-Boot> bootm 0x85000000 0x86000000 0x84000000 - -Zynq: - - U-Boot> bootm 0x2000000 0x3000000 0x2A00000 - - -Loading via SD ---------------------- -**(Note: This section only applies to Zynq and ZynqMP.)** - -### Preparing SD/MMC -Setup the card with the first partition formatted as FAT16. If you intend to -boot with the root filesystem located on the SD card, also create a second -partition formatted as EXT4. - -It is recommended that the first partition be at least 64MB in size, however -this value will depend on whether using a ramdisk for the root filesystem and -how large the ramdisk is. - -This section describes how to manually prepare and populate an SD card image. -There are automation tools in OpenEmbedded that can generate disk images already -formatted and prepared such that they can be written directly to a disk. Refer -to the Yocto Project Development Manual for more details: - http://www.yoctoproject.org/docs/current/dev-manual/dev-manual.html#creating-partitioned-images - -### Installing U-Boot (Zynq) -Add the following files to the first partition: - -* `boot.bin` -* `u-boot.img` - -### Installing U-Boot (ZynqMP) -Add the following files to the first partition: - -* `boot.bin` -* `u-boot.bin` - -### Installing Kernel and Device Tree (Zynq) -Add the following files to the first partition: - -* `uImage` -* `<machine name>.dtb` - -### Installing Kernel and Device Tree (ZynqMP) -Add the following files to the first partition: - -* `Image` -* `<machine name>.dtb` - -### Install ARM Trusted Firmware (ZynqMP) -Add the following file to the first partition: - - * `atf-uboot.ub` - -### Install U-boot environment file (ZynqMP) -Add the following file to the first partition: - - * `uEnv.txt` - -### Installing Root Filesystem -If using a ramdisk also add the `.cpio.gz.u-boot` type of root filesystem image -to the first partition. - -* `core-image-minimal-<machine name>.cpio.gz.u-boot` - -If using the SD card as the root filesystem, populate the second partition with -the content of the root filesystem. To install the root filesystem extract the -corresponding tarball into the root of the second partition (the following -command assumes that the second partition is mounted at /media/root). - - tar x -C /media/root -f core-image-minimal-<machine name>.tar.gz - -### U-Boot Configuration File -Also create the file `uEnv.txt` on the first partition of the SD card partition, -with the following contents. Replacing the names of files where appropriate. - - kernel_image=uImage - devicetree_image=<machine name>.dtb - -If using a ramdisk root filesystem setup the `ramdisk_image` variable. - - ramdisk_image=core-image-minimal-<machine name>.cpio.gz.u-boot - -If using the SD card as the root filesystem setup the kernel boot args, and -`uenvcmd` variable. - - bootargs=root=/dev/mmcblk0p2 rw rootwait - uenvcmd=fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && bootm 0x3000000 - 0x2A00000 - -### Booting -Insert the SD card and connect UART to a terminal program and power on the -board. (For boards that have configurable boot jumper/switches ensure the board -is configured for SD). - -Initially U-Boot SPL will load, which will in turn load U-Boot. U-Boot will use -the `uEnv.txt` to automatically load and execute the kernel. - - -Loading via TFTP ----------------- -**(Note: This boot flow requires ethernet on the baord and a TFTP server)** - -Boot your system into U-Boot, using one of boot methods (e.g. JTAG, SD, QSPI). - -### Kernel, Root Filesystem and Device Tree -Place the following images into the root of the TFTP server directory: - -* `core-image-minimal-<machine name>.cpio.gz.u-boot` -* `uImage` (Zynq) or `linux.bin.ub` (MicroBlaze) -* `<machine name>.dtb` - -### Booting via U-Boot -The serial console of the target board will display the U-Boot console. -Configure the `ipaddr` and `serverip` of the U-Boot environment. - - U-Boot> set serverip <server ip> - U-Boot> set ipaddr <board ip> - -Using the U-Boot console; load the Kernel, root filesystem and the DTB into -memory. And then boot Linux using the `bootm` command. (Note the load addresses -will be dependant on machine used) - -MicroBlaze (kc705-microblazeel): - - U-Boot> tftpboot 0x85000000 linux.bin.ub - U-Boot> tftpboot 0x86000000 core-image-minimal-kc705-microblazeel.cpio.gz.u-boot - U-Boot> tftpboot 0x84000000 kc705-microblazeel.dtb - U-Boot> bootm 0x85000000 0x86000000 0x84000000 - -Zynq: - - U-Boot> tftpboot 0x2000000 uImage - U-Boot> tftpboot 0x3000000 core-image-minimal-<machine name>.cpio.gz.u-boot - U-Boot> tftpboot 0x2A00000 <machine name>.dtb - U-Boot> bootm 0x2000000 0x3000000 0x2A00000 - -U-Boot will prepare the Kernel for boot and then it will being to execute. - - ... - Starting kernel... - diff --git a/meta-xilinx/meta-xilinx-bsp/README.building.md b/meta-xilinx/meta-xilinx-bsp/README.building.md deleted file mode 100644 index 230037c17..000000000 --- a/meta-xilinx/meta-xilinx-bsp/README.building.md +++ /dev/null @@ -1,100 +0,0 @@ -Build Instructions -================== - -The following instructions require OE-Core meta and BitBake. Poky provides these -components, however they can be acquired separately. - -Initialize a build using the `oe-init-build-env` script. Once initialized -configure `bblayers.conf` by adding the `meta-xilinx-bsp` and -`meta-xilinx-contrib` layer. e.g.: - - BBLAYERS ?= " \ - <path to layer>/oe-core/meta \ - <path to layer>/meta-xilinx-bsp \ - <path to layer>/meta-xilinx-standalone \ - <path to layer>/meta-xilinx-contrib \ - " - -meta-xilinx-standalone layer provides recipes which enable building baremetal -toolchain for PMU firmware. This layer is required for ZU+ devices which -depends on PMU firmware - -meta-xilinx-contrib is a contribution layer and is optional. - -To build a specific target BSP configure the associated machine in `local.conf`: - - MACHINE ?= "zc702-zynq7" - -Build the target file system image using `bitbake`: - - $ bitbake core-image-minimal - -Once complete the images for the target machine will be available in the output -directory `tmp/deploy/images/<machine name>/`. - -Using SPL flow to build ZU+ ------------------------------- - -The pmufw needs a "configuration object" to know what it should do, and it -expects to receive it at runtime. - -With the U-Boot SPL workflow there's no FSBL, and passing a cfg obj to pmufw is -just not implemented in U-Boot - -To work around this problem a small patch has been developed so that -pm_cfg_obj.c is linked into pmufw and loaded directly, without waiting for it -from the outside. Find the original patch on the meta-topic layer [1] and the -patch updated for pmufw 2018.x here [2]. - -[1] -https://github.com/topic-embedded-products/meta-topic/blob/master/recipes-bsp/pmu-firmware/pmu-firmware_2017.%25.bbappend - -[2] -https://github.com/lucaceresoli/zynqmp-pmufw-builder/blob/master/0001-Load-XPm_ConfigObject-at-boot.patch - - -Using multiconfig to build ZU+ ------------------------------- - -In your local.conf multiconfig should be enabled by: - -`BBMULTICONFIG ?= "pmu"` - -Add a directory conf/multiconfig in the build directory and create pmu.conf inside it. - -Add the following in pmu.conf: - - MACHINE="zynqmp-pmu" - DISTRO="xilinx-standalone" - TMPDIR="${TOPDIR}/pmutmp" - -Add the following in your local.conf - - MACHINE="zcu102-zynqmp" - DISTRO="poky" - -A multiconfig dependency has to be added in the image recipe or local.conf. - -For example in core-image-minimal you would need: - - do_image[mcdepends] = "multiconfig::pmu:pmu-firmware:do_deploy" - -This creates a multiconfig dependency between the task do_image from the default multiconfig '' (which has no name) -to the task do_deploy() from the package pmu-firmware from the pmu multiconfig which was just created above. - - $ bitbake core-image-minimal - -This will build both core-image-minimal and pmu-firmware. - - -More information about multiconfig: -https://www.yoctoproject.org/docs/current/mega-manual/mega-manual.html#dev-building-images-for-multiple-targets-using-multiple-configurations - - -Additional Information ----------------------- - -For more complete details on setting up and using Yocto/OE refer to the Yocto -Project Quick Start guide available at: - http://www.yoctoproject.org/docs/current/yocto-project-qs/yocto-project-qs.html - diff --git a/meta-xilinx/meta-xilinx-bsp/README.md b/meta-xilinx/meta-xilinx-bsp/README.md deleted file mode 100644 index e41428619..000000000 --- a/meta-xilinx/meta-xilinx-bsp/README.md +++ /dev/null @@ -1,88 +0,0 @@ -meta-xilinx -=========== - -This layer provides support for MicroBlaze, Zynq and ZynqMP. - -Additional documentation: - -* [Building](README.building.md) -* [Booting](README.booting.md) - -Supported Boards/Machines -========================= - -Boards/Machines supported by this layer: - -* MicroBlaze: - * [Xilinx ML605 (QEMU)](conf/machine/ml605-qemu-microblazeel.conf) - `ml605-qemu-microblazeel` (QEMU support) - * [Xilinx S3A DSP 1800 (QEMU)](conf/machine/s3adsp1800-qemu-microblazeeb.conf) - `s3adsp1800-qemu-microblazeeb` (QEMU support) - * [Xilinx KC705](conf/machine/kc705-microblazeel.conf) - `kc705-microblazeel` -* Zynq: - * [Zynq (QEMU)](conf/machine/qemu-zynq7.conf) - `qemu-zynq7` (QEMU Support) - * [Xilinx ZC702](conf/machine/zc702-zynq7.conf) - `zc702-zynq7` (with QEMU support) - * [Xilinx ZC706](conf/machine/zc706-zynq7.conf) - `zc706-zynq7` (with QEMU support) - * [Avnet MicroZed](conf/machine/microzed-zynq7.conf) - `microzed-zynq7` - * [Avnet PicoZed](conf/machine/picozed-zynq7.conf) - `picozed-zynq7` - * [Avnet/Digilent ZedBoard](conf/machine/zedboard-zynq7.conf) - `zedboard-zynq7` - * [Digilent Zybo](conf/machine/zybo-zynq7.conf) - `zybo-zynq7` - * [Digilent Zybo Linux BD](conf/machine/zybo-linux-bd-zynq7.conf) - `zybo-linux-bd-zynq7` -* ZynqMP: - * [Xilinx ZCU102](conf/machine/zcu102-zynqmp.conf) - `zcu102-zynqmp` (QEMU support) - * [Xilinx ZCU106](conf/machine/zcu106-zynqmp.conf) - `zcu106-zynqmp` - * [Xilinx ZCU104](conf/machine/zcu104-zynqmp.conf) - `zcu104-zynqmp` - -Additional information on Xilinx architectures can be found at: - http://www.xilinx.com/support/index.htm - -For Zybo Linux BD reference design, please see meta-xilinx-contrib layer - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> - Mark Hatle <mark.hatle@xilinx.com> - -Dependencies -============ - -This layer depends on: - - URI: git://git.openembedded.org/bitbake - - URI: git://git.openembedded.org/openembedded-core - layers: meta - -Recipe Licenses -=============== - -Due to licensing restrictions some recipes in this layer rely on closed source -or restricted content provided by Xilinx. In order to use these recipes you must -accept or agree to the licensing terms (e.g. EULA, Export Compliance, NDA, -Redistribution, etc). This layer **does not enforce** any legal requirement, it -is the **responsibility of the user** the ensure that they are in compliance -with any licenses or legal requirements for content used. - -In order to use recipes that rely on restricted content the `xilinx` license -flag must be white-listed in the build configuration (e.g. `local.conf`). This -can be done on a per package basis: - - LICENSE_FLAGS_WHITELIST += "xilinx_pmu-rom" - -or generally: - - LICENSE_FLAGS_WHITELIST += "xilinx" - -Generally speaking Xilinx content that is provided as a restricted download -cannot be obtained without a Xilinx account, in order to use this content you -must first download it with your Xilinx account and place the downloaded content -in the `downloads/` directory of your build or on a `PREMIRROR`. Attempting to -fetch the content using bitbake will fail, indicating the URL from which to -acquire the content. - diff --git a/meta-xilinx/meta-xilinx-bsp/README.qemu.md b/meta-xilinx/meta-xilinx-bsp/README.qemu.md deleted file mode 100644 index 992e06187..000000000 --- a/meta-xilinx/meta-xilinx-bsp/README.qemu.md +++ /dev/null @@ -1,25 +0,0 @@ - -ZynqMP - PMU ROM ----------------- - -Since Xilinx tool release v2017.1 multiple components (arm-trusted-firmware, -linux, u-boot, etc.) require the PMU firmware to be loaded. For QEMU this also -means that the PMU ROM must be loaded so that the PMU firmware can be used. - -The PMU ROM is not available for download separately from a location that can be -accessed without a Xilinx account. As such the PMU ROM must be obtained manually -by the user. The PMU ROM is available in the ZCU102 PetaLinux BSP, but can be -extracted without the need for the PetaLinux tools. - -Download the BSP (you will need a Xilinx account and agreement to terms): - -https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-zcu102-v2017.1-final.bsp&akdm=1 - -Once downloaded the PMU ROM can be extracted using the following command and -place `pmu-rom.elf` in the `deploy/images/zcu102-zynqmp/` directory. - -``` -# tar -O -xf xilinx-zcu102-v2017.1-final.bsp \ - xilinx-zcu102-2017.1/pre-built/linux/images/pmu_rom_qemu_sha3.elf > pmu-rom.elf -``` - diff --git a/meta-xilinx/meta-xilinx-bsp/classes/image-types-xilinx-qemu.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/image-types-xilinx-qemu.bbclass deleted file mode 100644 index 45417ea7b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/image-types-xilinx-qemu.bbclass +++ /dev/null @@ -1,10 +0,0 @@ -# Define the 'qemu-sd' conversion type -# -# This conversion type pads any image to the 512K boundary to ensure that the -# image file can be used directly with QEMU's SD emulation which requires the -# block device to match that of valid SD card sizes (which are multiples of -# 512K). - -CONVERSIONTYPES_append = " qemu-sd" -CONVERSION_CMD_qemu-sd = "cp ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type} ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd; truncate -s %512K ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd" -CONVERSION_DEPENDS_qemu-sd = "coreutils-native" diff --git a/meta-xilinx/meta-xilinx-bsp/classes/image-wic-utils.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/image-wic-utils.bbclass deleted file mode 100644 index 562f3263e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/image-wic-utils.bbclass +++ /dev/null @@ -1,51 +0,0 @@ -# Helper/utility functions to work with the IMAGE_BOOT_FILES variable and its -# expected behvaior with regards to the contents of the DEPLOY_DIR_IMAGE. -# -# The use of these functions assume that the deploy directory is populated with -# any dependent files/etc. Such that the recipe using these functions depends -# on the recipe that provides the files being used/queried. - -def boot_files_split_expand(d): - # IMAGE_BOOT_FILES has extra renaming info in the format '<source>;<target>' - for f in (d.getVar("IMAGE_BOOT_FILES") or "").split(" "): - parts = f.split(";", 1) - sources = [parts[0].strip()] - if "*" in parts[0]: - # has glob part - import glob - deployroot = d.getVar("DEPLOY_DIR_IMAGE") - sources = [] - for i in glob.glob(os.path.join(deployroot, parts[0])): - sources.append(os.path.basename(i)) - - # for all sources, yield an entry - for s in sources: - if len(parts) == 2: - yield s, parts[1].strip() - yield s, s - -def boot_files_bitstream(d): - expectedfiles = [("bitstream", True)] - expectedexts = [(".bit", True), (".bin", False)] - # search for bitstream paths, use the renamed file. First matching is used - for source, target in boot_files_split_expand(d): - # skip boot.bin and u-boot.bin, it is not a bitstream - skip = ["boot.bin", "u-boot.bin"] - if source in skip or target in skip: - continue - - for e, t in expectedfiles: - if source == e or target == e: - return target, t - for e, t in expectedexts: - if source.endswith(e) or target.endswith(e): - return target, t - return "", False - -def boot_files_dtb_filepath(d): - dtbs = (d.getVar("IMAGE_BOOT_FILES") or "").split(" ") - for source, target in boot_files_split_expand(d): - if target.endswith(".dtb"): - return target - return "" - diff --git a/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass deleted file mode 100644 index 6da28f36f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass +++ /dev/null @@ -1,35 +0,0 @@ -python __anonymous () { - kerneltypes = set((d.getVar("KERNEL_IMAGETYPE") or "").split()) - kerneltypes |= set((d.getVar("KERNEL_IMAGETYPES") or "").split()) - if any(t.startswith("simpleImage.") for t in kerneltypes): - # Enable building of simpleImage - bb.build.addtask('do_prep_simpleimage', 'do_compile', 'do_configure', d) - uarch = d.getVar("UBOOT_ARCH") - if uarch == "microblaze": - d.appendVarFlag('do_prep_simpleimage', 'depends', ' virtual/dtb:do_populate_sysroot') -} - -do_prep_simpleimage[dirs] += "${B}" -do_prep_simpleimage () { - install -d ${B}/arch/${ARCH}/boot/dts - for type in ${KERNEL_IMAGETYPES} ; do - if [ -z "${type##*simpleImage*}" ] && [ ${ARCH} = "microblaze" ]; then - ext="${type##*.}" - # Microblaze simpleImage only works with dts file - cp ${RECIPE_SYSROOT}/boot/devicetree/${ext}.dts ${B}/arch/${ARCH}/boot/dts/ - fi - done -} - -do_deploy_append () { - for type in ${KERNEL_IMAGETYPES} ; do - if [ -z "${type##*simpleImage*}" ] && [ ${ARCH} = "microblaze" ]; then - base_name=${imageType}-${KERNEL_IMAGE_NAME} - install -m 0644 ${KERNEL_OUTPUT_DIR}/${type}.strip $deployDir/${base_name}.strip - install -m 0644 ${KERNEL_OUTPUT_DIR}/${type}.unstrip $deployDir/${base_name}.unstrip - symlink_name=${imageType}-${KERNEL_IMAGE_LINK_NAME} - ln -sf ${base_name}.strip $deployDir/${symlink_name}.strip - ln -sf ${base_name}.unstrip $deployDir/${symlink_name}.unstrip - fi - done -} diff --git a/meta-xilinx/meta-xilinx-bsp/classes/qemuboot-xilinx.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/qemuboot-xilinx.bbclass deleted file mode 100644 index 1c3f2bb61..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/qemuboot-xilinx.bbclass +++ /dev/null @@ -1,27 +0,0 @@ - -# enable the overrides for the context of the conf only -OVERRIDES .= ":qemuboot-xilinx" - -# Default machine targets for Xilinx QEMU (FDT Generic) -# Allow QB_MACHINE to be overridden by a BSP config -QB_MACHINE ?= "${QB_MACHINE_XILINX}" -QB_RNG="" -QB_MACHINE_XILINX_aarch64 = "-machine arm-generic-fdt" -QB_MACHINE_XILINX_arm = "-M arm-generic-fdt-7series" -QB_MACHINE_XILINX_microblaze = "-M microblaze-fdt-plnx" - -# defaults -QB_DEFAULT_KERNEL ?= "none" - -inherit qemuboot - -# rewrite the qemuboot with the custom sysroot bindir -python do_write_qemuboot_conf_append() { - val = os.path.join(d.getVar('BASE_WORKDIR'), d.getVar('BUILD_SYS'), 'qemu-xilinx-helper-native/1.0-r1/recipe-sysroot-native/usr/bin/') - cf.set('config_bsp', 'STAGING_BINDIR_NATIVE', '%s' % val) - - # write out the updated version from this append - with open(qemuboot, 'w') as f: - cf.write(f) -} - diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-fetch-restricted.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-fetch-restricted.bbclass deleted file mode 100644 index a778ec7dc..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-fetch-restricted.bbclass +++ /dev/null @@ -1,35 +0,0 @@ -# This class is setup to override the default fetching for the target recipe. -# When fetching it forces PREMIRROR only fetching so that no attempts are made -# to fetch the Xilinx downloads that are restricted to authenticated users only. -# -# The purpose of this class is to allow for automatation with pre-downloaded -# content or content that is available with curated/user defined pre-mirrors -# and or pre-populated downloads/ directories. - -python do_fetch() { - xilinx_restricted_url = "xilinx.com/member/forms/download" - - src_uri = (d.getVar('SRC_URI') or "").split() - if len(src_uri) == 0: - return - - for i in src_uri: - if xilinx_restricted_url in i: - # force the use of premirrors only, do not attempt download from xilinx.com - d.setVar("BB_FETCH_PREMIRRORONLY", "1") - break - - try: - fetcher = bb.fetch2.Fetch(src_uri, d) - fetcher.download() - except bb.fetch2.NetworkAccess as e: - if xilinx_restricted_url in e.url: - # fatal on access to xilinx.com restricted downloads, print the url for manual download - bb.fatal("The following download cannot be fetched automatically. " \ - "Please manually download the file and place it in the 'downloads' directory (or on an available PREMIRROR).\n" \ - " %s" % (e.url.split(";")[0])) - else: - bb.fatal(str(e)) - except bb.fetch2.BBFetchException as e: - bb.fatal(str(e)) -} diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-platform-init.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-platform-init.bbclass deleted file mode 100644 index 5d0995004..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-platform-init.bbclass +++ /dev/null @@ -1,14 +0,0 @@ -# This class should be included by any recipe that wants to access or provide -# the platform init source files which are used to initialize a Zynq or ZynqMP -# SoC. - -# Define the path to the xilinx platform init code/headers -PLATFORM_INIT_DIR ?= "/usr/src/xilinx-platform-init" - -PLATFORM_INIT_STAGE_DIR = "${STAGING_DIR_HOST}${PLATFORM_INIT_DIR}" - -# Target files use for platform init -PLATFORM_INIT_FILES ?= "" -PLATFORM_INIT_FILES_zynq = "ps7_init_gpl.c ps7_init_gpl.h" -PLATFORM_INIT_FILES_zynqmp = "psu_init_gpl.c psu_init_gpl.h" - diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass deleted file mode 100644 index 0126d8ba8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass +++ /dev/null @@ -1,11 +0,0 @@ -inherit testimage - -HOSTTOOLS += 'ip ping ps scp ssh stty' - -python do_testimage_prepend () { - from oeqa.core.target.qemu import supported_fstypes - supported_fstypes.append('wic.qemu-sd') -} - -IMAGE_AUTOLOGIN = "0" -IMAGE_FSTYPES = "wic.qemu-sd" diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xlnx-standalone.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xlnx-standalone.bbclass deleted file mode 100644 index 9232b1ef4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/classes/xlnx-standalone.bbclass +++ /dev/null @@ -1,16 +0,0 @@ -# Only enabled when ilp32 is enabled. -def xlnx_ilp32_dict(machdata, d): - machdata["elf"] = { - "aarch64" : (183, 0, 0, True, 32), - "aarch64_be" :(183, 0, 0, False, 32), - } - return machdata - -# Only enabled when microblaze64 is enabled. -def xlnx_mb64_dict(machdata, d): - machdata["elf"] = { - "microblaze": (189, 0, 0, False, 64), - "microblazeeb":(189, 0, 0, False, 64), - "microblazeel":(189, 0, 0, True, 64), - } - return machdata diff --git a/meta-xilinx/meta-xilinx-bsp/conf/0001-local.conf.sample-PMU_ROM-to-use-pmu-rom.elf-from-pr.patch b/meta-xilinx/meta-xilinx-bsp/conf/0001-local.conf.sample-PMU_ROM-to-use-pmu-rom.elf-from-pr.patch deleted file mode 100644 index f7d487fea..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/0001-local.conf.sample-PMU_ROM-to-use-pmu-rom.elf-from-pr.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 4694f1ef8bdb40f5aa82597a62f2a8a8a5a38969 Mon Sep 17 00:00:00 2001 -From: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> -Date: Thu, 13 Aug 2020 16:56:12 -0700 -Subject: [meta-xilinx-bsp][master-upstream][PATCH] local.conf.sample: PMU_ROM - to use pmu-rom.elf from /proj/yocto - -Users have to manually copy pmu-rom.elf to DEPLOY_DIR when using runqemu. -Enable PMU_ROM line within local.conf to use pmu from /proj/yocto/pmu-rom/ - -Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> ---- - meta-xilinx-bsp/conf/local.conf.sample | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/meta-xilinx-bsp/conf/local.conf.sample b/meta-xilinx-bsp/conf/local.conf.sample -index 377a519..5d567af 100644 ---- a/meta-xilinx-bsp/conf/local.conf.sample -+++ b/meta-xilinx-bsp/conf/local.conf.sample -@@ -231,3 +231,5 @@ PMU_FIRMWARE_IMAGE_NAME = "pmu-firmware-${MACHINE}" - # this doesn't mean anything to you. - CONF_VERSION = "1" - -+#Enable the below line to use pmu-rom.elf from a specific path -+#PMU_ROM = "/proj/yocto/pmu-rom/pmu-rom.elf" --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/bblayers.conf.sample b/meta-xilinx/meta-xilinx-bsp/conf/bblayers.conf.sample deleted file mode 100644 index 07f756585..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/bblayers.conf.sample +++ /dev/null @@ -1,35 +0,0 @@ -LCONF_VERSION = "7" - -BBPATH = "${TOPDIR}" -BBFILES ?= "" - -BBLAYERS ?= " \ - ##OEROOT##/meta \ - ##OEROOT##/meta-poky \ - ##OEROOT##/../meta-openembedded/meta-perl \ - ##OEROOT##/../meta-openembedded/meta-python \ - ##OEROOT##/../meta-openembedded/meta-filesystems \ - ##OEROOT##/../meta-openembedded/meta-gnome \ - ##OEROOT##/../meta-openembedded/meta-multimedia \ - ##OEROOT##/../meta-openembedded/meta-networking \ - ##OEROOT##/../meta-openembedded/meta-webserver \ - ##OEROOT##/../meta-openembedded/meta-xfce \ - ##OEROOT##/../meta-openembedded/meta-initramfs \ - ##OEROOT##/../meta-openembedded/meta-oe \ - ##OEROOT##/../meta-browser \ - ##OEROOT##/../meta-qt5 \ - ##OEROOT##/../meta-xilinx/meta-xilinx-bsp \ - ##OEROOT##/../meta-xilinx/meta-xilinx-pynq \ - ##OEROOT##/../meta-xilinx/meta-xilinx-standalone \ - ##OEROOT##/../meta-xilinx/meta-xilinx-contrib \ - ##OEROOT##/../meta-xilinx-tools \ - ##OEROOT##/../meta-petalinux \ - ##OEROOT##/../meta-virtualization \ - ##OEROOT##/../meta-openamp \ - ##OEROOT##/../meta-jupyter \ - ##OEROOT##/../meta-python2 \ -" - -BBLAYERS_NON_REMOVABLE ?= " \ - ##OEROOT##/meta \ -" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/layer.conf b/meta-xilinx/meta-xilinx-bsp/conf/layer.conf deleted file mode 100644 index e680b51c5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/layer.conf +++ /dev/null @@ -1,18 +0,0 @@ -# We have a conf and classes directory, add to BBPATH -BBPATH .= ":${LAYERDIR}" - -# We have a packages directory, add to BBFILES -BBFILES += "${LAYERDIR}/recipes-*/*/*.bb" -BBFILES += "${LAYERDIR}/recipes-*/*/*.bbappend" - -BBFILE_COLLECTIONS += "xilinx" -BBFILE_PATTERN_xilinx = "^${LAYERDIR}/" -BBFILE_PRIORITY_xilinx = "5" - -LAYERDEPENDS_xilinx = "core" - -LAYERSERIES_COMPAT_xilinx = "dunfell gatesgarth" - -BB_DANGLINGAPPENDS_WARNONLY ?= "1" - -XILINX_RELEASE_VERSION = "v2020.2" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/local.conf.sample b/meta-xilinx/meta-xilinx-bsp/conf/local.conf.sample deleted file mode 100644 index 505ba0d60..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/local.conf.sample +++ /dev/null @@ -1,235 +0,0 @@ -# -# This file is your local configuration file and is where all local user settings -# are placed. The comments in this file give some guide to the options a new user -# to the system might want to change but pretty much any configuration option can -# be set in this file. More adventurous users can look at local.conf.extended -# which contains other examples of configuration which can be placed in this file -# but new users likely won't need any of them initially. -# -# Lines starting with the '#' character are commented out and in some cases the -# default values are provided as comments to show people example syntax. Enabling -# the option is a question of removing the # character and making any change to the -# variable as required. - -# BASE = "${COREBASE}/../.." - -# -# Machine Selection -# -# You need to select a specific machine to target the build with. There are a selection -# of emulated machines available which can boot and run in the QEMU emulator: -# -# This sets the default machine if no other machine is selected: -MACHINE ??= "qemuzynq" - -# -# Where to place downloads -# -# During a first build the system will download many different source code tarballs -# from various upstream projects. This can take a while, particularly if your network -# connection is slow. These are all stored in DL_DIR. When wiping and rebuilding you -# can preserve this directory to speed up this part of subsequent builds. This directory -# is safe to share between multiple builds on the same machine too. -# -# The default is a downloads directory under TOPDIR which is the build directory. -# -# DL_DIR ?= "${BASE}/downloads" - -# -# Where to place shared-state files -# -# BitBake has the capability to accelerate builds based on previously built output. -# This is done using "shared state" files which can be thought of as cache objects -# and this option determines where those files are placed. -# -# You can wipe out TMPDIR leaving this directory intact and the build would regenerate -# from these files if no changes were made to the configuration. If changes were made -# to the configuration, only shared state files where the state was still valid would -# be used (done using checksums). -# -# The default is a sstate-cache directory under TOPDIR. -# -# SSTATE_DIR ?= "${BASE}/sstate-cache" - -# -# Where to place the build output -# -# This option specifies where the bulk of the building work should be done and -# where BitBake should place its temporary files and output. Keep in mind that -# this includes the extraction and compilation of many applications and the toolchain -# which can use Gigabytes of hard disk space. -# -# The default is a tmp directory under TOPDIR. -# -#TMPDIR = "${TOPDIR}/tmp" -# -#TMPDIR_versal = "${TOPDIR}/tmp-versal" - -# -# Default policy config -# -# The distribution setting controls which policy settings are used as defaults. -# The default value is fine for general Yocto project use, at least initially. -# Ultimately when creating custom policy, people will likely end up subclassing -# these defaults. -# -DISTRO ?= "petalinux" - -# -# Package Management configuration -# -# This variable lists which packaging formats to enable. Multiple package backends -# can be enabled at once and the first item listed in the variable will be used -# to generate the root filesystems. -# Options are: -# - 'package_deb' for debian style deb files -# - 'package_ipk' for ipk files are used by opkg (a debian style embedded package manager) -# - 'package_rpm' for rpm style packages -# E.g.: PACKAGE_CLASSES ?= "package_rpm package_deb package_ipk" -# We default to ipk: -PACKAGE_CLASSES ?= "package_rpm" - -# -# SDK/ADT target architecture -# -# This variable specifies the architecture to build SDK/ADT items for and means -# you can build the SDK packages for architectures other than the machine you are -# running the build on (i.e. building i686 packages on an x86_64 host). -# Supported values are i686 and x86_64 -#SDKMACHINE ?= "i686" - -# -# Extra image configuration defaults -# -# The EXTRA_IMAGE_FEATURES variable allows extra packages to be added to the generated -# images. Some of these options are added to certain image types automatically. The -# variable can contain the following options: -# "dbg-pkgs" - add -dbg packages for all installed packages -# (adds symbol information for debugging/profiling) -# "dev-pkgs" - add -dev packages for all installed packages -# (useful if you want to develop against libs in the image) -# "ptest-pkgs" - add -ptest packages for all ptest-enabled packages -# (useful if you want to run the package test suites) -# "tools-sdk" - add development tools (gcc, make, pkgconfig etc.) -# "tools-debug" - add debugging tools (gdb, strace) -# "eclipse-debug" - add Eclipse remote debugging support -# "tools-profile" - add profiling tools (oprofile, exmap, lttng, valgrind) -# "tools-testapps" - add useful testing tools (ts_print, aplay, arecord etc.) -# "debug-tweaks" - make an image suitable for development -# e.g. ssh root access has a blank password -# There are other application targets that can be used here too, see -# meta/classes/image.bbclass and meta/classes/core-image.bbclass for more details. -# We default to enabling the debugging tweaks. -EXTRA_IMAGE_FEATURES = "debug-tweaks" - -# -# Additional image features -# -# The following is a list of additional classes to use when building images which -# enable extra features. Some available options which can be included in this variable -# are: -# - 'buildstats' collect build statistics -# - 'image-mklibs' to reduce shared library files size for an image -# - 'image-prelink' in order to prelink the filesystem image -# - 'image-swab' to perform host system intrusion detection -# NOTE: if listing mklibs & prelink both, then make sure mklibs is before prelink -# NOTE: mklibs also needs to be explicitly enabled for a given image, see local.conf.extended -USER_CLASSES ?= "buildstats image-mklibs" - -# -# Runtime testing of images -# -# The build system can test booting virtual machine images under qemu (an emulator) -# after any root filesystems are created and run tests against those images. To -# enable this uncomment this line. See classes/testimage(-auto).bbclass for -# further details. -#TEST_IMAGE = "1" -# -# Interactive shell configuration -# -# Under certain circumstances the system may need input from you and to do this it -# can launch an interactive shell. It needs to do this since the build is -# multithreaded and needs to be able to handle the case where more than one parallel -# process may require the user's attention. The default is iterate over the available -# terminal types to find one that works. -# -# Examples of the occasions this may happen are when resolving patches which cannot -# be applied, to use the devshell or the kernel menuconfig -# -# Supported values are auto, gnome, xfce, rxvt, screen, konsole (KDE 3.x only), none -# Note: currently, Konsole support only works for KDE 3.x due to the way -# newer Konsole versions behave -#OE_TERMINAL = "auto" -# By default disable interactive patch resolution (tasks will just fail instead): -PATCHRESOLVE = "noop" - -# -# Disk Space Monitoring during the build -# -# Monitor the disk space during the build. If there is less that 1GB of space or less -# than 100K inodes in any key build location (TMPDIR, DL_DIR, SSTATE_DIR), gracefully -# shutdown the build. If there is less that 100MB or 1K inodes, perform a hard abort -# of the build. The reason for this is that running completely out of space can corrupt -# files and damages the build in ways which may not be easily recoverable. -# It's necesary to monitor /tmp, if there is no space left the build will fail -# with very exotic errors. -BB_DISKMON_DIRS = "\ - STOPTASKS,${TMPDIR},1G,100K \ - STOPTASKS,${DL_DIR},1G,100K \ - STOPTASKS,${SSTATE_DIR},1G,100K \ - STOPTASKS,/tmp,100M,100K \ - ABORT,${TMPDIR},100M,1K \ - ABORT,${DL_DIR},100M,1K \ - ABORT,${SSTATE_DIR},100M,1K \ - ABORT,/tmp,10M,1K" - -# -# Shared-state files from other locations -# -# As mentioned above, shared state files are prebuilt cache data objects which can -# used to accelerate build time. This variable can be used to configure the system -# to search other mirror locations for these objects before it builds the data itself. -# -# This can be a filesystem directory, or a remote url such as http or ftp. These -# would contain the sstate-cache results from previous builds (possibly from other -# machines). This variable works like fetcher MIRRORS/PREMIRRORS and points to the -# cache locations to check for the shared objects. -# NOTE: if the mirror uses the same structure as SSTATE_DIR, you need to add PATH -# at the end as shown in the examples below. This will be substituted with the -# correct path within the directory structure. -#SSTATE_MIRRORS ?= "\ -#file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \ -#file://.* file:///some/local/dir/sstate/PATH" - -XILINX_VER_MAIN = "2020.2" - -# Uncomment below lines to provide path for custom xsct trim -# This is required for building Versal based devices, please fetch the -# xsct-trim from Xilinx lounge area -# -#EXTERNAL_XSCT_TARBALL = "/proj/yocto/xsct-trim/2020.2_xsct_daily_latest" -#VALIDATE_XSCT_CHECKSUM = '0' - -# XILINX_VIVADO_DESIGN_SUIT should point to the Vivado installation directly if you are using xilinx-mcs recipe in meta-xilinx-tools -#XILINX_VIVADO_DESIGN_SUIT = "/proj/xbuilds/2018.3_daily_latest/installs/lin64/Vivado/2018.3" - -# INHERIT += "externalsrc" -# PREFERRED_PROVIDER_virtual/kernel = "linux-xlnx-dev" -# EXTERNALSRC_pn-linux-xlnx-dev = "${BASE}/sources/linux" -# RM_WORK_EXCLUDE += "linux-xlnx-dev" - -# PREFERRED_PROVIDER_virtual/bootloader = "u-boot-xlnx-dev" -# EXTERNALSRC_pn-u-boot-xlnx-dev = "${BASE}/sources/u-boot" -# RM_WORK_EXCLUDE += "u-boot-xlnx-dev" - -#Add below lines to use runqemu for ZU+ machines -PMU_FIRMWARE_DEPLOY_DIR ??= "${DEPLOY_DIR_IMAGE}" -PMU_FIRMWARE_IMAGE_NAME ??= "pmu-firmware-${MACHINE}" - -# CONF_VERSION is increased each time build/conf/ changes incompatibly and is used to -# track the version of this file when it was generated. This can safely be ignored if -# this doesn't mean anything to you. -CONF_VERSION = "1" - -#Enable the below line to use pmu-rom.elf from a specific path -#PMU_ROM = "/proj/yocto/pmu-rom/pmu-rom.elf" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch32-tc.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch32-tc.conf deleted file mode 100644 index 72fbc80f9..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch32-tc.conf +++ /dev/null @@ -1,220 +0,0 @@ -require conf/multilib.conf -require conf/machine/include/tune-cortexa9.inc -require conf/machine/include/baremetal-tc.conf - -# Define all of the multilibs supproted by this configuration -MULTILIB_GLOBAL_VARIANTS = "${@extend_variants(d,'MULTILIBS','multilib')}" - -MULTILIBS = "multilib:libarmv5tesoftfp multilib:libarmv5tehard" -MULTILIBS += "multilib:libnofp" -MULTILIBS += "multilib:libv7nofp multilib:libv7fpsoftfp multilib:libv7fphard" -MULTILIBS += "multilib:libv7anofp" -MULTILIBS += "multilib:libv7afpsoftfp" -MULTILIBS += "multilib:libv7afpthf multilib:libv7asimdsoftfp" -MULTILIBS += "multilib:libv7asimdhard multilib:libv7vesimdsoftfp" -MULTILIBS += "multilib:libvtvesimdhf" -MULTILIBS += "multilib:libv8anofp" -MULTILIBS += "multilib:libv8asimdsoftfp multilib:libv8asimdhard" - -TUNE_CCARGS = "${TUNE_CCARGS_tune-${DEFAULTTUNE}}" -TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}" - -# Base configuration -# CFLAGS: -DEFAULTTUNE = "aarch32" - -AVAILTUNES += "aarch32" -PACKAGE_EXTRA_ARCHS_tune-aarch32 = "${TUNE_PKGARCH_tune-aarch32}" -BASE_LIB_tune-aarch32 = "lib" -TUNE_FEATURES_tune-aarch32 = "arm" -TUNE_CCARGS_tune-aarch32 = "" -TUNE_PKGARCH_tune-aarch32 = "aarch32" - - -# arm/v5te/softfp -# CFLAGS: -marm -march=armv5te+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libarmv5tesoftfp = "armv5tesoftfp" - -AVAILTUNES += "armv5tesoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv5tesoftfp = "${TUNE_PKGARCH_tune-armv5tesoftfp}" -BASE_LIB_tune-armv5tesoftfp = "lib/arm/v5te/softfp" -TUNE_FEATURES_tune-armv5tesoftfp = "arm" -TUNE_CCARGS_tune-armv5tesoftfp = "-marm -march=armv5te+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv5tesoftfp = "armv5tefp" - - -# arm/v5te/hard -# CFLAGS: -marm -march=armv5te+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libarmv5tehard = "armv5tehard" - -AVAILTUNES += "armv5tehard" -PACKAGE_EXTRA_ARCHS_tune-armv5tehard = "${TUNE_PKGARCH_tune-armv5tehard}" -BASE_LIB_tune-armv5tehard = "lib/arm/v5te/hard" -TUNE_FEATURES_tune-armv5tehard = "arm" -TUNE_CCARGS_tune-armv5tehard = "-marm -march=armv5te+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv5tehard = "armv5tefphf" - - -# thumb/nofp -# CFLAGS: -mthumb -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libnofp = "armnofp" - -AVAILTUNES += "armnofp" -PACKAGE_EXTRA_ARCHS_tune-armnofp = "${TUNE_PKGARCH_tune-armnofp}" -BASE_LIB_tune-armnofp = "lib/thumb/nofp" -TUNE_FEATURES_tune-armnofp = "arm" -TUNE_CCARGS_tune-armnofp = "-mthumb -mfloat-abi=soft" -TUNE_PKGARCH_tune-armnofp = "armt" - - -# thumb/v7/nofp -# CFLAGS: -mthumb -march=armv7 -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv7nofp = "armv7nofp" - -AVAILTUNES += "armv7nofp" -PACKAGE_EXTRA_ARCHS_tune-armv7nofp = "${TUNE_PKGARCH_tune-armv7nofp}" -BASE_LIB_tune-armv7nofp = "lib/thumb/v7/nofp" -TUNE_FEATURES_tune-armv7nofp = "arm" -TUNE_CCARGS_tune-armv7nofp = "-mthumb -march=armv7 -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv7nofp = "armv7t" - - -# thumb/v7+fp/softfp -# CFLAGS: -mthumb -march=armv7+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7fpsoftfp = "armv7fpsoftfp" - -AVAILTUNES += "armv7fpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7fpsoftfp = "${TUNE_PKGARCH_tune-armv7fpsoftfp}" -BASE_LIB_tune-armv7fpsoftfp = "lib/thumb/v7+fp/softfp" -TUNE_FEATURES_tune-armv7fpsoftfp = "arm" -TUNE_CCARGS_tune-armv7fpsoftfp = "-mthumb -march=armv7+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7fpsoftfp = "armv7fpt" - - -# thumb/v7+fp/hard -# CFLAGS: -mthumb -march=armv7+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv7fphard = "armv7fphard" - -AVAILTUNES += "armv7fphard" -PACKAGE_EXTRA_ARCHS_tune-armv7fphard = "${TUNE_PKGARCH_tune-armv7fphard}" -BASE_LIB_tune-armv7fphard = "lib/thumb/v7+fp/hard" -TUNE_FEATURES_tune-armv7fphard = "arm" -TUNE_CCARGS_tune-armv7fphard = "-mthumb -march=armv7+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv7fphard = "armv7fpthf" - - -# thumb/v7-a/nofp -# CFLAGS: -mthumb -march=armv7-a -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv7anofp = "armv7anofp" - -AVAILTUNES += "armv7anofp" -PACKAGE_EXTRA_ARCHS_tune-armv7anofp = "${TUNE_PKGARCH_tune-armv7anofp}" -BASE_LIB_tune-armv7anofp = "lib/thumb/v7-a/nofp" -TUNE_FEATURES_tune-armv7anofp = "arm" -TUNE_CCARGS_tune-armv7anofp = "-mthumb -march=armv7-a -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv7anofp = "armv7at" - - -# thumb/v7-a+fp/softfp -# CFLAGS: -mthumb -march=armv7-a+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7afpsoftfp = "armv7afpsoftfp" - -AVAILTUNES += "armv7afpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7afpsoftfp = "${TUNE_PKGARCH_tune-armv7afpsoftfp}" -BASE_LIB_tune-armv7afpsoftfp = "lib/thumb/v7-a+fp/softfp" -TUNE_FEATURES_tune-armv7afpsoftfp = "arm" -TUNE_CCARGS_tune-armv7afpsoftfp = "-mthumb -march=armv7-a+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7afpsoftfp = "armv7afpt" - - -# thumb/v7-a+fp/hard -# CFLAGS: -mthumb -march=armv7-a+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv7afpthf = "armv7afpthf" - -AVAILTUNES += "armv7afpthf" -PACKAGE_EXTRA_ARCHS_tune-armv7afpthf = "${TUNE_PKGARCH_tune-armv7afpthf}" -BASE_LIB_tune-armv7afpthf = "lib/thumb/v7-a+fp/hard" -TUNE_FEATURES_tune-armv7afpthf = "arm" -TUNE_CCARGS_tune-armv7afpthf = "-mthumb -march=armv7-a+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv7afpthf = "armv7afpthf" - -# thumb/v7-a+simd/softfp -# CFLAGS: -mthumb -march=armv7-a+simd -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7asimdsoftfp = "armv7asimdsoftfp" - -AVAILTUNES += "armv7asimdsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7asimdsoftfp = "${TUNE_PKGARCH_tune-armv7asimdsoftfp}" -BASE_LIB_tune-armv7asimdsoftfp = "lib/thumb/v7-a+simd/softfp" -TUNE_FEATURES_tune-armv7asimdsoftfp = "arm" -TUNE_CCARGS_tune-armv7asimdsoftfp = "-mthumb -march=armv7-a+simd -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7asimdsoftfp = "armv7asimdt" - - -# thumb/v7-a+simd/hard -# CFLAGS: -mthumb -march=armv7-a+simd -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv7asimdhard = "armv7asimdhard" - -AVAILTUNES += "armv7asimdhard" -PACKAGE_EXTRA_ARCHS_tune-armv7asimdhard = "${TUNE_PKGARCH_tune-armv7asimdhard}" -BASE_LIB_tune-armv7asimdhard = "lib/thumb/v7-a+simd/hard" -TUNE_FEATURES_tune-armv7asimdhard = "arm" -TUNE_CCARGS_tune-armv7asimdhard = "-mthumb -march=armv7-a+simd -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv7asimdhard = "armv7asimdthf" - - -# thumb/v7ve+simd/softfp -# CFLAGS: -mthumb -march=armv7ve+simd -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7vesimdsoftfp = "armv7vesimdsoftfp" - -AVAILTUNES += "armv7vesimdsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7vesimdsoftfp = "${TUNE_PKGARCH_tune-armv7vesimdsoftfp}" -BASE_LIB_tune-armv7vesimdsoftfp = "lib/thumb/v7ve+simd/softfp" -TUNE_FEATURES_tune-armv7vesimdsoftfp = "arm" -TUNE_CCARGS_tune-armv7vesimdsoftfp = "-mthumb -march=armv7ve+simd -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7vesimdsoftfp = "armv7vesimdt" - -# thumb/v7ve+simd/hard -# CFLAGS: -mthumb -march=armv7ve+simd -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libvtvesimdhf = "armvtvesimdhf" - -AVAILTUNES += "armvtvesimdhf" -PACKAGE_EXTRA_ARCHS_tune-armvtvesimdhf = "${TUNE_PKGARCH_tune-armvtvesimdhf}" -BASE_LIB_tune-armvtvesimdhf = "lib/thumb/v7ve+simd/hard" -TUNE_FEATURES_tune-armvtvesimdhf = "arm" -TUNE_CCARGS_tune-armvtvesimdhf = "-mthumb -march=armv7ve+simd -mfloat-abi=hard" -TUNE_PKGARCH_tune-armvtvesimdhf = "armv7vesimdthf" - - -# thumb/v8-a/nofp -# CFLAGS: -mthumb -march=armv8-a -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv8anofp = "armv8anofp" - -AVAILTUNES += "armv8anofp" -PACKAGE_EXTRA_ARCHS_tune-armv8anofp = "${TUNE_PKGARCH_tune-armv8anofp}" -BASE_LIB_tune-armv8anofp = "lib/thumb/v8-a/nofp" -TUNE_FEATURES_tune-armv8anofp = "arm" -TUNE_CCARGS_tune-armv8anofp = "-mthumb -march=armv8-a -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv8anofp = "armv8at" - -# thumb/v8-a+simd/softfp -# CFLAGS: -mthumb -march=armv8-a+simd -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv8asimdsoftfp = "armv8asimdsoftfp" - -AVAILTUNES += "armv8asimdsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv8asimdsoftfp = "${TUNE_PKGARCH_tune-armv8asimdsoftfp}" -BASE_LIB_tune-armv8asimdsoftfp = "lib/thumb/v8-a+simd/softfp" -TUNE_FEATURES_tune-armv8asimdsoftfp = "arm" -TUNE_CCARGS_tune-armv8asimdsoftfp = "-mthumb -march=armv8-a+simd -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv8asimdsoftfp = "armv8asimdt" - - -# thumb/v8-a+simd/hard -# CFLAGS: -mthumb -march=armv8-a+simd -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv8asimdhard = "armv8asimdhard" - -AVAILTUNES += "armv8asimdhard" -PACKAGE_EXTRA_ARCHS_tune-armv8asimdhard = "${TUNE_PKGARCH_tune-armv8asimdhard}" -BASE_LIB_tune-armv8asimdhard = "lib/thumb/v8-a+simd/hard" -TUNE_FEATURES_tune-armv8asimdhard = "arm" -TUNE_CCARGS_tune-armv8asimdhard = "-mthumb -march=armv8-a+simd -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv8asimdhard = "armv8asimdthf" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf deleted file mode 100644 index 08c2d1c65..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf +++ /dev/null @@ -1,29 +0,0 @@ -require conf/multilib.conf -require conf/machine/include/tune-cortexa72-cortexa53.inc -require conf/machine/include/baremetal-tc.conf - -# Define ilp32 variant (not in tune files) -TUNEVALID[ilp32] = "ilp32 ABI" - -TUNE_CCARGS .= '${@bb.utils.contains("TUNE_FEATURES", "ilp32", " -mabi=ilp32", "", d)}' - -# ILP request an alternative machine dictionary -INHERIT += "xlnx-standalone" -PACKAGEQA_EXTRA_MACHDEFFUNCS .= '${@bb.utils.contains("TUNE_FEATURES", "ilp32", " xlnx_ilp32_dict", "", d)}' - -# Define all of the multilibs supported by this configuration -MULTILIB_GLOBAL_VARIANTS = "${@extend_variants(d,'MULTILIBS','multilib')}" -MULTILIBS = "multilib:libilp32" - -# Base configuration -# CFLAGS: -DEFAULTTUNE = "cortexa72-cortexa53" - -# CFLAGS: -mabi=ilp32 -DEFAULTTUNE_virtclass-multilib-libilp32 = "cortexa72-cortexa53-ilp32" - -AVAILTUNES += "cortexa72-cortexa53-ilp32" -ARMPKGARCH_tune-cortexa72-cortexa53-ilp32 = "${ARMPKGARCH_tune-cortexa72-cortexa53}-ilp32" -TUNE_FEATURES_tune-cortexa72-cortexa53-ilp32 = "${TUNE_FEATURES_tune-cortexa72-cortexa53} ilp32" -PACKAGE_EXTRA_ARCHS_tune-cortexa72-cortexa53-ilp32 = "${PACKAGE_EXTRA_ARCHS_tune-cortexa72-cortexa53} cortexa72-cortexa53-ilp32" -BASE_LIB_tune-cortexa72-cortexa53-ilp32 = "lib/ilp32" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/arm-rm-tc.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/arm-rm-tc.conf deleted file mode 100644 index c13133398..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/arm-rm-tc.conf +++ /dev/null @@ -1,264 +0,0 @@ -require conf/multilib.conf -require conf/machine/include/tune-cortexrm.inc -require conf/machine/include/baremetal-tc.conf - -# Define all of the multilibs supproted by this configuration -MULTILIB_GLOBAL_VARIANTS = "${@extend_variants(d,'MULTILIBS','multilib')}" - -MULTILIBS = "multilib:libarmv5tesoftfp multilib:libarmv5tehard" -MULTILIBS += "multilib:libnofp" -MULTILIBS += "multilib:libv7nofp multilib:libv7fpsoftfp multilib:libv7fphard" -MULTILIBS += "multilib:libv6mnofp" -MULTILIBS += "multilib:libv7mnofp" -MULTILIBS += "multilib:libv7emnofp multilib:libv7emfpsoftfp" -MULTILIBS += "multilib:libv7emfphard multilib:libv7emdpsoftfp" -MULTILIBS += "multilib:libv7emdphard" -MULTILIBS += "multilib:libv8mbasenofp" -MULTILIBS += "multilib:libv8mmainnofp multilib:libv8mmainfpsoftfp multilib:libv8mmainfphard multilib:libv8mmaindpsoftfp multilib:libv8mmaindphard" - -TUNE_CCARGS = "${TUNE_CCARGS_tune-${DEFAULTTUNE}}" -TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}" - -# Base configuration -# CFLAGS: -DEFAULTTUNE = "armrm" - -AVAILTUNES += "armrm" -PACKAGE_EXTRA_ARCHS_tune-armrm = "${TUNE_PKGARCH_tune-armrm}" -BASE_LIB_tune-armrm = "lib" -TUNE_FEATURES_tune-armrm = "arm armrm" -TUNE_CCARGS_tune-armrm = "" -TUNE_PKGARCH_tune-armrm = "armrm" - - -# arm/v5te/softfp -# CFLAGS: -marm -march=armv5te+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libarmv5tesoftfp = "armv5tesoftfp" - -AVAILTUNES += "armv5tesoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv5tesoftfp = "${TUNE_PKGARCH_tune-armv5tesoftfp}" -BASE_LIB_tune-armv5tesoftfp = "lib/arm/v5te/softfp" -TUNE_FEATURES_tune-armv5tesoftfp = "arm armrm" -TUNE_CCARGS_tune-armv5tesoftfp = "-marm -march=armv5te+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv5tesoftfp = "armv5tefp" - - -# arm/v5te/hard -# CFLAGS: -marm -march=armv5te+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libarmv5tehard = "armv5tehard" - -AVAILTUNES += "armv5tehard" -PACKAGE_EXTRA_ARCHS_tune-armv5tehard = "${TUNE_PKGARCH_tune-armv5tehard}" -BASE_LIB_tune-armv5tehard = "lib/arm/v5te/hard" -TUNE_FEATURES_tune-armv5tehard = "arm armrm" -TUNE_CCARGS_tune-armv5tehard = "-marm -march=armv5te+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv5tehard = "armv5tefphf" - - -# thumb/nofp -# CFLAGS: -mthumb -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libnofp = "armnofp" - -AVAILTUNES += "armnofp" -PACKAGE_EXTRA_ARCHS_tune-armnofp = "${TUNE_PKGARCH_tune-armnofp}" -BASE_LIB_tune-armnofp = "lib/thumb/nofp" -TUNE_FEATURES_tune-armnofp = "arm armrm" -TUNE_CCARGS_tune-armnofp = "-mthumb -mfloat-abi=soft" -TUNE_PKGARCH_tune-armnofp = "armt" - - -# thumb/v7/nofp -# CFLAGS: -mthumb -march=armv7 -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv7nofp = "armv7nofp" - -AVAILTUNES += "armv7nofp" -PACKAGE_EXTRA_ARCHS_tune-armv7nofp = "${TUNE_PKGARCH_tune-armv7nofp}" -BASE_LIB_tune-armv7nofp = "lib/thumb/v7/nofp" -TUNE_FEATURES_tune-armv7nofp ="arm armrm" -TUNE_CCARGS_tune-armv7nofp = "-mthumb -march=armv7 -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv7nofp = "armv7t" - - -# thumb/v7+fp/softfp -# CFLAGS: -mthumb -march=armv7+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7fpsoftfp = "armv7fpsoftfp" - -AVAILTUNES += "armv7fpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7fpsoftfp = "${TUNE_PKGARCH_tune-armv7fpsoftfp}" -BASE_LIB_tune-armv7fpsoftfp = "lib/thumb/v7+fp/softfp" -TUNE_FEATURES_tune-armv7fpsoftfp ="arm armrm" -TUNE_CCARGS_tune-armv7fpsoftfp = "-mthumb -march=armv7+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7fpsoftfp = "armv7fpt" - - -# thumb/v7+fp/hard -# CFLAGS: -mthumb -march=armv7+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv7fphard = "armv7fphard" - -AVAILTUNES += "armv7fphard" -PACKAGE_EXTRA_ARCHS_tune-armv7fphard = "${TUNE_PKGARCH_tune-armv7fphard}" -BASE_LIB_tune-armv7fphard = "lib/thumb/v7+fp/hard" -TUNE_FEATURES_tune-armv7fphard ="arm armrm" -TUNE_CCARGS_tune-armv7fphard = "-mthumb -march=armv7+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv7fphard = "armv7fpthf" - - -# thumb/v6-m/nofp -# CFLAGS: -mthumb -march=armv6s-m -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv6mnofp = "armv6mnofp" - -# Workaround for this multilib in newlib -# newlib/libc/sys/arm/trap.S:88: Error: lo register required -- `sub ip,sp,ip -EXTRA_OECONF_append_pn-libv6mnofp-newlib = " --disable-newlib-supplied-syscalls" - -AVAILTUNES += "armv6mnofp" -PACKAGE_EXTRA_ARCHS_tune-armv6mnofp = "${TUNE_PKGARCH_tune-armv6mnofp}" -BASE_LIB_tune-armv6mnofp = "lib/thumb/v6-m/nofp" -TUNE_FEATURES_tune-armv6mnofp ="arm armrm" -TUNE_CCARGS_tune-armv6mnofp = "-mthumb -march=armv6s-m -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv6mnofp = "armv6smt" - - -# thumb/v7-m/nofp -# CFLAGS: -mthumb -march=armv7-m -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv7mnofp = "armv7mnofp" - -AVAILTUNES += "armv7mnofp" -PACKAGE_EXTRA_ARCHS_tune-armv7mnofp = "${TUNE_PKGARCH_tune-armv7mnofp}" -BASE_LIB_tune-armv7mnofp = "lib/thumb/v7-m/nofp" -TUNE_FEATURES_tune-armv7mnofp ="arm armrm" -TUNE_CCARGS_tune-armv7mnofp = "-mthumb -march=armv7-m -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv7mnofp = "armv7mt" - - -# thumb/v7e-m/nofp -# CFLAGS: -mthumb -march=armv7e-m -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv7emnofp = "armv7emnofp" - -AVAILTUNES += "armv7emnofp" -PACKAGE_EXTRA_ARCHS_tune-armv7emnofp = "${TUNE_PKGARCH_tune-armv7emnofp}" -BASE_LIB_tune-armv7emnofp = "lib/thumb/v7e-m/nofp" -TUNE_FEATURES_tune-armv7emnofp ="arm armrm" -TUNE_CCARGS_tune-armv7emnofp = "-mthumb -march=armv7e-m -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv7emnofp = "armv7emt" - - -# thumb/v7e-m+fp/softfp -# CFLAGS: -mthumb -march=armv7e-m+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7emfpsoftfp = "armv7emfpsoftfp" - -AVAILTUNES += "armv7emfpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7emfpsoftfp = "${TUNE_PKGARCH_tune-armv7emfpsoftfp}" -BASE_LIB_tune-armv7emfpsoftfp = "lib/thumb/v7e-m+fp/softfp" -TUNE_FEATURES_tune-armv7emfpsoftfp ="arm armrm" -TUNE_CCARGS_tune-armv7emfpsoftfp = "-mthumb -march=armv7e-m+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7emfpsoftfp = "armv7emfpt" - - -# thumb/v7e-m+fp/hard -# CFLAGS: -mthumb -march=armv7e-m+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv7emfphard = "armv7emfphard" - -AVAILTUNES += "armv7emfphard" -PACKAGE_EXTRA_ARCHS_tune-armv7emfphard = "${TUNE_PKGARCH_tune-armv7emfphard}" -BASE_LIB_tune-armv7emfphard = "lib/thumb/v7e-m+fp/hard" -TUNE_FEATURES_tune-armv7emfphard ="arm armrm" -TUNE_CCARGS_tune-armv7emfphard = "-mthumb -march=armv7e-m+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv7emfphard = "armv7emfpthf" - - -# thumb/v7e-m+dp/softfp -# CFLAGS: -mthumb -march=armv7e-m+fp.dp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv7emdpsoftfp = "armv7emdpsoftfp" - -AVAILTUNES += "armv7emdpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv7emdpsoftfp = "${TUNE_PKGARCH_tune-armv7emdpsoftfp}" -BASE_LIB_tune-armv7emdpsoftfp = "lib/thumb/v7e-m+dp/softfp" -TUNE_FEATURES_tune-armv7emdpsoftfp ="arm armrm" -TUNE_CCARGS_tune-armv7emdpsoftfp = "-mthumb -march=armv7e-m+fp.dp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv7emdpsoftfp = "armv7emdp" - -# thumb/v7e-m+dp/hard -# CFLAGS: -mthumb -march=armv7e-m+fp.dp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv7emdphard = "armv7emdphard" - -AVAILTUNES += "armv7emdphard" -PACKAGE_EXTRA_ARCHS_tune-armv7emdphard = "${TUNE_PKGARCH_tune-armv7emdphard}" -BASE_LIB_tune-armv7emdphard = "lib/thumb/v7e-m+dp/hard" -TUNE_FEATURES_tune-armv7emdphard ="arm armrm" -TUNE_CCARGS_tune-armv7emdphard = "-mthumb -march=armv7e-m+fp.dp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv7emdphard = "armv7emdpthf" - - -# thumb/v8-m.base/nofp -# CFLAGS: -mthumb -march=armv8-m.base -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv8mbasenofp = "armv8mbasenofp" - -# Workaround for this multilib in newlib -# newlib/libc/sys/arm/trap.S:88: Error: lo register required -- `sub ip,sp,ip' -EXTRA_OECONF_append_pn-libv8mbasenofp-newlib = " --disable-newlib-supplied-syscalls" - -AVAILTUNES += "armv8mbasenofp" -PACKAGE_EXTRA_ARCHS_tune-armv8mbasenofp = "${TUNE_PKGARCH_tune-armv8mbasenofp}" -BASE_LIB_tune-armv8mbasenofp = "lib/thumb/v8-m.base/nofp" -TUNE_FEATURES_tune-armv8mbasenofp ="arm armrm" -TUNE_CCARGS_tune-armv8mbasenofp = "-mthumb -march=armv8-m.base -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv8mbasenofp = "armv8mbaset" - -# thumb/v8-m.main/nofp -# CFLAGS: -mthumb -march=armv8-m.main -mfloat-abi=soft -DEFAULTTUNE_virtclass-multilib-libv8mmainnofp = "armv8mmainnofp" - -AVAILTUNES += "armv8mmainnofp" -PACKAGE_EXTRA_ARCHS_tune-armv8mmainnofp = "${TUNE_PKGARCH_tune-armv8mmainnofp}" -BASE_LIB_tune-armv8mmainnofp = "lib/thumb/v8-m.main/nofp" -TUNE_FEATURES_tune-armv8mmainnofp ="arm armrm" -TUNE_CCARGS_tune-armv8mmainnofp = "-mthumb -march=armv8-m.main -mfloat-abi=soft" -TUNE_PKGARCH_tune-armv8mmainnofp = "armv8mmaint" - - -# thumb/v8-m.main+fp/softfp -# CFLAGS: -mthumb -march=armv8-m.main+fp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv8mmainfpsoftfp = "armv8mmainfpsoftfp" - -AVAILTUNES += "armv8mmainfpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv8mmainfpsoftfp = "${TUNE_PKGARCH_tune-armv8mmainfpsoftfp}" -BASE_LIB_tune-armv8mmainfpsoftfp = "lib/thumb/v8-m.main+fp/softfp" -TUNE_FEATURES_tune-armv8mmainfpsoftfp ="arm armrm" -TUNE_CCARGS_tune-armv8mmainfpsoftfp = "-mthumb -march=armv8-m.main+fp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv8mmainfpsoftfp = "armv8mmainfpt" - -# thumb/v8-m.main+fp/hard -# CFLAGS: -mthumb -march=armv8-m.main+fp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv8mmainfphard = "armv8mmainfphard" - -AVAILTUNES += "armv8mmainfphard" -PACKAGE_EXTRA_ARCHS_tune-armv8mmainfphard = "${TUNE_PKGARCH_tune-armv8mmainfphard}" -BASE_LIB_tune-armv8mmainfphard = "lib/thumb/v8-m.main+fp/hard" -TUNE_FEATURES_tune-armv8mmainfphard ="arm armrm" -TUNE_CCARGS_tune-armv8mmainfphard = "-mthumb -march=armv8-m.main+fp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv8mmainfphard = "armv8mmainfpthf" - - -# thumb/v8-m.main+dp/softfp -# CFLAGS: -mthumb -march=armv8-m.main+fp.dp -mfloat-abi=softfp -DEFAULTTUNE_virtclass-multilib-libv8mmaindpsoftfp = "armv8mmaindpsoftfp" - -AVAILTUNES += "armv8mmaindpsoftfp" -PACKAGE_EXTRA_ARCHS_tune-armv8mmaindpsoftfp = "${TUNE_PKGARCH_tune-armv8mmaindpsoftfp}" -BASE_LIB_tune-armv8mmaindpsoftfp = "lib/thumb/v8-m.main+dp/softfp" -TUNE_FEATURES_tune-armv8mmaindpsoftfp ="arm armrm" -TUNE_CCARGS_tune-armv8mmaindpsoftfp = "-mthumb -march=armv8-m.main+fp.dp -mfloat-abi=softfp" -TUNE_PKGARCH_tune-armv8mmaindpsoftfp = "armv8mmainfpdpt" - - -# thumb/v8-m.main+dp/hard -# CFLAGS: -mthumb -march=armv8-m.main+fp.dp -mfloat-abi=hard -DEFAULTTUNE_virtclass-multilib-libv8mmaindphard = "armv8mmaindphard" - -AVAILTUNES += "armv8mmaindphard" -PACKAGE_EXTRA_ARCHS_tune-armv8mmaindphard = "${TUNE_PKGARCH_tune-armv8mmaindphard}" -BASE_LIB_tune-armv8mmaindphard = "lib/thumb/v8-m.main+dp/hard" -TUNE_FEATURES_tune-armv8mmaindphard ="arm armrm" -TUNE_CCARGS_tune-armv8mmaindphard = "-mthumb -march=armv8-m.main+fp.dp -mfloat-abi=hard" -TUNE_PKGARCH_tune-armv8mmaindphard = "armv8mmainfpdpthf" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa53-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa53-zynqmp.conf deleted file mode 100644 index d2bbab0de..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa53-zynqmp.conf +++ /dev/null @@ -1,3 +0,0 @@ -DEFAULTTUNE ?= "cortexa53" - -require conf/machine/include/soc-zynqmp.inc diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf deleted file mode 100644 index 27e109c01..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf +++ /dev/null @@ -1,3 +0,0 @@ -DEFAULTTUNE ?= "cortexa72" - -require conf/machine/include/soc-versal.inc diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa9-zynq.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa9-zynq.conf deleted file mode 100644 index 02568109b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexa9-zynq.conf +++ /dev/null @@ -1 +0,0 @@ -require conf/machine/include/soc-zynq.inc diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexr5-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexr5-versal.conf deleted file mode 100644 index fa58dc007..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexr5-versal.conf +++ /dev/null @@ -1,3 +0,0 @@ -DEFAULTTUNE ?= "cortexr5f" - -require conf/machine/include/soc-versal.inc diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexr5-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexr5-zynqmp.conf deleted file mode 100644 index 817150f83..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/cortexr5-zynqmp.conf +++ /dev/null @@ -1,3 +0,0 @@ -DEFAULTTUNE ?= "cortexr5f" - -require conf/machine/include/soc-zynqmp.inc diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/baremetal-tc.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/baremetal-tc.conf deleted file mode 100644 index a53ceac25..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/baremetal-tc.conf +++ /dev/null @@ -1,7 +0,0 @@ -# This is specific to baremetal toolchains only. -# -# Some of the operations we want to do are different then regular Yocto -# Project SDK workflows, so wrap baremetal toolchain items in a custom -# override: - -MACHINEOVERRIDES_append = ":baremetal-multilib-tc" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc deleted file mode 100644 index f2533be70..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc +++ /dev/null @@ -1,79 +0,0 @@ -# Default Xilinx BSP Machine settings - -MACHINE_FEATURES_BACKFILL_CONSIDERED += "rtc" - -# File System Configuration -IMAGE_FSTYPES ?= "tar.gz cpio cpio.gz.u-boot" - -# Kernel Configuration -PREFERRED_PROVIDER_virtual/kernel ??= "linux-xlnx" - -# U-Boot Configuration -PREFERRED_PROVIDER_virtual/bootloader ??= "u-boot-xlnx" -PREFERRED_PROVIDER_virtual/boot-bin ??= "${PREFERRED_PROVIDER_virtual/bootloader}" - -do_image_wic[depends] += "${@' '.join('%s:do_deploy' % r for r in (d.getVar('WIC_DEPENDS') or "").split())}" - -UBOOT_SUFFIX ?= "img" -UBOOT_SUFFIX_microblaze ?= "bin" - -UBOOT_BINARY ?= "u-boot.${UBOOT_SUFFIX}" -UBOOT_ELF ?= "u-boot" -UBOOT_ELF_aarch64 ?= "u-boot.elf" - -#Hardware accelaration -PREFERRED_PROVIDER_virtual/libgles1_mali400 = "libmali-xlnx" -PREFERRED_PROVIDER_virtual/libgles2_mali400 = "libmali-xlnx" -PREFERRED_PROVIDER_virtual/egl_mali400 = "libmali-xlnx" -PREFERRED_PROVIDER_virtual/libgl_mali400 = "mesa-gl" -PREFERRED_PROVIDER_virtual/mesa_mali400 = "mesa-gl" - -# microblaze does not get on with pie for reasons not looked into as yet -GCCPIE_microblaze = "" -GLIBCPIE_microblaze = "" -SECURITY_CFLAGS_microblaze = "" -SECURITY_LDFLAGS_microblaze = "" -# Microblaze does not support gnu hash style -LINKER_HASH_STYLE_microblaze = "sysv" - -XSERVER ?= " \ - xserver-xorg \ - xf86-input-evdev \ - xf86-input-mouse \ - xf86-input-keyboard \ - xf86-video-fbdev \ - ${XSERVER_EXT} \ - " - -IMAGE_BOOT_FILES ?= "${@get_default_image_boot_files(d)}" - -def get_default_image_boot_files(d): - files = [] - - # kernel images - kerneltypes = set((d.getVar("KERNEL_IMAGETYPE") or "").split()) - kerneltypes |= set((d.getVar("KERNEL_IMAGETYPES") or "").split()) - for i in kerneltypes: - files.append(i) - - # u-boot image - if d.getVar("UBOOT_BINARY"): - files.append(d.getVar("UBOOT_BINARY")) - - # device trees (device-tree only), these are first as they are likely desired over the kernel ones - if "device-tree" in (d.getVar("MACHINE_ESSENTIAL_EXTRA_RDEPENDS") or ""): - files.append("devicetree/*.dtb") - - - # device trees (kernel only) - if d.getVar("KERNEL_DEVICETREE"): - dtbs = d.getVar("KERNEL_DEVICETREE").split(" ") - dtbs = [os.path.basename(d) for d in dtbs] - for dtb in dtbs: - files.append(dtb) - - return " ".join(files) - -XSERVER_EXT ?= "" - -FPGA_MNGR_RECONFIG_ENABLE ?= "${@bb.utils.contains('IMAGE_FEATURES', 'fpga-manager', '1', '0', d)}" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-qemu.inc deleted file mode 100644 index b804112b5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-qemu.inc +++ /dev/null @@ -1,55 +0,0 @@ -# This include is used to setup default QEMU and qemuboot config for meta-xilinx -# machines. - -# Use the xilinx specific version for these users -IMAGE_CLASSES += "qemuboot-xilinx" - -# depend on qemu-helper-native, which will depend on QEMU -EXTRA_IMAGEDEPENDS += "qemu-helper-native" - -PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native" -PREFERRED_PROVIDER_qemu = "qemu-xilinx" -PREFERRED_PROVIDER_qemu-native = "qemu-xilinx-native" -PREFERRED_PROVIDER_nativesdk-qemu = "nativesdk-qemu-xilinx" - -def qemu_default_dtb(d): - if d.getVar("IMAGE_BOOT_FILES", True): - dtbs = d.getVar("IMAGE_BOOT_FILES", True).split(" ") - # IMAGE_BOOT_FILES has extra renaming info in the format '<source>;<target>' - # Note: Wildcard sources work here only because runqemu expands them at run time - dtbs = [f.split(";")[0] for f in dtbs] - dtbs = [f for f in dtbs if f.endswith(".dtb")] - if len(dtbs) != 0: - return dtbs[0] - return "" - -def qemu_default_serial(d): - if d.getVar("SERIAL_CONSOLES", True): - first_console = d.getVar("SERIAL_CONSOLES", True).split(" ")[0] - speed, console = first_console.split(";", 1) - # zynqmp uses earlycon and stdout (in dtb) - if "zynqmp" in d.getVar("MACHINEOVERRIDES", True).split(":"): - return "" - return "console=%s,%s earlyprintk" % (console, speed) - return "" - -def qemu_target_binary(d): - ta = d.getVar("TARGET_ARCH", True) - if ta == "microblazeeb": - ta = "microblaze" - elif ta == "arm": - ta = "aarch64" - return "qemu-system-%s" % ta - -def qemu_zynqmp_unhalt(d, multiarch): - if multiarch: - return "-global xlnx,zynqmp-boot.cpu-num=0 -global xlnx,zynqmp-boot.use-pmufw=true" - return "-device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4 -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4" - -# For qemuboot, default setup across all machines in meta-xilinx -QB_SYSTEM_NAME_aarch64 ?= "${@qemu_target_binary(d)}-multiarch" -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE ?= "cpio" -QB_DTB ?= "${@qemu_default_dtb(d)}" -QB_KERNEL_CMDLINE_APPEND ?= "${@qemu_default_serial(d)}" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-tune-include.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-tune-include.inc deleted file mode 100644 index 7b6bd12ab..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-tune-include.inc +++ /dev/null @@ -1,14 +0,0 @@ -# Unfortunately various tunefiles don't include each other, so create -# a list of things to require based on the DEFAULTTUNE setting. -TUNEFILE[cortexr5] = "conf/machine/include/tune-cortexrm.inc" -TUNEFILE[cortexr5f] = "conf/machine/include/tune-cortexrm.inc" -TUNEFILE[cortexa9thf-neon] = "conf/machine/include/tune-cortexa9.inc" -TUNEFILE[cortexa53] = "conf/machine/include/tune-cortexa53.inc" -TUNEFILE[cortexa72] = "conf/machine/include/tune-cortexa72.inc" -TUNEFILE[cortexa72-cortexa53] = "conf/machine/include/tune-cortexa72-cortexa53.inc" -TUNEFILE[microblaze] = "conf/machine/include/tune-microblaze.inc" - -# Default to arch-armv8a.inc -TUNEFILE = "${@ d.getVarFlag('TUNEFILE', d.getVar('DEFAULTTUNE')) if d.getVarFlag('TUNEFILE', d.getVar('DEFAULTTUNE')) else 'conf/machine/include/arm/arch-armv8a.inc'}" - -require ${TUNEFILE} diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc deleted file mode 100644 index d15f4909a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc +++ /dev/null @@ -1,19 +0,0 @@ -DEFAULTTUNE ?= "cortexa72-cortexa53" -SOC_FAMILY ?= "versal" - -# Available SOC_VARIANT's for versal: -# "-prime" - Versal deafult Prime Devices -# "-ai-core" - Versal AI-core Devices -# "-premium" - Versal Premium Devices - -SOC_VARIANT ?= "-prime" - -require soc-tune-include.inc -require xilinx-soc-family.inc - -# Linux Configuration -KERNEL_IMAGETYPE ?= "Image" - -WIC_DEPENDS ?= "virtual/kernel virtual/bootloader virtual/boot-bin virtual/arm-trusted-firmware" - -UBOOT_ELF ?= "u-boot.elf" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-zynq.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-zynq.inc deleted file mode 100644 index 0111cbd98..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-zynq.inc +++ /dev/null @@ -1,24 +0,0 @@ -DEFAULTTUNE ?= "cortexa9thf-neon" -SOC_FAMILY ?= "zynq" - -# Available SOC_VARIANT's for zynq: -# 7zs - Zynq-7000 Single A9 Core -# 7z - Zynq-7000 Dual A9 Core - -SOC_VARIANT ?= "7z" - -require soc-tune-include.inc -require xilinx-soc-family.inc - -# Linux Configuration -KERNEL_IMAGETYPE ?= "uImage" -KERNEL_IMAGETYPES += "zImage" - -# Set default load address. -# Override with KERNEL_EXTRA_ARGS_<board> += "..." in machine file if required -KERNEL_EXTRA_ARGS_zynq += "UIMAGE_LOADADDR=0x8000" - -# WIC Specific dependencies -WIC_DEPENDS ?= "virtual/kernel virtual/bootloader virtual/boot-bin" - -UBOOT_ELF ?= "u-boot.elf" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-zynqmp.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-zynqmp.inc deleted file mode 100644 index 8d421fb36..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-zynqmp.inc +++ /dev/null @@ -1,28 +0,0 @@ -DEFAULTTUNE ?= "cortexa72-cortexa53" -SOC_FAMILY ?= "zynqmp" - -# Available SOC_VARIANT's for zynqmp: -# "cg" - Zynq UltraScale+ CG Devices -# "eg" - Zynq UltraScale+ EG Devices -# "ev" - Zynq UltraScale+ EV Devices -# "dr" - Zynq UltraScale+ DR Devices - -SOC_VARIANT ?= "eg" - -MACHINEOVERRIDES_prepend_zynqmpeg = "mali400:" -MACHINEOVERRIDES_prepend_zynqmpev = "mali400:vcu:" - -require soc-tune-include.inc -require xilinx-soc-family.inc - -# Linux Configuration -KERNEL_IMAGETYPE ?= "Image" - -# Support multilib on zynqmp -DEFAULTTUNE_virtclass-multilib-lib32 ?= "armv7vethf-neon-vfpv4" - -WIC_DEPENDS ?= "virtual/kernel virtual/bootloader virtual/boot-bin virtual/arm-trusted-firmware" - -UBOOT_SUFFIX ?= "bin" - -XSERVER_EXT_zynqmp ?= "xf86-video-armsoc" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-cortexrm.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-cortexrm.inc deleted file mode 100644 index 66edbdbdb..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-cortexrm.inc +++ /dev/null @@ -1,21 +0,0 @@ -DEFAULTTUNE ?= "cortexr5" - -require conf/machine/include/arm/arch-armv8a.inc - -TUNEVALID[armrm] = "Enable ARM Cortex-R/M Family" -MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armrm', 'armrm:', '' ,d)}" - -TUNEVALID[cortexr5] = "Enable Cortex-r5 specific processor optimizations" -TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexr5', ' -mcpu=cortex-r5', '', d)}" - -AVAILTUNES += "cortexr5" -ARMPKGARCH_tune-cortexr5 = "cortexr5" - -TUNE_FEATURES_tune-cortexr5 = "armrm cortexr5" -PACKAGE_EXTRA_ARCHS_tune-cortexr5 = "${TUNE_PKGARCH}" - -AVAILTUNES += "cortexr5f" -ARMPKGARCH_tune-cortexr5f = "cortexr5f" - -TUNE_FEATURES_tune-cortexr5f = "armrm cortexr5 vfpv3d16 callconvention-hard" -PACKAGE_EXTRA_ARCHS_tune-cortexr5f = "${TUNE_PKGARCH}" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/xilinx-board.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/xilinx-board.inc deleted file mode 100644 index 700a2f805..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/xilinx-board.inc +++ /dev/null @@ -1,12 +0,0 @@ -BOARD ??= "" -BOARD_VARIANT ??= "" - -MACHINEOVERRIDES =. "${@['', '${BOARD}:']['${BOARD}' != '']}" -MACHINEOVERRIDES =. "${@['', '${BOARD}${BOARD_VARIANT}:']['${BOARD_VARIANT}' != '']}" - - -BOARD_ARCH ?= "${BOARD}" -BOARDVARIANT_ARCH ?= "${BOARD}${BOARD_VARIANT}" - -PACKAGE_EXTRA_ARCHS_append = " ${BOARD_ARCH}" -PACKAGE_EXTRA_ARCHS_append = "${@['', ' ${BOARDVARIANT_ARCH}'][d.getVar('BOARDVARIANT_ARCH') != d.getVar('BOARD_ARCH')]}" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/xilinx-soc-family.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/xilinx-soc-family.inc deleted file mode 100644 index e6c62ccc6..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/xilinx-soc-family.inc +++ /dev/null @@ -1,10 +0,0 @@ -require conf/machine/include/soc-family.inc - -SOC_VARIANT ??= "" -MACHINEOVERRIDES =. "${@['', '${SOC_FAMILY}${SOC_VARIANT}:']['${SOC_VARIANT}' != '']}" - -SOC_FAMILY_ARCH ?= "${SOC_FAMILY}" -SOC_VARIANT_ARCH ?= "${SOC_FAMILY}${SOC_VARIANT}" - -PACKAGE_EXTRA_ARCHS_append = " ${SOC_FAMILY_ARCH}" -PACKAGE_EXTRA_ARCHS_append = "${@['', ' ${SOC_VARIANT_ARCH}'][d.getVar('SOC_VARIANT_ARCH') != d.getVar('SOC_FAMILY_ARCH')]}" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/kc705-microblazeel.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/kc705-microblazeel.conf deleted file mode 100644 index 73f5b0468..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/kc705-microblazeel.conf +++ /dev/null @@ -1,22 +0,0 @@ -#@TYPE: Machine -#@NAME: kc705-microblazeel -#@DESCRIPTION: Machine support for Xilinx KC705 Embedded Kit. -# - -require conf/machine/include/tune-microblaze.inc -require conf/machine/include/machine-xilinx-default.inc - -TUNE_FEATURES_tune-microblaze += "v11.0 barrel-shift reorder pattern-compare multiply-high divide-hard" - -MACHINE_FEATURES = "" - -USE_VT = "" -SERIAL_CONSOLES ?= "115200;ttyS0" - -KERNEL_IMAGETYPE ?= "linux.bin.ub" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -EXTRA_IMAGEDEPENDS += "virtual/bitstream virtual/bootloader" - -UBOOT_MACHINE = "microblaze-generic_defconfig" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-plm.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-plm.conf deleted file mode 100644 index 9ab8a46b2..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-plm.conf +++ /dev/null @@ -1,10 +0,0 @@ -DEFAULTTUNE ?= "microblaze" - -require conf/machine/include/soc-versal.inc - -# Endianess, multiplier, barrel shift, pattern compare, floating point double or single, are the possibilities -AVAILTUNES += "microblaze" -TUNE_FEATURES_tune-microblaze = "microblaze v11.0 barrel-shift pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblaze = "${TUNE_PKGARCH}" - -LINKER_HASH_STYLE_microblaze = "sysv" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-pmu.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-pmu.conf deleted file mode 100644 index 09fd3c805..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-pmu.conf +++ /dev/null @@ -1,10 +0,0 @@ -DEFAULTTUNE ?= "microblaze" - -require conf/machine/include/soc-zynqmp.inc - -# Endianess, multiplier, barrel shift, pattern compare, floating point double or single, are the possibilities -AVAILTUNES += "microblaze" -TUNE_FEATURES_tune-microblaze = "microblaze v11.0 barrel-shift pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblaze = "${TUNE_PKGARCH}" - -LINKER_HASH_STYLE_microblaze = "sysv" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-tc.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-tc.conf deleted file mode 100644 index bc80ad754..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblaze-tc.conf +++ /dev/null @@ -1,541 +0,0 @@ -require conf/multilib.conf -require conf/machine/include/microblaze/arch-microblaze.inc -require conf/machine/include/baremetal-tc.conf - -# ILP request an alternative machine dictionary -INHERIT += "xlnx-standalone" -PACKAGEQA_EXTRA_MACHDEFFUNCS .= '${@bb.utils.contains("TUNE_FEATURES", "64-bit", " xlnx_mb64_dict", "", d)}' - -# GNU hash style not supported -LINKER_HASH_STYLE_microblaze = "" - -# Define all of the multilibs supproted by this configuration -MULTILIB_GLOBAL_VARIANTS = "${@extend_variants(d,'MULTILIBS','multilib')}" - -MULTILIBS += "multilib:libmble" -MULTILIBS += "multilib:libmbbs" -MULTILIBS += "multilib:libmbp" -MULTILIBS += "multilib:libmbm" -MULTILIBS += "multilib:libmbfpd" -MULTILIBS += "multilib:libmbmfpd" -MULTILIBS += "multilib:libmbpm" -MULTILIBS += "multilib:libmbpfpd" -MULTILIBS += "multilib:libmbpmfpd" -MULTILIBS += "multilib:libmbbsp" -MULTILIBS += "multilib:libmbbsm" -MULTILIBS += "multilib:libmbbsfpd" -MULTILIBS += "multilib:libmbbsmfpd" -MULTILIBS += "multilib:libmbbspm" -MULTILIBS += "multilib:libmbbspfpd" -MULTILIBS += "multilib:libmbbspmfpd" -MULTILIBS += "multilib:libmblem64" -MULTILIBS += "multilib:libmblebs" -MULTILIBS += "multilib:libmblep" -MULTILIBS += "multilib:libmblem" -MULTILIBS += "multilib:libmblefpd" -MULTILIBS += "multilib:libmblemfpd" -MULTILIBS += "multilib:libmblepm" -MULTILIBS += "multilib:libmblepfpd" -MULTILIBS += "multilib:libmblepmfpd" -MULTILIBS += "multilib:libmblebsp" -MULTILIBS += "multilib:libmblebsm" -MULTILIBS += "multilib:libmblebsfpd" -MULTILIBS += "multilib:libmblebsmfpd" -MULTILIBS += "multilib:libmblebspm" -MULTILIBS += "multilib:libmblebspfpd" -MULTILIBS += "multilib:libmblebspmfpd" -MULTILIBS += "multilib:libmblem64bs" -MULTILIBS += "multilib:libmblem64p" -MULTILIBS += "multilib:libmblem64m" -MULTILIBS += "multilib:libmblem64fpd" -MULTILIBS += "multilib:libmblem64mfpd" -MULTILIBS += "multilib:libmblem64pm" -MULTILIBS += "multilib:libmblem64pfpd" -MULTILIBS += "multilib:libmblem64pmfpd" -MULTILIBS += "multilib:libmblem64bsp" -MULTILIBS += "multilib:libmblem64bsm" -MULTILIBS += "multilib:libmblem64bsfpd" -MULTILIBS += "multilib:libmblem64bsmfpd" -MULTILIBS += "multilib:libmblem64bspm" -MULTILIBS += "multilib:libmblem64bspfpd" -MULTILIBS += "multilib:libmblem64bspmfpd" - - -# Base configuration -# CFLAGS: -DEFAULTTUNE = "microblaze" - -AVAILTUNES += "microblaze" -BASE_LIB_tune-microblaze = "lib" -TUNE_FEATURES_tune-microblaze = "microblaze bigendian" -PACKAGE_EXTRA_ARCHS_tune-microblaze = "${TUNE_PKGARCH}" - - -# le -# CFLAGS: -mlittle-endian -DEFAULTTUNE_virtclass-multilib-libmble = "microblazele" - -AVAILTUNES += "microblazele" -BASE_LIB_tune-microblazele = "lib/le" -TUNE_FEATURES_tune-microblazele = "microblaze" -PACKAGE_EXTRA_ARCHS_tune-microblazele = "${TUNE_PKGARCH}" - - -# bs -# CFLAGS: -mxl-barrel-shift -DEFAULTTUNE_virtclass-multilib-libmbbs = "microblazebs" - -AVAILTUNES += "microblazebs" -BASE_LIB_tune-microblazebs = "lib/bs" -TUNE_FEATURES_tune-microblazebs = "microblaze bigendian barrel-shift" -PACKAGE_EXTRA_ARCHS_tune-microblazebs = "${TUNE_PKGARCH}" - - -# p -# CFLAGS: -mxl-pattern-compare -DEFAULTTUNE_virtclass-multilib-libmbp = "microblazep" - -AVAILTUNES += "microblazep" -BASE_LIB_tune-microblazep = "lib/p" -TUNE_FEATURES_tune-microblazep = "microblaze bigendian pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblazep = "${TUNE_PKGARCH}" - - -# m -# CFLAGS: -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmbm = "microblazem" - -AVAILTUNES += "microblazem" -BASE_LIB_tune-microblazem = "lib/m" -TUNE_FEATURES_tune-microblazem = "microblaze bigendian multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazem = "${TUNE_PKGARCH}" - - -# fpd -# CFLAGS: -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbfpd = "microblazefpd" - -AVAILTUNES += "microblazefpd" -BASE_LIB_tune-microblazefpd = "lib/fpd" -TUNE_FEATURES_tune-microblazefpd = "microblaze bigendian fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazefpd = "${TUNE_PKGARCH}" - - -# m/fpd -# CFLAGS: -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbmfpd = "microblazemfpd" - -AVAILTUNES += "microblazemfpd" -BASE_LIB_tune-microblazemfpd = "lib/m/fpd" -TUNE_FEATURES_tune-microblazemfpd = "microblaze bigendian multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazemfpd = "${TUNE_PKGARCH}" - - -# p/m -# CFLAGS: -mxl-pattern-compare -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmbpm = "microblazepm" - -AVAILTUNES += "microblazepm" -BASE_LIB_tune-microblazepm = "lib/p/m" -TUNE_FEATURES_tune-microblazepm = "microblaze bigendian pattern-compare multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazepm = "${TUNE_PKGARCH}" - - -# p/fpd -# CFLAGS: -mxl-pattern-compare -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbpfpd = "microblazepfpd" - -AVAILTUNES += "microblazepfpd" -BASE_LIB_tune-microblazepfpd = "lib/p/fpd" -TUNE_FEATURES_tune-microblazepfpd = "microblaze bigendian pattern-compare fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazepfpd = "${TUNE_PKGARCH}" - - -# p/m/fpd -# CFLAGS: -mxl-pattern-compare -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbpmfpd = "microblazepmfpd" - -AVAILTUNES += "microblazepmfpd" -BASE_LIB_tune-microblazepmfpd = "lib/p/m/fpd" -TUNE_FEATURES_tune-microblazepmfpd = "microblaze bigendian pattern-compare multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazepmfpd = "${TUNE_PKGARCH}" - - -# bs/p -# CFLAGS: -mxl-barrel-shift -mxl-pattern-compare -DEFAULTTUNE_virtclass-multilib-libmbbsp = "microblazebsp" - -AVAILTUNES += "microblazebsp" -BASE_LIB_tune-microblazebsp = "lib/bs/p" -TUNE_FEATURES_tune-microblazebsp = "microblaze bigendian barrel-shift pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblazebsp = "${TUNE_PKGARCH}" - - -# bs/m -# CFLAGS: -mxl-barrel-shift -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmbbsm = "microblazebsm" - -AVAILTUNES += "microblazebsm" -BASE_LIB_tune-microblazebsm = "lib/bs/m" -TUNE_FEATURES_tune-microblazebsm = "microblaze bigendian barrel-shift multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazebsm = "${TUNE_PKGARCH}" - - -# bs/fpd -# CFLAGS: -mxl-barrel-shift -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbbsfpd = "microblazebsfpd" - -AVAILTUNES += "microblazebsfpd" -BASE_LIB_tune-microblazebsfpd = "lib/bs/fpd" -TUNE_FEATURES_tune-microblazebsfpd = "microblaze bigendian barrel-shift fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazebsfpd = "${TUNE_PKGARCH}" - - -# bs/m/fpd -# CFLAGS: -mxl-barrel-shift -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbbsmfpd = "microblazebsmfpd" - -AVAILTUNES += "microblazebsmfpd" -BASE_LIB_tune-microblazebsmfpd = "lib/bs/m/fpd" -TUNE_FEATURES_tune-microblazebsmfpd = "microblaze bigendian barrel-shift multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazebsmfpd = "${TUNE_PKGARCH}" - - -# bs/p/m -# CFLAGS: -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmbbspm = "microblazebspm" - -AVAILTUNES += "microblazebspm" -BASE_LIB_tune-microblazebspm = "lib/bs/p/m" -TUNE_FEATURES_tune-microblazebspm = "microblaze bigendian barrel-shift pattern-compare multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazebspm = "${TUNE_PKGARCH}" - - -# bs/p/fpd -# CFLAGS: -mxl-barrel-shift -mxl-pattern-compare -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbbspfpd = "microblazebspfpd" - -AVAILTUNES += "microblazebspfpd" -BASE_LIB_tune-microblazebspfpd = "lib/bs/p/fpd" -TUNE_FEATURES_tune-microblazebspfpd = "microblaze bigendian barrel-shift pattern-compare fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazebspfpd = "${TUNE_PKGARCH}" - - -# bs/p/m/fpd -# CFLAGS: -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmbbspmfpd = "microblazebspmfpd" - -AVAILTUNES += "microblazebspmfpd" -BASE_LIB_tune-microblazebspmfpd = "lib/bs/p/m/fpd" -TUNE_FEATURES_tune-microblazebspmfpd = "microblaze bigendian barrel-shift pattern-compare multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazebspmfpd = "${TUNE_PKGARCH}" - - -# le/m64 -# CFLAGS: -mlittle-endian -m64 -DEFAULTTUNE_virtclass-multilib-libmblem64 = "microblazele64" - -AVAILTUNES += "microblazele64" -BASE_LIB_tune-microblazele64 = "lib/le/m64" -TUNE_FEATURES_tune-microblazele64 = "microblaze 64-bit" -PACKAGE_EXTRA_ARCHS_tune-microblazele64 = "${TUNE_PKGARCH}" - - -# le/bs -# CFLAGS: -mlittle-endian -mxl-barrel-shift -DEFAULTTUNE_virtclass-multilib-libmblebs = "microblazelebs" - -AVAILTUNES += "microblazelebs" -BASE_LIB_tune-microblazelebs = "lib/le/bs" -TUNE_FEATURES_tune-microblazelebs = "microblaze barrel-shift" -PACKAGE_EXTRA_ARCHS_tune-microblazelebs = "${TUNE_PKGARCH}" - - -# le/p -# CFLAGS: -mlittle-endian -mxl-pattern-compare -DEFAULTTUNE_virtclass-multilib-libmblep = "microblazelep" - -AVAILTUNES += "microblazelep" -BASE_LIB_tune-microblazelep = "lib/le/p" -TUNE_FEATURES_tune-microblazelep = "microblaze pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblazelep = "${TUNE_PKGARCH}" - - -# le/m -# CFLAGS: -mlittle-endian -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblem = "microblazelem" - -AVAILTUNES += "microblazelem" -BASE_LIB_tune-microblazelem = "lib/le/m" -TUNE_FEATURES_tune-microblazelem = "microblaze multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazelem = "${TUNE_PKGARCH}" - - -# le/fpd -# CFLAGS: -mlittle-endian -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblefpd = "microblazelefpd" - -AVAILTUNES += "microblazelefpd" -BASE_LIB_tune-microblazelefpd = "lib/le/fpd" -TUNE_FEATURES_tune-microblazelefpd = "microblaze fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelefpd = "${TUNE_PKGARCH}" - - -# le/m/fpd -# CFLAGS: -mlittle-endian -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblemfpd = "microblazelemfpd" - -AVAILTUNES += "microblazelemfpd" -BASE_LIB_tune-microblazelemfpd = "lib/le/m/fpd" -TUNE_FEATURES_tune-microblazelemfpd = "microblaze multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelemfpd = "${TUNE_PKGARCH}" - - -# le/p/m -# CFLAGS: -mlittle-endian -mxl-pattern-compare -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblepm = "microblazelepm" - -AVAILTUNES += "microblazelepm" -BASE_LIB_tune-microblazelepm = "lib/le/p/m" -TUNE_FEATURES_tune-microblazelepm = "microblaze pattern-compare multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazelepm = "${TUNE_PKGARCH}" - - -# le/p/fpd -# CFLAGS: -mlittle-endian -mxl-pattern-compare -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblepfpd = "microblazelepfpd" - -AVAILTUNES += "microblazelepfpd" -BASE_LIB_tune-microblazelepfpd = "lib/le/p/fpd" -TUNE_FEATURES_tune-microblazelepfpd = "microblaze pattern-compare fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelepfpd = "${TUNE_PKGARCH}" - - -# le/p/m/fpd -# CFLAGS: -mlittle-endian -mxl-pattern-compare -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblepmfpd = "microblazelepmfpd" - -AVAILTUNES += "microblazelepmfpd" -BASE_LIB_tune-microblazelepmfpd = "lib/le/p/m/fpd" -TUNE_FEATURES_tune-microblazelepmfpd = "microblaze pattern-compare multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelepmfpd = "${TUNE_PKGARCH}" - - -# le/bs/p -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -DEFAULTTUNE_virtclass-multilib-libmblebsp = "microblazelebsp" - -AVAILTUNES += "microblazelebsp" -BASE_LIB_tune-microblazelebsp = "lib/le/bs/p" -TUNE_FEATURES_tune-microblazelebsp = "microblaze barrel-shift pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblazelebsp = "${TUNE_PKGARCH}" - - -# le/bs/m -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblebsm = "microblazelebsm" - -AVAILTUNES += "microblazelebsm" -BASE_LIB_tune-microblazelebsm = "lib/le/bs/m" -TUNE_FEATURES_tune-microblazelebsm = "microblaze barrel-shift multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazelebsm = "${TUNE_PKGARCH}" - - -# le/bs/fpd -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblebsfpd = "microblazelebsfpd" - -AVAILTUNES += "microblazelebsfpd" -BASE_LIB_tune-microblazelebsfpd = "lib/le/bs/fpd" -TUNE_FEATURES_tune-microblazelebsfpd = "microblaze barrel-shift fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelebsfpd = "${TUNE_PKGARCH}" - - -# le/bs/m/fpd -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblebsmfpd = "microblazelebsmfpd" - -AVAILTUNES += "microblazelebsmfpd" -BASE_LIB_tune-microblazelebsmfpd = "lib/le/bs/m/fpd" -TUNE_FEATURES_tune-microblazelebsmfpd = "microblaze barrel-shift multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelebsmfpd = "${TUNE_PKGARCH}" - - -# le/bs/p/m -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblebspm = "microblazelebspm" - -AVAILTUNES += "microblazelebspm" -BASE_LIB_tune-microblazelebspm = "lib/le/bs/p/m" -TUNE_FEATURES_tune-microblazelebspm = "microblaze barrel-shift pattern-compare multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazelebspm = "${TUNE_PKGARCH}" - - -# le/bs/p/fpd -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblebspfpd = "microblazelebspfpd" - -AVAILTUNES += "microblazelebspfpd" -BASE_LIB_tune-microblazelebspfpd = "lib/le/bs/p/fpd" -TUNE_FEATURES_tune-microblazelebspfpd = "microblaze barrel-shift pattern-compare fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelebspfpd = "${TUNE_PKGARCH}" - - -# le/bs/p/m/fpd -# CFLAGS: -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblebspmfpd = "microblazelebspmfpd" - -AVAILTUNES += "microblazelebspmfpd" -BASE_LIB_tune-microblazelebspmfpd = "lib/le/bs/p/m/fpd" -TUNE_FEATURES_tune-microblazelebspmfpd = "microblaze barrel-shift pattern-compare multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazelebspmfpd = "${TUNE_PKGARCH}" - - -# le/m64/bs -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -DEFAULTTUNE_virtclass-multilib-libmblem64bs = "microblazele64bs" - -AVAILTUNES += "microblazele64bs" -BASE_LIB_tune-microblazele64bs = "lib/le/m64/bs" -TUNE_FEATURES_tune-microblazele64bs = "microblaze 64-bit barrel-shift" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bs = "${TUNE_PKGARCH}" - - -# le/m64/p -# CFLAGS: -mlittle-endian -m64 -mxl-pattern-compare -DEFAULTTUNE_virtclass-multilib-libmblem64p = "microblazele64p" - -AVAILTUNES += "microblazele64p" -BASE_LIB_tune-microblazele64p = "lib/le/m64/p" -TUNE_FEATURES_tune-microblazele64p = "microblaze 64-bit pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblazele64p = "${TUNE_PKGARCH}" - - -# le/m64/m -# CFLAGS: -mlittle-endian -m64 -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblem64m = "microblazele64m" - -AVAILTUNES += "microblazele64m" -BASE_LIB_tune-microblazele64m = "lib/le/m64/m" -TUNE_FEATURES_tune-microblazele64m = "microblaze 64-bit multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazele64m = "${TUNE_PKGARCH}" - - -# le/m64/fpd -# CFLAGS: -mlittle-endian -m64 -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64fpd = "microblazele64fpd" - -AVAILTUNES += "microblazele64fpd" -BASE_LIB_tune-microblazele64fpd = "lib/le/m64/fpd" -TUNE_FEATURES_tune-microblazele64fpd = "microblaze 64-bit fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64fpd = "${TUNE_PKGARCH}" - - -# le/m64/m/fpd -# CFLAGS: -mlittle-endian -m64 -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64mfpd = "microblazele64mfpd" - -AVAILTUNES += "microblazele64mfpd" -BASE_LIB_tune-microblazele64mfpd = "lib/le/m64/m/fpd" -TUNE_FEATURES_tune-microblazele64mfpd = "microblaze 64-bit multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64mfpd = "${TUNE_PKGARCH}" - - -# le/m64/p/m -# CFLAGS: -mlittle-endian -m64 -mxl-pattern-compare -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblem64pm = "microblazele64pm" - -AVAILTUNES += "microblazele64pm" -BASE_LIB_tune-microblazele64pm = "lib/le/m64/p/m" -TUNE_FEATURES_tune-microblazele64pm = "microblaze 64-bit pattern-compare multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazele64pm = "${TUNE_PKGARCH}" - - -# le/m64/p/fpd -# CFLAGS: -mlittle-endian -m64 -mxl-pattern-compare -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64pfpd = "microblazele64pfpd" - -AVAILTUNES += "microblazele64pfpd" -BASE_LIB_tune-microblazele64pfpd = "lib/le/m64/p/fpd" -TUNE_FEATURES_tune-microblazele64pfpd = "microblaze 64-bit pattern-compare fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64pfpd = "${TUNE_PKGARCH}" - - -# le/m64/p/m/fpd -# CFLAGS: -mlittle-endian -m64 -mxl-pattern-compare -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64pmfpd = "microblazele64pmfpd" - -AVAILTUNES += "microblazele64pmfpd" -BASE_LIB_tune-microblazele64pmfpd = "lib/le/m64/p/m/fpd" -TUNE_FEATURES_tune-microblazele64pmfpd = "microblaze 64-bit pattern-compare multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64pmfpd = "${TUNE_PKGARCH}" - - -# le/m64/bs/p -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mxl-pattern-compare -DEFAULTTUNE_virtclass-multilib-libmblem64bsp = "microblazele64bsp" - -AVAILTUNES += "microblazele64bsp" -BASE_LIB_tune-microblazele64bsp = "lib/le/m64/bs/p" -TUNE_FEATURES_tune-microblazele64bsp = "microblaze 64-bit barrel-shift pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bsp = "${TUNE_PKGARCH}" - - -# le/m64/bs/m -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblem64bsm = "microblazele64bsm" - -AVAILTUNES += "microblazele64bsm" -BASE_LIB_tune-microblazele64bsm = "lib/le/m64/bs/m" -TUNE_FEATURES_tune-microblazele64bsm = "microblaze 64-bit barrel-shift multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bsm = "${TUNE_PKGARCH}" - - -# le/m64/bs/fpd -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64bsfpd = "microblazele64bsfpd" - -AVAILTUNES += "microblazele64bsfpd" -BASE_LIB_tune-microblazele64bsfpd = "lib/le/m64/bs/fpd" -TUNE_FEATURES_tune-microblazele64bsfpd = "microblaze 64-bit barrel-shift fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bsfpd = "${TUNE_PKGARCH}" - - -# le/m64/bs/m/fpd -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64bsmfpd = "microblazele64bsmfpd" - -AVAILTUNES += "microblazele64bsmfpd" -BASE_LIB_tune-microblazele64bsmfpd = "lib/le/m64/bs/m/fpd" -TUNE_FEATURES_tune-microblazele64bsmfpd = "microblaze 64-bit barrel-shift multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bsmfpd = "${TUNE_PKGARCH}" - - -# le/m64/bs/p/m -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-mul -DEFAULTTUNE_virtclass-multilib-libmblem64bspm = "microblazele64bspm" - -AVAILTUNES += "microblazele64bspm" -BASE_LIB_tune-microblazele64bspm = "lib/le/m64/bs/p/m" -TUNE_FEATURES_tune-microblazele64bspm = "microblaze 64-bit barrel-shift pattern-compare multiply-low" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bspm = "${TUNE_PKGARCH}" - - -# le/m64/bs/p/fpd -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mxl-pattern-compare -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64bspfpd = "microblazele64bspfpd" - -AVAILTUNES += "microblazele64bspfpd" -BASE_LIB_tune-microblazele64bspfpd = "lib/le/m64/bs/p/fpd" -TUNE_FEATURES_tune-microblazele64bspfpd = "microblaze 64-bit barrel-shift pattern-compare fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bspfpd = "${TUNE_PKGARCH}" - - -# le/m64/bs/p/m/fpd -# CFLAGS: -mlittle-endian -m64 -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-mul -mhard-float -DEFAULTTUNE_virtclass-multilib-libmblem64bspmfpd = "microblazele64bspmfpd" - -AVAILTUNES += "microblazele64bspmfpd" -BASE_LIB_tune-microblazele64bspmfpd = "lib/le/m64/bs/p/m/fpd" -TUNE_FEATURES_tune-microblazele64bspmfpd = "microblaze 64-bit barrel-shift pattern-compare multiply-low fpu-hard" -PACKAGE_EXTRA_ARCHS_tune-microblazele64bspmfpd = "${TUNE_PKGARCH}" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblazeel-v11.0-bs-cmp-mh-div-generic.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microblazeel-v11.0-bs-cmp-mh-div-generic.conf deleted file mode 100644 index ed4e2acb6..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblazeel-v11.0-bs-cmp-mh-div-generic.conf +++ /dev/null @@ -1,17 +0,0 @@ -#@TYPE: Machine -#@NAME: microblazeel-v11.0-bs-cmp-mh-div-generic -#@DESCRIPTION: microblazeel-v11.0-bs-cmp-mh-div - -require conf/machine/include/tune-microblaze.inc -require conf/machine/include/machine-xilinx-default.inc - -TUNE_FEATURES_tune-microblaze += "v11.0 barrel-shift pattern-compare reorder divide-hard multiply-high" - -MACHINE_FEATURES = "" - -KERNEL_IMAGETYPE = "linux.bin.ub" -KERNEL_IMAGETYPES = "" - -SERIAL_CONSOLES ?= "115200;ttyS0" - -EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblazeel-v11.0-bs-cmp-ml-generic.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microblazeel-v11.0-bs-cmp-ml-generic.conf deleted file mode 100644 index f154197ac..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/microblazeel-v11.0-bs-cmp-ml-generic.conf +++ /dev/null @@ -1,17 +0,0 @@ -#@TYPE: Machine -#@NAME: microblazeel-v11.0-bs-cmp-ml-generic -#@DESCRIPTION: microblazeel-v11.0-bs-cmp-ml - -require conf/machine/include/tune-microblaze.inc -require conf/machine/include/machine-xilinx-default.inc - -TUNE_FEATURES_tune-microblaze += "v11.0 barrel-shift reorder pattern-compare multiply-low" - -MACHINE_FEATURES = "" - -KERNEL_IMAGETYPE = "linux.bin.ub" -KERNEL_IMAGETYPES = "" - -SERIAL_CONSOLES ?= "115200;ttyS0" - -EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf deleted file mode 100644 index c531dbb2e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf +++ /dev/null @@ -1,31 +0,0 @@ -#@TYPE: Machine -#@NAME: microzed-zynq7 -#@DESCRIPTION: Machine support for microZed. (http://www.microzed.org/) - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "ext2 vfat usbhost" - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "zynq-microzed.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf deleted file mode 100644 index 3e5d623fd..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf +++ /dev/null @@ -1,27 +0,0 @@ -#@TYPE: Machine -#@NAME: ml605-qemu-microblazeel -#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-ml605' model) - -require conf/machine/include/tune-microblaze.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -TUNE_FEATURES_tune-microblaze += "v8.50 barrel-shift reorder pattern-compare divide-hard multiply-high fpu-hard" - -MACHINE_FEATURES = "" - -USE_VT = "" -SERIAL_CONSOLES ?= "115200;ttyS0" - -KERNEL_IMAGETYPE ?= "linux.bin.ub" - -# Use the networking setup from qemuarm -MACHINEOVERRIDES_prepend_pn-init-ifupdown = "qemuall:" -FILESOVERRIDES_append_pn-init-ifupdown = ":qemuarm" - -# This machine is a targeting a QEMU model, runqemu setup: -QB_MEM = "-m 256" -QB_MACHINE = "-machine petalogix-ml605" -QB_OPT_APPEND = "-nographic -serial mon:stdio" -QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf deleted file mode 100644 index 17e83334b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf +++ /dev/null @@ -1,35 +0,0 @@ -#@TYPE: Machine -#@NAME: picozed-zynq7 -#@DESCRIPTION: Machine support for picoZed. (http://www.picozed.org/) -# -# Note: This machine configuration is intended as a generic config for -# the picozed SOM. It also covers the multiple SKUs for the picoZed -# including 7010, 7020, 7015 and 7030. - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "ext2 vfat usbhost usbgadget" - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf deleted file mode 100644 index 8bccfde29..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf +++ /dev/null @@ -1,40 +0,0 @@ -#@TYPE: Machine -#@NAME: qemu-zynq7 -#@DESCRIPTION: Zynq QEMU machine support ('xilinx-zynq-a9' model) - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -MACHINE_FEATURES = "ext2 vfat" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -HDF_MACHINE = "zc702-zynq7" - -# Use the networking setup from qemuarm -MACHINEOVERRIDES_prepend_pn-init-ifupdown = "qemuall:" -FILESOVERRIDES_append_pn-init-ifupdown = ":qemuarm" - -QB_MEM = "-m 1024" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=/tftpboot -net nic" -QB_DEFAULT_KERNEL_qemuboot-xilinx = "zImage" - -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE = "cpio.gz.u-boot" -QB_DTB = "system.dtb" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND = " \ - -nographic -serial null -serial mon:stdio \ - -initrd ${DEPLOY_DIR_IMAGE}/petalinux-image-minimal-qemu-zynq7.cpio.gz.u-boot \ - -gdb tcp::9000 \ - -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 \ - -device loader,addr=0xf8000140,data=0x00500801,data-len=4 \ - -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 \ - -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 \ - -device loader,addr=0xF8000910,data=0xF,data-len=0x4 \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf deleted file mode 100644 index 1ce632910..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf +++ /dev/null @@ -1,23 +0,0 @@ -#@TYPE: Machine -#@NAME: s3adsp1800-qemu-microblazeeb -#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-s3adsp1800' model) - -require conf/machine/include/tune-microblaze.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -TUNE_FEATURES_tune-microblaze += "v8.00 bigendian barrel-shift pattern-compare multiply-low" - -MACHINE_FEATURES = "" - -USE_VT = "" -SERIAL_CONSOLES ?= "115200;ttyUL0" - -KERNEL_IMAGETYPE ?= "linux.bin.ub" - -# This machine is a targeting a QEMU model, runqemu setup: -QB_MEM = "-m 256" -QB_MACHINE = "-machine petalogix-s3adsp1800" -QB_OPT_APPEND = "-nographic -serial mon:stdio" -QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/system-zcu102.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/system-zcu102.conf deleted file mode 100644 index 5d3bbd286..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/system-zcu102.conf +++ /dev/null @@ -1,61 +0,0 @@ -#@TYPE: Machine -#@NAME: system-zcu102 -#@DESCRIPTION: Machine supporting the architectures in the ZCU102 evaluation board. - -# This machine sets up a build for a heterogeneous architecture board. -# In this specific case, this refers to a zcu102-zynqmp board, which -# should build artifacts for the hard microblaze architecture, and the -# cortex-a53. - -# This is meant to be used as a base case and adapting it to -# other boards should be fairly simple. - -# To build a full system, simply invoke the command: -# $ bitbake <image> -# which is analogous to -# $ bitbake mc::<image> -# Where image can be core-image-minimal for example -# If a user wants to build a package for a certain architecture -# a similar command can be invoked, just changing the parameter -# between : and : to the desired multiconfig from one of the -# declared values below. -# For example, to build the xilstandalone library for the microblaze: -# $ bitbake mc:pmumc:xilstandalone -# or to build fsbl for cortexa53: -# $ bitbake mc:fsblmc:zyqmp-fsbl - - -# These artifacts are the pmu firmware along with the fsbl and the -# Linux OS respectively - -# Keep in mind that there would still be a wiring required to merge -# the artifacts from their respective deploy directories using bootgen. -BBMULTICONFIG = "fsblmc pmumc" - -# The following should be changed to the machine which corresponds to -# the architecture of a specific device, in this case cortexa53 -# But there are several hard coded expected values from several -# repos, e.g. linux-xlnx which expects a defconfig depending on -# the machine that is being used, as a TEMPORARY solution and -# to prove how multiconfig can be used to build a full system -# with heterogeneous architectures we'll use MACHINE=zcu102-zynqmp. - -# The downside is that this stills needs xsct and would technically -# build two pmu firmwrares and two fsbls, one coming from our -# multiconfig and one that uses xsct respectively, once the values -# mentioned above are fixed, this should work properly with: -# MACHINE = "cortexa53-zynqmp" - -MACHINE = "zcu102-zynqmp" -require conf/machine/${MACHINE}.conf - -# Use the same format for TMPDIR as in the other multiconfigs so its less confusing. -TMPDIR = "${TOPDIR}/tmp-${MACHINE}-${TCLIBC}" - -# Create dependencies for Linux only, other multiconfig applications, -# can be built separately, e.g. bitbake mc:pmumc:pmufw -# in this case, linux cannot, also worth mentioning that these should -# eventually be set on a recipe level and would probably be useful to -# create a chain of dependencies: pmufw<-fsbl<-Linux -do_image[mcdepends] += "multiconfig::fsblmc:zynqmp-fsbl:do_deploy" -do_image[mcdepends] += "multiconfig::pmumc:pmufw:do_deploy"
\ No newline at end of file diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf deleted file mode 100644 index f31c10cf2..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf +++ /dev/null @@ -1,38 +0,0 @@ -#@TYPE: Machine -#@NAME: ultra96-zynqmp -#@DESCRIPTION: Machine support for Ultra96 Evaluation Board. -# - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/xilinx-board.inc - -BOARD = "ultra96" - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost usbgadget wifi bluetooth mipi" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu100-revC.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " -MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "linux-firmware-wl18xx" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/v350-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/v350-versal.conf deleted file mode 100644 index 6741e2f32..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/v350-versal.conf +++ /dev/null @@ -1,29 +0,0 @@ -#@TYPE: Machine -#@NAME: v350-versal -##@DESCRIPTION: Machine support for v350 versal. - -require conf/machine/include/soc-versal.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyAMA0" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ -" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - Image \ - boot.scr \ -" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf deleted file mode 100644 index bbc068874..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf +++ /dev/null @@ -1,72 +0,0 @@ -#@TYPE: Machine -#@NAME: vc-p-a2197-versal -##@DESCRIPTION: Machine support for vc-p-a2197 versal . - -require conf/machine/include/soc-versal.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -SOC_VARIANT = "-ai-core" - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyAMA0" - -# Default SD image build onfiguration, use qemu-sd to pad -IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" -WKS_FILES ?= "sdimage-bootpart.wks" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ - qemu-devicetrees \ - virtual/cdo \ -" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - system.dtb \ - Image \ - boot.scr \ -" -# This machine has a QEMU model, runqemu setup: -QB_MEM = "-m 8G" -QB_DEFAULT_KERNEL = "none" -QB_NETWORK_DEVICE = "" -QB_KERNEL_CMDLINE_APPEND ?= "" -QB_NET = "none" - -QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Use booti 80000 6000000 4000000 to launch -QB_OPT_APPEND ?= " -serial null -serial null -serial mon:stdio -display none" - -QB_OPT_APPEND_append_qemuboot-xilinx = " \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-ps-vc-p-a2197-00.dtb \ - -display none \ - -net nic -net user,tftp=${DEPLOY_DIR_IMAGE} \ - " -# PLM instance args -QB_PLM_OPT = " \ - -M microblaze-fdt \ - -device loader,file=${DEPLOY_DIR_IMAGE}/BOOT-${MACHINE}_bh.bin,addr=0xF201E000,force-raw \ - -device loader,addr=0xf0000000,data=0xba020004,data-len=4 \ - -device loader,addr=0xf0000004,data=0xb800fffc,data-len=4 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/CDO/pmc_cdo.bin,addr=0xf2000000,force-raw \ - -device loader,file=${DEPLOY_DIR_IMAGE}/plm-${MACHINE}.elf,cpu-num=1 \ - -device loader,addr=0xF1110624,data=0x0,data-len=4 \ - -device loader,addr=0xF1110620,data=0x1,data-len=4 \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-pmc-vc-p-a2197-00.dtb \ - -display none \ - " -QB_OPT_APPEND_append_qemuboot-xilinx = " -plm-args '${QB_PLM_OPT}'" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/vck-sc-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/vck-sc-zynqmp.conf deleted file mode 100644 index 6a453a2cb..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/vck-sc-zynqmp.conf +++ /dev/null @@ -1,32 +0,0 @@ -#@TYPE: Machine -#@NAME: vck-sc-zynqmp -##@DESCRIPTION: Machine support for vck190 system controller. - - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE ?= "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -# PMU instance args -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ -" -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ -" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/vck190-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/vck190-versal.conf deleted file mode 100644 index 1ab6a1c75..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/vck190-versal.conf +++ /dev/null @@ -1,78 +0,0 @@ -#@TYPE: Machine -#@NAME: vck-versal -##@DESCRIPTION: Machine support for vck-versal . - -require conf/machine/include/soc-versal.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -SOC_VARIANT = "-ai-core" - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyAMA0" - -# Default SD image build onfiguration, use qemu-sd to pad -IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" -WKS_FILES ?= "sdimage-bootpart.wks" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ - qemu-devicetrees \ - virtual/cdo \ -" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - Image \ - boot.scr \ -" -PLM_DEPLOY_DIR ?= "{TOPDIR}/versalmbtmp/deploy/images/versal-mb" -PLM_IMAGE_NAME ?= "plm-versal-mb" -PSM_FIRMWARE_DEPLOY_DIR ?= "{TOPDIR}/versalmbtmp/deploy/images/versal-mb" -PSM_FIRMWARE_IMAGE_NAME ?= "psm-firmware-versal-mb" - - -# This machine has a QEMU model, runqemu setup: -QB_MEM = "-m 8G" -QB_DEFAULT_KERNEL = "none" -QB_NETWORK_DEVICE = "" -QB_KERNEL_CMDLINE_APPEND ?= "" -QB_NET = "none" - -QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Use booti 80000 6000000 4000000 to launch -QB_OPT_APPEND ?= " -serial null -serial null -serial mon:stdio -display none" - -QB_OPT_APPEND_append_qemuboot-xilinx = " \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-ps-vc-p-a2197-00.dtb \ - -display none \ - -net nic -net user,tftp=${DEPLOY_DIR_IMAGE} \ - " - -# PLM instance args -QB_PLM_OPT = " \ - -M microblaze-fdt \ - -device loader,file=${DEPLOY_DIR_IMAGE}/BOOT-${MACHINE}_bh.bin,addr=0xF201E000,force-raw \ - -device loader,addr=0xf0000000,data=0xba020004,data-len=4 \ - -device loader,addr=0xf0000004,data=0xb800fffc,data-len=4 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/CDO/pmc_cdo.bin,addr=0xf2000000,force-raw \ - -device loader,file=${DEPLOY_DIR_IMAGE}/plm-${MACHINE}.elf,cpu-num=1 \ - -device loader,addr=0xF1110624,data=0x0,data-len=4 \ - -device loader,addr=0xF1110620,data=0x1,data-len=4 \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-pmc-vc-p-a2197-00.dtb \ - -display none \ - " -QB_OPT_APPEND_append_qemuboot-xilinx = " -plm-args '${QB_PLM_OPT}'" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/vck5000-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/vck5000-versal.conf deleted file mode 100644 index 97fb9cc78..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/vck5000-versal.conf +++ /dev/null @@ -1,29 +0,0 @@ -#@TYPE: Machine -#@NAME: vck500-versal -##@DESCRIPTION: Machine support for vck5000 versal. - -require conf/machine/include/soc-versal.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyAMA0" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ -" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - Image \ - boot.scr \ -" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/versal-generic.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/versal-generic.conf deleted file mode 100644 index dd6966a0a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/versal-generic.conf +++ /dev/null @@ -1,83 +0,0 @@ -#@TYPE: Machine -#@NAME: Generic versal -#@DESCRIPTION: versal devices - -require conf/machine/include/soc-versal.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc -require conf/machine/include/xilinx-board.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" - -UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyAMA0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -# Default SD image build onfiguration, use qemu-sd to pad -IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" -WKS_FILES ?= "sdimage-bootpart.wks" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ - qemu-devicetrees \ - virtual/cdo \ -" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - Image \ - boot.scr \ -" -PLM_DEPLOY_DIR ?= "{TOPDIR}/versalmbtmp/deploy/images/versal-mb" -PLM_IMAGE_NAME ?= "plm-versal-mb" -PSM_FIRMWARE_DEPLOY_DIR ?= "{TOPDIR}/versalmbtmp/deploy/images/versal-mb" -PSM_FIRMWARE_IMAGE_NAME ?= "psm-firmware-versal-mb" - -# We use the vc-p-a2197-00-versal DTB from the external-hdf. -HDF_MACHINE = "vc-p-a2197-00-versal" - -# This machine has a QEMU model, runqemu setup: -QB_MEM = "-m 8G" -QB_DEFAULT_KERNEL = "none" -QB_NETWORK_DEVICE = "" -QB_KERNEL_CMDLINE_APPEND ?= "" -QB_NET = "none" - -QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Use booti 80000 6000000 4000000 to launch -QB_OPT_APPEND ?= " -serial null -serial null -serial mon:stdio -display none" - -QB_OPT_APPEND_append_qemuboot-xilinx = " \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-ps-vc-p-a2197-00.dtb \ - -display none \ - -net nic -net user,tftp=${DEPLOY_DIR_IMAGE} \ - " - -# PLM instance args -QB_PLM_OPT = " \ - -M microblaze-fdt \ - -device loader,file=${DEPLOY_DIR_IMAGE}/BOOT-${MACHINE}_bh.bin,addr=0xF201E000,force-raw \ - -device loader,addr=0xf0000000,data=0xba020004,data-len=4 \ - -device loader,addr=0xf0000004,data=0xb800fffc,data-len=4 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/CDO/pmc_cdo.bin,addr=0xf2000000,force-raw \ - -device loader,file=${DEPLOY_DIR_IMAGE}/plm-${MACHINE}.elf,cpu-num=1 \ - -device loader,addr=0xF1110624,data=0x0,data-len=4 \ - -device loader,addr=0xF1110620,data=0x1,data-len=4 \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-pmc-vc-p-a2197-00.dtb \ - -display none \ - " -QB_OPT_APPEND_append_qemuboot-xilinx = " -plm-args '${QB_PLM_OPT}'" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/versal-mb.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/versal-mb.conf deleted file mode 100644 index f40b8bca8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/versal-mb.conf +++ /dev/null @@ -1,10 +0,0 @@ -DEFAULTTUNE ?= "microblaze" - -require conf/machine/include/soc-versal.inc - -# Endianess, multiplier, barrel shift, pattern compare, floating point double or single, are the possibilities -AVAILTUNES += "microblaze" -TUNE_FEATURES_tune-microblaze = "microblaze v11.0 barrel-shift pattern-compare" -PACKAGE_EXTRA_ARCHS_tune-microblaze = "${TUNE_PKGARCH}" - -LINKER_HASH_STYLE_microblaze = "" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/vmk180-versal.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/vmk180-versal.conf deleted file mode 100644 index e9044ba7f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/vmk180-versal.conf +++ /dev/null @@ -1,70 +0,0 @@ -#@TYPE: Machine -#@NAME: vmk180-versal -##@DESCRIPTION: Machine support for vmk180-versal . - -require conf/machine/include/soc-versal.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyAMA0" - -IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" -WKS_FILES ?= "sdimage-bootpart.wks" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ - qemu-devicetrees \ - virtual/cdo \ -" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - Image \ - boot.scr \ -" - -# This machine has a QEMU model, runqemu setup: -QB_MEM = "-m 8G" -QB_DEFAULT_KERNEL = "none" -QB_NETWORK_DEVICE = "" -QB_KERNEL_CMDLINE_APPEND ?= "" -QB_NET = "none" - -QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Use booti 80000 6000000 4000000 to launch -QB_OPT_APPEND ?= " -serial null -serial null -serial mon:stdio -display none" - -QB_OPT_APPEND_append_qemuboot-xilinx = " \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-ps-vc-p-a2197-00.dtb \ - -display none \ - -net nic -net user,tftp=${DEPLOY_DIR_IMAGE} \ - " - -# PLM instance args -QB_PLM_OPT = " \ - -M microblaze-fdt \ - -device loader,file=${DEPLOY_DIR_IMAGE}/BOOT-${MACHINE}_bh.bin,addr=0xF201E000,force-raw \ - -device loader,addr=0xf0000000,data=0xba020004,data-len=4 \ - -device loader,addr=0xf0000004,data=0xb800fffc,data-len=4 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/CDO/pmc_cdo.bin,addr=0xf2000000,force-raw \ - -device loader,file=${DEPLOY_DIR_IMAGE}/plm-${MACHINE}.elf,cpu-num=1 \ - -device loader,addr=0xF1110624,data=0x0,data-len=4 \ - -device loader,addr=0xF1110620,data=0x1,data-len=4 \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/board-versal-pmc-vc-p-a2197-00.dtb \ - -display none \ - " -QB_OPT_APPEND_append_qemuboot-xilinx = " -plm-args '${QB_PLM_OPT}'" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1254-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1254-zynqmp.conf deleted file mode 100644 index 3bdb215d0..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1254-zynqmp.conf +++ /dev/null @@ -1,35 +0,0 @@ -#@TYPE: Machine -#@NAME: zc1254-zynqmp -#@DESCRIPTION: Machine support for ZC1254 Evaluation Board. -# - -SOC_VARIANT ?= "dr" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -KERNEL_DEVICETREE = "xilinx/zynqmp-zc1254-revA.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc702-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc702-zynq7.conf deleted file mode 100644 index edd3cb2d4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc702-zynq7.conf +++ /dev/null @@ -1,58 +0,0 @@ -#@TYPE: Machine -#@NAME: zc702-zynq7 -#@DESCRIPTION: Machine support for ZC702 Evaluation Board. -# -# For details on the Evaluation board: -# http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm -# For documentation and design files for the ZC702: -# http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/zynq-7000_soc_boards_and_kits/zynq-7000_soc_zc702_evaluation_kit.html -# For the FSBL 'zynq_fsbl_0.elf' refer to UG873 and the associated design files. -# - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -# u-boot configuration -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "zynq-zc702.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - boot.scr \ - " - -QB_MEM = "-m 1024" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=/tftpboot -net nic" -QB_DEFAULT_KERNEL_qemuboot-xilinx = "zImage" - -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE = "cpio.gz.u-boot" -QB_DTB = "system.dtb" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND = " \ - -nographic -serial null -serial mon:stdio \ - -initrd ${DEPLOY_DIR_IMAGE}/petalinux-image-minimal-zc702-zynq7.cpio.gz.u-boot \ - -gdb tcp::9000 \ - -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 \ - -device loader,addr=0xf8000140,data=0x00500801,data-len=4 \ - -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 \ - -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 \ - -device loader,addr=0xF8000910,data=0xF,data-len=0x4 \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc706-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc706-zynq7.conf deleted file mode 100644 index 10b5e29c9..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc706-zynq7.conf +++ /dev/null @@ -1,58 +0,0 @@ -#@TYPE: Machine -#@NAME: zc706-zynq7 -#@DESCRIPTION: Machine support for ZC706 Evaluation Board. -# -# For details on the Evaluation board: -# http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm -# For documentation and design files for the ZC702: -# http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/zynq-7000_soc_boards_and_kits/zynq-7000_soc_zc706_evaluation_kit.html -# For the FSBL 'zynq_fsbl_0.elf' refer to UG873 and the associated design files. -# - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost usbgadget" - -# u-boot configuration -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "zynq-zc706.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - boot.scr \ - " - -QB_MEM = "-m 1024" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=/tftpboot -net nic" -QB_DEFAULT_KERNEL_qemuboot-xilinx = "zImage" - -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE = "cpio.gz.u-boot" -QB_DTB = "system.dtb" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND = " \ - -nographic -serial null -serial mon:stdio \ - -initrd ${DEPLOY_DIR_IMAGE}/petalinux-image-minimal-zc706-zynq7.cpio.gz.u-boot \ - -gdb tcp::9000 \ - -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 \ - -device loader,addr=0xf8000140,data=0x00500801,data-len=4 \ - -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 \ - -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 \ - -device loader,addr=0xF8000910,data=0xF,data-len=0x4 \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf deleted file mode 100644 index 2c890cfb8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf +++ /dev/null @@ -1,74 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu102-zynqmp -#@DESCRIPTION: Machine support for ZCU102 Evaluation Board. - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -# Default SD image build onfiguration, use qemu-sd to pad -IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" -WKS_FILES ?= "sdimage-bootpart.wks" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu102-rev1.0.dtb" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - qemu-devicetrees \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - boot.scr \ - " - -# This machine has a QEMU model, runqemu setup: -QB_MEM = "-m 4096" -QB_OPT_APPEND ?= "-nographic -serial mon:stdio -serial null" -QB_NETWORK_DEVICE = "-net nic -net nic -net nic -net nic,netdev=net0,macaddr=@MAC@" - -# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND_append_qemuboot-xilinx = " \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zcu102-arm.dtb \ - ${@qemu_zynqmp_unhalt(d, True)} \ - -device loader,file=${DEPLOY_DIR_IMAGE}/arm-trusted-firmware.elf,cpu-num=0 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/u-boot.elf \ - -device loader,file=${DEPLOY_DIR_IMAGE}/system.dtb,addr=0x100000 \ - " - -# Attach the rootfs disk image to the second SD interface of QEMU (which is SD0) -QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# PMU instance args -PMU_ROM ?= "${DEPLOY_DIR_IMAGE}/pmu-rom.elf" -PMU_FIRMWARE_DEPLOY_DIR ?= "${@ '${TOPDIR}/pmutmp/deploy/images/microblaze-pmu' if d.getVar('BBMULTICONFIG') == 'pmu' else '${TOPDIR}/tmp/deploy/images/${MACHINE}'}" -PMU_FIRMWARE_IMAGE_NAME ?= "${@ 'pmu-firmware-microblaze-pmu' if d.getVar('BBMULTICONFIG') == 'pmu' else 'pmu-zcu102-zynqmp'}" - -QB_PMU_OPT = " \ - -M microblaze-fdt \ - -display none \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zynqmp-pmu.dtb \ - -kernel ${PMU_ROM} \ - -device loader,file=${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}.elf \ - -device loader,addr=0xfd1a0074,data=0x1011003,data-len=4 \ - -device loader,addr=0xfd1a007C,data=0x1010f03,data-len=4 \ - " -QB_OPT_APPEND_append_qemuboot-xilinx = " -pmu-args '${QB_PMU_OPT}'" - -do_write_qemuboot_conf[depends] += "u-boot-zynq-uenv:do_deploy" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu104-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu104-zynqmp.conf deleted file mode 100644 index 17a677fe3..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu104-zynqmp.conf +++ /dev/null @@ -1,38 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu104-zynqmp -#@DESCRIPTION: Machine support for ZCU104 Evaluation Board. -# - -SOC_VARIANT ?= "ev" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu104-revC.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " - -MACHINE_HWCODECS = "libomxil-xlnx" - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu106-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu106-zynqmp.conf deleted file mode 100644 index 27ab2a98f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu106-zynqmp.conf +++ /dev/null @@ -1,36 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu106-zynqmp -#@DESCRIPTION: Machine support for ZCU106 Evaluation Board. - -SOC_VARIANT ?= "ev" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu106-revA.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " - -MACHINE_HWCODECS = "libomxil-xlnx" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu111-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu111-zynqmp.conf deleted file mode 100644 index 24e96ad64..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu111-zynqmp.conf +++ /dev/null @@ -1,35 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu111-zynqmp -#@DESCRIPTION: Machine support for ZCU111 Evaluation Board. -# - -SOC_VARIANT ?= "dr" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu111-revA.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu1275-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu1275-zynqmp.conf deleted file mode 100644 index 2ac4004fc..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu1275-zynqmp.conf +++ /dev/null @@ -1,35 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu1275-zynqmp -#@DESCRIPTION: Machine support for ZCU1275 Evaluation Board. -# - -SOC_VARIANT ?= "dr" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu1275-revB.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu1285-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu1285-zynqmp.conf deleted file mode 100644 index d7d41d4d8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu1285-zynqmp.conf +++ /dev/null @@ -1,35 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu1285-zynqmp -#@DESCRIPTION: Machine support for ZCU1285 Evaluation Board. -# - -SOC_VARIANT ?= "dr" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu1285-revA.dtb" - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu208-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu208-zynqmp.conf deleted file mode 100644 index c69b5f35b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu208-zynqmp.conf +++ /dev/null @@ -1,33 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu208-zynqmp -#@DESCRIPTION: Machine support for ZCU208 Evaluation Board. -# - -SOC_VARIANT ?= "dr" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu216-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu216-zynqmp.conf deleted file mode 100644 index 4f07e0ea8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu216-zynqmp.conf +++ /dev/null @@ -1,33 +0,0 @@ -#@TYPE: Machine -#@NAME: zcu216-zynqmp -#@DESCRIPTION: Machine support for ZCU216 Evaluation Board. -# - -SOC_VARIANT ?= "dr" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - - -PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" -PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - boot.scr \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf deleted file mode 100644 index d731b6bb3..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf +++ /dev/null @@ -1,34 +0,0 @@ -#@TYPE: Machine -#@NAME: zedboard-zynq7 -#@DESCRIPTION: Machine support for ZedBoard. (http://www.zedboard.org/) -# -# For details on the Evaluation board: -# http://www.zedboard.org/content/overview -# For design files (including 'zynq_fsbl_0.elf') for the ZedBoard: -# http://www.zedboard.org/reference-designs-categories/zynq-concepts-tools-and-techniques-zedboard -# - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -# u-boot configuration -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "zynq-zed.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - boot.scr \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf deleted file mode 100644 index 898954e9e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf +++ /dev/null @@ -1,40 +0,0 @@ -#@TYPE: Machine -#@NAME: zybo-linux-bd-zynq7 -#@DESCRIPTION: Machine support for zybo-linux-bd project. -# -# generated base on ZYBO linux-bd project -# - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot" - -MACHINE_FEATURES = "ext2 vfat usbhost usbgadget keyboard screen alsa sdio" -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" -FORCE_PLATFORM_INIT = "1" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bitstream \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -IMAGE_BOOT_FILES += " \ - boot.bin \ - bitstream \ - uEnv.txt \ - " - -KERNEL_FEATURES += " \ - bsp/xilinx/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc \ - features/xilinx/v4l2/v4l2.scc \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf deleted file mode 100644 index d7af056a3..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf +++ /dev/null @@ -1,35 +0,0 @@ -#@TYPE: Machine -#@NAME: zybo-zynq7 -#@DESCRIPTION: Machine support for ZYBO. -# -# For details on the ZYBO board: -# https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO -# - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "ext2 vfat usbhost usbgadget" - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -UBOOT_MACHINE = "xilinx_zynq_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -KERNEL_DEVICETREE = "zynq-zybo.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zynq-generic.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zynq-generic.conf deleted file mode 100644 index be0f701cb..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zynq-generic.conf +++ /dev/null @@ -1,41 +0,0 @@ -#@TYPE: Machine -#@NAME: Generic Zynq -#@DESCRIPTION: Generic Zynq Device - -require conf/machine/include/soc-zynq.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc -require conf/machine/include/xilinx-board.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost usbgadget" - -EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" - -UBOOT_MACHINE ?= "xilinx_zynq_virt_defconfig" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -HDF_MACHINE = "zc702-zynq7" - -QB_MEM = "-m 1024" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=/tftpboot -net nic" -QB_DEFAULT_KERNEL_qemuboot-xilinx = "zImage" - -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE = "cpio.gz.u-boot" -QB_DTB = "system.dtb" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND = " \ - -nographic -serial null -serial mon:stdio \ - -initrd ${DEPLOY_DIR_IMAGE}/petalinux-image-minimal-zynq-generic.cpio.gz.u-boot \ - -gdb tcp::9000 \ - -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 \ - -device loader,addr=0xf8000140,data=0x00500801,data-len=4 \ - -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 \ - -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 \ - -device loader,addr=0xF8000910,data=0xF,data-len=0x4 \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zynqmp-generic.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zynqmp-generic.conf deleted file mode 100644 index 9c7dbe839..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zynqmp-generic.conf +++ /dev/null @@ -1,84 +0,0 @@ -#@TYPE: Machine -#@NAME: Generic zynqmp -#@DESCRIPTION: zynqmp devices - -# CG is the lowest common demoninator, so use this by default -SOC_VARIANT ?= "cg" - -require conf/machine/include/soc-zynqmp.inc -require conf/machine/include/machine-xilinx-default.inc -require conf/machine/include/machine-xilinx-qemu.inc -require conf/machine/include/xilinx-board.inc - -MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" - -EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" - -UBOOT_MACHINE = "xilinx_zynqmp_virt_defconfig" -SPL_BINARY ?= "spl/boot.bin" - -# Default SD image build onfiguration, use qemu-sd to pad -IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" -WKS_FILES ?= "sdimage-bootpart.wks" - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -# We need a generic one that works with QEMU... -HDF_MACHINE = "zcu102-zynqmp" -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu102-rev1.0.dtb" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - arm-trusted-firmware \ - qemu-devicetrees \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - atf-uboot.ub \ - ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ - boot.scr \ - " - -# This machine has a QEMU model, runqemu setup: -QB_MEM = "-m 4096" -QB_OPT_APPEND ?= "-nographic -serial mon:stdio -serial null" -QB_NETWORK_DEVICE = "-net nic -net nic -net nic -net nic,netdev=net0,macaddr=@MAC@" - -# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND_append_qemuboot-xilinx = " \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zcu102-arm.dtb \ - ${@qemu_zynqmp_unhalt(d, True)} \ - -device loader,file=${DEPLOY_DIR_IMAGE}/arm-trusted-firmware.elf,cpu-num=0 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/u-boot.elf \ - -device loader,file=${DEPLOY_DIR_IMAGE}/system.dtb,addr=0x100000 \ - " - -# Attach the rootfs disk image to the second SD interface of QEMU (which is SD0) -QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# PMU instance args -PMU_ROM ?= "${DEPLOY_DIR_IMAGE}/pmu-rom.elf" -PMU_FIRMWARE_DEPLOY_DIR ?= "${@ '${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu' if d.getVar('BMULTICONFIG') == 'pmu' else '${TOPDIR}/tmp/deploy/images/${MACHINE}'}" -PMU_FIRMWARE_IMAGE_NAME ?= "${@ 'pmu-firmware-zynqmp-pmu' if d.getVar('BBMULTICONFIG') == 'pmu' else 'pmu-${MACHINE}'}" - -QB_PMU_OPT = " \ - -M microblaze-fdt \ - -display none \ - -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zynqmp-pmu.dtb \ - -kernel ${PMU_ROM} \ - -device loader,file=${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}.elf \ - -device loader,addr=0xfd1a0074,data=0x1011003,data-len=4 \ - -device loader,addr=0xfd1a007C,data=0x1010f03,data-len=4 \ - " -QB_OPT_APPEND_append_qemuboot-xilinx = " -pmu-args '${QB_PMU_OPT}'" - -do_write_qemuboot_conf[depends] += "u-boot-zynq-uenv:do_deploy" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/multiconfig/fsblmc.conf b/meta-xilinx/meta-xilinx-bsp/conf/multiconfig/fsblmc.conf deleted file mode 100644 index 87bb56a8c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/multiconfig/fsblmc.conf +++ /dev/null @@ -1,8 +0,0 @@ -MACHINE = "cortexa53-zynqmp" -DISTRO = "xilinx-standalone" -TMPDIR = "${TOPDIR}/tmp-${MACHINE}-${TCLIBC}" - -# These should be temporary until the dtg repo has the correct design -HDF_BASE ?= "file://" -HDF_PATH ?= "${TOPDIR}/system.dsa" -HDF_EXT ?= "dsa" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/multiconfig/pmumc.conf b/meta-xilinx/meta-xilinx-bsp/conf/multiconfig/pmumc.conf deleted file mode 100644 index 756ea94aa..000000000 --- a/meta-xilinx/meta-xilinx-bsp/conf/multiconfig/pmumc.conf +++ /dev/null @@ -1,8 +0,0 @@ -MACHINE = "microblaze-pmu" -DISTRO = "xilinx-standalone" -TMPDIR = "${TOPDIR}/tmp-${MACHINE}-${TCLIBC}" - -# These should be temporary until the dtg repo has the correct design -HDF_BASE ?= "file://" -HDF_PATH ?= "${TOPDIR}/system.dsa" -HDF_EXT ?= "dsa" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc deleted file mode 100644 index b086f8ca2..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ /dev/null @@ -1,97 +0,0 @@ -DESCRIPTION = "ARM Trusted Firmware" - -LICENSE = "BSD" -LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" - -PROVIDES = "virtual/arm-trusted-firmware" - -inherit deploy - -DEPENDS += "u-boot-mkimage-native" - -S = "${WORKDIR}/git" -B = "${WORKDIR}/build" - -SYSROOT_DIRS += "/boot" - -XILINX_RELEASE_VERSION ?= "" -ATF_VERSION ?= "2.2" -ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" -PV = "${ATF_VERSION}${ATF_VERSION_EXTENSION}+git${SRCPV}" - -BRANCH ?= "" -REPO ?= "git://github.com/Xilinx/arm-trusted-firmware.git;protocol=https" -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -ATF_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}${IMAGE_VERSION_SUFFIX}" - -COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE_zynqmp = ".*" -COMPATIBLE_MACHINE_versal = ".*" - -PLATFORM_zynqmp = "zynqmp" -PLATFORM_versal = "versal" - -# requires CROSS_COMPILE set by hand as there is no configure script -export CROSS_COMPILE="${TARGET_PREFIX}" - -# Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application -CFLAGS[unexport] = "1" -LDFLAGS[unexport] = "1" -AS[unexport] = "1" -LD[unexport] = "1" - -ATF_CONSOLE ?= "" -ATF_CONSOLE_zynqmp = "cadence" -ATF_CONSOLE_versal ?= "pl011" - -DEBUG_ATF ?= "" -DEBUG_ATF_versal ?= "1" - -EXTRA_OEMAKE_zynqmp_append = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" -EXTRA_OEMAKE_append_versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" -EXTRA_OEMAKE_append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}" - -OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}" - -ATF_MEM_BASE ?= "" -ATF_MEM_SIZE ?= "" - -EXTRA_OEMAKE_zynqmp_append = "${@' ZYNQMP_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" -EXTRA_OEMAKE_zynqmp_append = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" - -EXTRA_OEMAKE_append_versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" -EXTRA_OEMAKE_append_versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" -EXTRA_OEMAKE_append_vc-p-a2197-00-versal =" VERSAL_PLATFORM=silicon" - -do_configure() { - oe_runmake clean -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} -} - -do_compile() { - oe_runmake -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} RESET_TO_BL31=1 bl31 -} - -do_install() { - install -d ${D}/boot - install -Dm 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${D}/boot/${PN}-${SRCPV}.elf -} - -do_deploy() { - install -d ${DEPLOYDIR} - install -m 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${DEPLOYDIR}/${ATF_BASE_NAME}.elf - ln -sf ${ATF_BASE_NAME}.elf ${DEPLOYDIR}/${PN}.elf - install -m 0644 ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.bin - ln -sf ${ATF_BASE_NAME}.bin ${DEPLOYDIR}/${PN}.bin - - # Get the entry point address from the elf. - BL31_BASE_ADDR=$(${READELF} -h ${OUTPUT_DIR}/bl31/bl31.elf | egrep -m 1 -i "entry point.*?0x" | sed -r 's/.*?(0x.*?)/\1/g') - mkimage -A arm64 -O arm-trusted-firmware -T kernel -C none \ - -a $BL31_BASE_ADDR -e $BL31_BASE_ADDR \ - -d ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.ub - ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/${PN}.ub - ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub -} -addtask deploy before do_build after do_compile -FILES_${PN} += "/boot/${PN}-${SRCPV}.elf" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2020.2.bb deleted file mode 100644 index 201b6496b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2020.2.bb +++ /dev/null @@ -1,6 +0,0 @@ -ATF_VERSION = "2.0" -BRANCH ?= "xlnx_rebase_v2.2" -SRCREV ?= "e6eea88b14aaf456c49f9c7e6747584224648cb9" - -include arm-trusted-firmware.inc - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/bootgen/bootgen_1.0.bb deleted file mode 100644 index 887558d96..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/bootgen/bootgen_1.0.bb +++ /dev/null @@ -1,31 +0,0 @@ -SUMMARY = "Building and installing bootgen" -DESCRIPTION = "Building and installing bootgen, a Xilinx tool that lets you stitch binary files together and generate device boot images" - -LICENSE = "Apache-2.0" -LIC_FILES_CHKSUM = "file://LICENSE;md5=d526b6d0807bf263b97da1da876f39b1" - -S = "${WORKDIR}/git" - -DEPENDS += "openssl" -RDEPENDS_${PN} += "openssl" - -REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https" -BRANCH ?= "master" -SRCREV ?= "465e32423aa6ba2d71f51c4ae0602cfeb022af08" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -EXTRA_OEMAKE += 'CROSS_COMPILER="${CXX}" -C ${S}' -CXXFLAGS_append = " -std=c++0x" - -TARGET_CC_ARCH += "${LDFLAGS}" - -do_install() { - install -d ${D}${bindir} - install -Dm 0755 ${S}/bootgen ${D}${bindir} -} - -FILES_${PN} = "${bindir}/bootgen" - -BBCLASSEXTEND = "native nativesdk" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb deleted file mode 100644 index 0ecb3aa3c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb +++ /dev/null @@ -1,41 +0,0 @@ -SUMMARY = "Xilinx BSP device trees" -DESCRIPTION = "Xilinx BSP device trees from within layer." -SECTION = "bsp" - -# the device trees from within the layer are licensed as MIT, kernel includes are GPL -LICENSE = "MIT & GPLv2" -LIC_FILES_CHKSUM = " \ - file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302 \ - file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6 \ - " - -inherit devicetree - -DEPENDS += "python3-dtc-native" - -PROVIDES = "virtual/dtb" - -# common zynq include -SRC_URI_append_zynq = " file://zynq-7000-qspi-dummy.dtsi" - -# device tree sources for the various machines -COMPATIBLE_MACHINE_picozed-zynq7 = ".*" -SRC_URI_append_picozed-zynq7 = " file://picozed-zynq7.dts" - -COMPATIBLE_MACHINE_qemu-zynq7 = ".*" -SRC_URI_append_qemu-zynq7 = " file://qemu-zynq7.dts" - -COMPATIBLE_MACHINE_zybo-linux-bd-zynq7 = ".*" -SRC_URI_append_zybo-linux-bd-zynq7 = " \ - file://zybo-linux-bd-zynq7.dts \ - file://pcw.dtsi \ - file://pl.dtsi \ - " - -COMPATIBLE_MACHINE_kc705-microblazeel = ".*" -SRC_URI_append_kc705-microblazeel = " \ - file://kc705-microblazeel.dts \ - file://pl.dtsi \ - file://system-conf.dtsi \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts deleted file mode 100644 index 45e488c1d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts +++ /dev/null @@ -1,56 +0,0 @@ -/dts-v1/; -/include/ "pl.dtsi" -/include/ "system-conf.dtsi" -/ { - hard-reset-gpios = <&reset_gpio 0 1>; - aliases { - ethernet0 = &axi_ethernet; - i2c0 = &iic_main; - serial0 = &rs232_uart; - }; - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&iic_main { - i2cswitch@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@54 { - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - }; -}; - -&axi_ethernet { - phy-handle = <&phy0>; - axi_ethernet_mdio: mdio { - phy0: phy@7 { - device_type = "ethernet-phy"; - reg = <7>; - }; - }; -}; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi deleted file mode 100644 index 43bc2ab78..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi +++ /dev/null @@ -1,445 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,microblaze"; - model = "Xilinx MicroBlaze"; - cpus { - #address-cells = <1>; - #cpus = <1>; - #size-cells = <0>; - microblaze_0: cpu@0 { - bus-handle = <&amba_pl>; - clock-frequency = <200000000>; - clocks = <&clk_cpu>; - compatible = "xlnx,microblaze-10.0"; - d-cache-baseaddr = <0x0000000080000000>; - d-cache-highaddr = <0x00000000bfffffff>; - d-cache-line-size = <0x20>; - d-cache-size = <0x4000>; - device_type = "cpu"; - i-cache-baseaddr = <0x0000000080000000>; - i-cache-highaddr = <0x00000000bfffffff>; - i-cache-line-size = <0x10>; - i-cache-size = <0x4000>; - interrupt-handle = <µblaze_0_axi_intc>; - model = "microblaze,10.0"; - timebase-frequency = <200000000>; - xlnx,addr-size = <0x20>; - xlnx,addr-tag-bits = <0x10>; - xlnx,allow-dcache-wr = <0x1>; - xlnx,allow-icache-wr = <0x1>; - xlnx,area-optimized = <0x0>; - xlnx,async-interrupt = <0x1>; - xlnx,async-wakeup = <0x3>; - xlnx,avoid-primitives = <0x0>; - xlnx,base-vectors = <0x0000000000000000>; - xlnx,branch-target-cache-size = <0x0>; - xlnx,cache-byte-size = <0x4000>; - xlnx,d-axi = <0x1>; - xlnx,d-lmb = <0x1>; - xlnx,d-lmb-mon = <0x0>; - xlnx,daddr-size = <0x20>; - xlnx,data-size = <0x20>; - xlnx,dc-axi-mon = <0x0>; - xlnx,dcache-addr-tag = <0x10>; - xlnx,dcache-always-used = <0x1>; - xlnx,dcache-byte-size = <0x4000>; - xlnx,dcache-data-width = <0x0>; - xlnx,dcache-force-tag-lutram = <0x0>; - xlnx,dcache-line-len = <0x8>; - xlnx,dcache-use-writeback = <0x0>; - xlnx,dcache-victims = <0x0>; - xlnx,debug-counter-width = <0x20>; - xlnx,debug-enabled = <0x1>; - xlnx,debug-event-counters = <0x5>; - xlnx,debug-external-trace = <0x0>; - xlnx,debug-interface = <0x0>; - xlnx,debug-latency-counters = <0x1>; - xlnx,debug-profile-size = <0x0>; - xlnx,debug-trace-async-reset = <0x0>; - xlnx,debug-trace-size = <0x2000>; - xlnx,div-zero-exception = <0x1>; - xlnx,dp-axi-mon = <0x0>; - xlnx,dynamic-bus-sizing = <0x0>; - xlnx,ecc-use-ce-exception = <0x0>; - xlnx,edge-is-positive = <0x1>; - xlnx,enable-discrete-ports = <0x0>; - xlnx,endianness = <0x1>; - xlnx,fault-tolerant = <0x0>; - xlnx,fpu-exception = <0x0>; - xlnx,freq = <0xbebc200>; - xlnx,fsl-exception = <0x0>; - xlnx,fsl-links = <0x0>; - xlnx,i-axi = <0x0>; - xlnx,i-lmb = <0x1>; - xlnx,i-lmb-mon = <0x0>; - xlnx,iaddr-size = <0x20>; - xlnx,ic-axi-mon = <0x0>; - xlnx,icache-always-used = <0x1>; - xlnx,icache-data-width = <0x0>; - xlnx,icache-force-tag-lutram = <0x0>; - xlnx,icache-line-len = <0x4>; - xlnx,icache-streams = <0x1>; - xlnx,icache-victims = <0x8>; - xlnx,ill-opcode-exception = <0x1>; - xlnx,imprecise-exceptions = <0x0>; - xlnx,instr-size = <0x20>; - xlnx,interconnect = <0x2>; - xlnx,interrupt-is-edge = <0x0>; - xlnx,interrupt-mon = <0x0>; - xlnx,ip-axi-mon = <0x0>; - xlnx,lockstep-master = <0x0>; - xlnx,lockstep-select = <0x0>; - xlnx,lockstep-slave = <0x0>; - xlnx,mmu-dtlb-size = <0x4>; - xlnx,mmu-itlb-size = <0x2>; - xlnx,mmu-privileged-instr = <0x0>; - xlnx,mmu-tlb-access = <0x3>; - xlnx,mmu-zones = <0x2>; - xlnx,num-sync-ff-clk = <0x2>; - xlnx,num-sync-ff-clk-debug = <0x2>; - xlnx,num-sync-ff-clk-irq = <0x1>; - xlnx,num-sync-ff-dbg-clk = <0x1>; - xlnx,num-sync-ff-dbg-trace-clk = <0x2>; - xlnx,number-of-pc-brk = <0x1>; - xlnx,number-of-rd-addr-brk = <0x0>; - xlnx,number-of-wr-addr-brk = <0x0>; - xlnx,opcode-0x0-illegal = <0x1>; - xlnx,optimization = <0x0>; - xlnx,pc-width = <0x20>; - xlnx,piaddr-size = <0x20>; - xlnx,pvr = <0x2>; - xlnx,pvr-user1 = <0x00>; - xlnx,pvr-user2 = <0x00000000>; - xlnx,reset-msr = <0x00000000>; - xlnx,reset-msr-bip = <0x0>; - xlnx,reset-msr-dce = <0x0>; - xlnx,reset-msr-ee = <0x0>; - xlnx,reset-msr-eip = <0x0>; - xlnx,reset-msr-ice = <0x0>; - xlnx,reset-msr-ie = <0x0>; - xlnx,sco = <0x0>; - xlnx,trace = <0x0>; - xlnx,unaligned-exceptions = <0x1>; - xlnx,use-barrel = <0x1>; - xlnx,use-branch-target-cache = <0x0>; - xlnx,use-config-reset = <0x0>; - xlnx,use-dcache = <0x1>; - xlnx,use-div = <0x1>; - xlnx,use-ext-brk = <0x0>; - xlnx,use-ext-nm-brk = <0x0>; - xlnx,use-extended-fsl-instr = <0x0>; - xlnx,use-fpu = <0x0>; - xlnx,use-hw-mul = <0x2>; - xlnx,use-icache = <0x1>; - xlnx,use-interrupt = <0x2>; - xlnx,use-mmu = <0x3>; - xlnx,use-msr-instr = <0x1>; - xlnx,use-non-secure = <0x0>; - xlnx,use-pcmp-instr = <0x1>; - xlnx,use-reorder-instr = <0x1>; - xlnx,use-stack-protection = <0x0>; - }; - }; - clocks { - #address-cells = <1>; - #size-cells = <0>; - clk_cpu: clk_cpu@0 { - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "clk_cpu"; - compatible = "fixed-clock"; - reg = <0>; - }; - clk_bus_0: clk_bus_0@1 { - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "clk_bus_0"; - compatible = "fixed-clock"; - reg = <1>; - }; - }; - amba_pl: amba_pl { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges ; - axi_ethernet: ethernet@40c00000 { - axistream-connected = <&axi_ethernet_dma>; - axistream-control-connected = <&axi_ethernet_dma>; - clock-frequency = <100000000>; - compatible = "xlnx,axi-ethernet-1.00.a"; - device_type = "network"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <4 2>; - phy-mode = "gmii"; - reg = <0x40c00000 0x40000>; - xlnx = <0x0>; - xlnx,axiliteclkrate = <0x0>; - xlnx,axisclkrate = <0x0>; - xlnx,clockselection = <0x0>; - xlnx,enableasyncsgmii = <0x0>; - xlnx,gt-type = <0x0>; - xlnx,gtinex = <0x0>; - xlnx,gtlocation = <0x0>; - xlnx,gtrefclksrc = <0x0>; - xlnx,include-dre ; - xlnx,instantiatebitslice0 = <0x0>; - xlnx,phy-type = <0x1>; - xlnx,phyaddr = <0x1>; - xlnx,rable = <0x0>; - xlnx,rxcsum = <0x0>; - xlnx,rxlane0-placement = <0x0>; - xlnx,rxlane1-placement = <0x0>; - xlnx,rxmem = <0x1000>; - xlnx,rxnibblebitslice0used = <0x0>; - xlnx,tx-in-upper-nibble = <0x1>; - xlnx,txcsum = <0x0>; - xlnx,txlane0-placement = <0x0>; - xlnx,txlane1-placement = <0x0>; - axi_ethernet_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - axi_ethernet_dma: dma@41e00000 { - #dma-cells = <1>; - axistream-connected = <&axi_ethernet>; - axistream-control-connected = <&axi_ethernet>; - clock-frequency = <200000000>; - clock-names = "s_axi_lite_aclk"; - clocks = <&clk_bus_0>; - compatible = "xlnx,eth-dma"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <3 2 2 2>; - reg = <0x41e00000 0x10000>; - xlnx,include-dre ; - }; - axi_timer_0: timer@41c00000 { - clock-frequency = <200000000>; - clocks = <&clk_bus_0>; - compatible = "xlnx,xps-timer-1.00.a"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <5 2>; - reg = <0x41c00000 0x10000>; - xlnx,count-width = <0x20>; - xlnx,gen0-assert = <0x1>; - xlnx,gen1-assert = <0x1>; - xlnx,one-timer-only = <0x0>; - xlnx,trig0-assert = <0x1>; - xlnx,trig1-assert = <0x1>; - }; - calib_complete_gpio: gpio@40010000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40010000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - dip_switches_4bits: gpio@40020000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40020000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - iic_main: i2c@40800000 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <200000000>; - clocks = <&clk_bus_0>; - compatible = "xlnx,xps-iic-2.00.a"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <1 2>; - reg = <0x40800000 0x10000>; - }; - led_8bits: gpio@40030000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40030000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x8>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - linear_flash: flash@60000000 { - bank-width = <2>; - compatible = "cfi-flash"; - reg = <0x60000000 0x8000000>; - xlnx,axi-clk-period-ps = <0x1388>; - xlnx,include-datawidth-matching-0 = <0x1>; - xlnx,include-datawidth-matching-1 = <0x1>; - xlnx,include-datawidth-matching-2 = <0x1>; - xlnx,include-datawidth-matching-3 = <0x1>; - xlnx,include-negedge-ioregs = <0x0>; - xlnx,lflash-period-ps = <0x1388>; - xlnx,linear-flash-sync-burst = <0x0>; - xlnx,max-mem-width = <0x10>; - xlnx,mem-a-lsb = <0x0>; - xlnx,mem-a-msb = <0x1f>; - xlnx,mem0-type = <0x2>; - xlnx,mem0-width = <0x10>; - xlnx,mem1-type = <0x0>; - xlnx,mem1-width = <0x10>; - xlnx,mem2-type = <0x0>; - xlnx,mem2-width = <0x10>; - xlnx,mem3-type = <0x0>; - xlnx,mem3-width = <0x10>; - xlnx,num-banks-mem = <0x1>; - xlnx,page-size = <0x10>; - xlnx,parity-type-mem-0 = <0x0>; - xlnx,parity-type-mem-1 = <0x0>; - xlnx,parity-type-mem-2 = <0x0>; - xlnx,parity-type-mem-3 = <0x0>; - xlnx,port-diff = <0x0>; - xlnx,s-axi-en-reg = <0x0>; - xlnx,s-axi-mem-addr-width = <0x20>; - xlnx,s-axi-mem-data-width = <0x20>; - xlnx,s-axi-mem-id-width = <0x1>; - xlnx,s-axi-reg-addr-width = <0x5>; - xlnx,s-axi-reg-data-width = <0x20>; - xlnx,synch-pipedelay-0 = <0x1>; - xlnx,synch-pipedelay-1 = <0x1>; - xlnx,synch-pipedelay-2 = <0x1>; - xlnx,synch-pipedelay-3 = <0x1>; - xlnx,tavdv-ps-mem-0 = <0x1fbd0>; - xlnx,tavdv-ps-mem-1 = <0x3a98>; - xlnx,tavdv-ps-mem-2 = <0x3a98>; - xlnx,tavdv-ps-mem-3 = <0x3a98>; - xlnx,tcedv-ps-mem-0 = <0x1fbd0>; - xlnx,tcedv-ps-mem-1 = <0x3a98>; - xlnx,tcedv-ps-mem-2 = <0x3a98>; - xlnx,tcedv-ps-mem-3 = <0x3a98>; - xlnx,thzce-ps-mem-0 = <0x88b8>; - xlnx,thzce-ps-mem-1 = <0x1b58>; - xlnx,thzce-ps-mem-2 = <0x1b58>; - xlnx,thzce-ps-mem-3 = <0x1b58>; - xlnx,thzoe-ps-mem-0 = <0x1b58>; - xlnx,thzoe-ps-mem-1 = <0x1b58>; - xlnx,thzoe-ps-mem-2 = <0x1b58>; - xlnx,thzoe-ps-mem-3 = <0x1b58>; - xlnx,tlzwe-ps-mem-0 = <0xc350>; - xlnx,tlzwe-ps-mem-1 = <0x0>; - xlnx,tlzwe-ps-mem-2 = <0x0>; - xlnx,tlzwe-ps-mem-3 = <0x0>; - xlnx,tpacc-ps-flash-0 = <0x61a8>; - xlnx,tpacc-ps-flash-1 = <0x61a8>; - xlnx,tpacc-ps-flash-2 = <0x61a8>; - xlnx,tpacc-ps-flash-3 = <0x61a8>; - xlnx,twc-ps-mem-0 = <0x11170>; - xlnx,twc-ps-mem-1 = <0x3a98>; - xlnx,twc-ps-mem-2 = <0x3a98>; - xlnx,twc-ps-mem-3 = <0x3a98>; - xlnx,twp-ps-mem-0 = <0x13880>; - xlnx,twp-ps-mem-1 = <0x2ee0>; - xlnx,twp-ps-mem-2 = <0x2ee0>; - xlnx,twp-ps-mem-3 = <0x2ee0>; - xlnx,twph-ps-mem-0 = <0x13880>; - xlnx,twph-ps-mem-1 = <0x2ee0>; - xlnx,twph-ps-mem-2 = <0x2ee0>; - xlnx,twph-ps-mem-3 = <0x2ee0>; - xlnx,use-startup = <0x0>; - xlnx,use-startup-int = <0x0>; - xlnx,wr-rec-time-mem-0 = <0x186a0>; - xlnx,wr-rec-time-mem-1 = <0x6978>; - xlnx,wr-rec-time-mem-2 = <0x6978>; - xlnx,wr-rec-time-mem-3 = <0x6978>; - }; - microblaze_0_axi_intc: interrupt-controller@41200000 { - #interrupt-cells = <2>; - compatible = "xlnx,xps-intc-1.00.a"; - interrupt-controller ; - reg = <0x41200000 0x10000>; - xlnx,kind-of-intr = <0x0>; - xlnx,num-intr-inputs = <0x6>; - }; - push_buttons_5bits: gpio@40040000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40040000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x5>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - reset_gpio: gpio@40000000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40000000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - rs232_uart: serial@44a00000 { - clock-frequency = <200000000>; - clocks = <&clk_bus_0>; - compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; - current-speed = <115200>; - device_type = "serial"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <0 2>; - port-number = <0>; - reg = <0x44a00000 0x10000>; - reg-offset = <0x1000>; - reg-shift = <2>; - xlnx,external-xin-clk-hz = <0x17d7840>; - xlnx,external-xin-clk-hz-d = <0x19>; - xlnx,has-external-rclk = <0x0>; - xlnx,has-external-xin = <0x0>; - xlnx,is-a-16550 = <0x1>; - xlnx,s-axi-aclk-freq-hz-d = "200.0"; - xlnx,use-modem-ports = <0x1>; - xlnx,use-user-ports = <0x1>; - }; - }; -}; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi deleted file mode 100644 index 09b26c6ad..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -/* - * CAUTION: This file is automatically generated by PetaLinux SDK. - * DO NOT modify this file - */ - - -/ { - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = "serial0:115200n8"; - }; -}; - -&axi_ethernet { - local-mac-address = [00 0a 35 00 22 01]; -}; - -&linear_flash { - reg = <0x60000000 0x08000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@0x00000000 { - label = "fpga"; - reg = <0x00000000 0x00b00000>; - }; - partition@0x00b00000 { - label = "boot"; - reg = <0x00b00000 0x00080000>; - }; - partition@0x00b80000 { - label = "bootenv"; - reg = <0x00b80000 0x00020000>; - }; - partition@0x00ba0000 { - label = "kernel"; - reg = <0x00ba0000 0x00c00000>; - }; - partition@0x017a0000 { - label = "spare"; - reg = <0x017a0000 0x00000000>; - }; -}; - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts deleted file mode 100644 index 6f9b653ab..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" - -/ { - model = "Avnet picoZed"; - compatible = "avnet,picozed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */ - }; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - compatible = "marvell,88e1512", "marvell,88e1510"; - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -&sdhci1 { - status = "okay"; - /* SD1 is onnected to a non-removable eMMC flash device */ - non-removable; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; - -&qspi { - status = "okay"; - primary_flash: ps7-qspi@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <50000000>; - /* Example 16M partition table using U-Boot + U-Boot SPL */ - partition@0x0 { - label = "boot"; - reg = <0x0 0xe0000>; - }; - partition@0xe0000 { - label = "ubootenv"; - reg = <0xe0000 0x20000>; - }; - partition@0x100000 { - label = "uboot"; - reg = <0x100000 0x100000>; - }; - partition@0x200000 { - label = "kernel"; - reg = <0x200000 0x4f0000>; - }; - partition@0x6f0000 { - label = "devicetree"; - reg = <0x6f0000 0x10000>; - }; - partition@0x700000 { - label = "rootfs"; - reg = <0x700000 0x400000>; - }; - partition@0xb00000 { - label = "spare"; - reg = <0xb00000 0x500000>; - }; - }; -}; - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts deleted file mode 100644 index cd0694d6b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts +++ /dev/null @@ -1,85 +0,0 @@ -/dts-v1/; -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" - -/ { - model = "Zynq A9 QEMU"; - compatible = "qemu,xilinx-zynq-a9", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; -}; - -&amba { - /* Setup a fixed 25 MHz clock (100Mbps) to trick the ethernet driver */ - fixednetclk: clock { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; -}; - -&gem0 { - status = "okay"; - clocks = <&clkc 30>, <&clkc 30>, <&fixednetclk>, <&fixednetclk>, <&clkc 30>; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@23 { - device_type = "ethernet-phy"; - reg = <23>; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&qspi { - status = "okay"; - is-dual = <1>; - primary_flash: ps7-qspi@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - reg = <0x0>; - spi-max-frequency = <50000000>; - partition@0x00000000 { - label = "boot"; - reg = <0x00000000 0x00500000>; - }; - partition@0x00500000 { - label = "bootenv"; - reg = <0x00500000 0x00020000>; - }; - partition@0x00520000 { - label = "config"; - reg = <0x00520000 0x00020000>; - }; - partition@0x00540000 { - label = "image"; - reg = <0x00540000 0x00a80000>; - }; - partition@0x00fc0000 { - label = "spare"; - reg = <0x00fc0000 0x00000000>; - }; - }; -}; - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi deleted file mode 100644 index 0f678d39c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -/* - * CAUTION: This file is automatically generated by Xilinx. - * Version: HSI 2015.4 - * Today is: Fri Mar 4 15:40:49 2016 -*/ - - -/ { - cpus { - cpu@0 { - operating-points = <650000 1000000 325000 1000000>; - }; - }; -}; -&gem0 { - phy-mode = "rgmii-id"; - status = "okay"; - xlnx,ptp-enet-clock = <0x6750918>; -}; -&gpio0 { - emio-gpio-width = <64>; - gpio-mask-high = <0x0>; - gpio-mask-low = <0x5600>; -}; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; -&intc { - num_cpus = <2>; - num_interrupts = <96>; -}; -&qspi { - is-dual = <0>; - num-cs = <1>; - status = "okay"; -}; -&sdhci0 { - status = "okay"; - xlnx,has-cd = <0x1>; - xlnx,has-power = <0x0>; - xlnx,has-wp = <0x1>; -}; -&uart1 { - current-speed = <115200>; - device_type = "serial"; - port-number = <0>; - status = "okay"; -}; -&usb0 { - dr_mode = "host"; - phy_type = "ulpi"; - status = "okay"; - usb-reset = <&gpio0 46 0>; -}; -&clkc { - fclk-enable = <0x3>; - ps-clk-frequency = <50000000>; -}; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi deleted file mode 100644 index 32bc76885..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -/* - * CAUTION: This file is automatically generated by Xilinx. - * Version: HSI 2015.4 - * Today is: Fri Mar 4 15:40:49 2016 -*/ - - -/ { - amba_pl: amba_pl { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges ; - axi_dynclk_0: axi_dynclk@43c10000 { - compatible = "xlnx,axi-dynclk-1.0"; - reg = <0x43c10000 0x10000>; - xlnx,s00-axi-addr-width = <0x5>; - xlnx,s00-axi-data-width = <0x20>; - }; - axi_gpio_btn: gpio@41210000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41210000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_hdmi: gpio@41230000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - interrupt-parent = <&intc>; - interrupts = <0 29 4>; - reg = <0x41230000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_led: gpio@41200000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41200000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_sw: gpio@41220000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41220000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_i2s_adi_0: axi_i2s_adi@43c20000 { - compatible = "xlnx,axi-i2s-adi-1.0"; - reg = <0x43c20000 0x10000>; - xlnx,bclk-pol = <0x0>; - xlnx,dma-type = <0x1>; - xlnx,has-rx = <0x1>; - xlnx,has-tx = <0x1>; - xlnx,lrclk-pol = <0x0>; - xlnx,num-ch = <0x1>; - xlnx,s-axi-min-size = <0x000001FF>; - xlnx,slot-width = <0x18>; - }; - axi_vdma_0: dma@43000000 { - #dma-cells = <1>; - compatible = "xlnx,axi-vdma-1.00.a"; - clocks = <&clkc 15>; - clock-names = "s_axi_lite_aclk"; - interrupt-parent = <&intc>; - interrupts = <0 30 4>; - reg = <0x43000000 0x10000>; - xlnx,flush-fsync = <0x1>; - xlnx,num-fstores = <0x1>; - dma-channel@43000000 { - compatible = "xlnx,axi-vdma-mm2s-channel"; - interrupts = <0 30 4>; - xlnx,datawidth = <0x20>; - xlnx,device-id = <0x0>; - }; - }; - v_tc_0: v_tc@43c00000 { - compatible = "xlnx,v-tc-6.1"; - interrupt-parent = <&intc>; - interrupts = <0 31 4>; - reg = <0x43c00000 0x10000>; - xlnx,det-achroma-en = <0x0>; - xlnx,det-avideo-en = <0x1>; - xlnx,det-fieldid-en = <0x0>; - xlnx,det-hblank-en = <0x1>; - xlnx,det-hsync-en = <0x1>; - xlnx,det-vblank-en = <0x1>; - xlnx,det-vsync-en = <0x1>; - xlnx,detect-en = <0x0>; - xlnx,fsync-hstart0 = <0x0>; - xlnx,fsync-hstart1 = <0x0>; - xlnx,fsync-hstart10 = <0x0>; - xlnx,fsync-hstart11 = <0x0>; - xlnx,fsync-hstart12 = <0x0>; - xlnx,fsync-hstart13 = <0x0>; - xlnx,fsync-hstart14 = <0x0>; - xlnx,fsync-hstart15 = <0x0>; - xlnx,fsync-hstart2 = <0x0>; - xlnx,fsync-hstart3 = <0x0>; - xlnx,fsync-hstart4 = <0x0>; - xlnx,fsync-hstart5 = <0x0>; - xlnx,fsync-hstart6 = <0x0>; - xlnx,fsync-hstart7 = <0x0>; - xlnx,fsync-hstart8 = <0x0>; - xlnx,fsync-hstart9 = <0x0>; - xlnx,fsync-vstart0 = <0x0>; - xlnx,fsync-vstart1 = <0x0>; - xlnx,fsync-vstart10 = <0x0>; - xlnx,fsync-vstart11 = <0x0>; - xlnx,fsync-vstart12 = <0x0>; - xlnx,fsync-vstart13 = <0x0>; - xlnx,fsync-vstart14 = <0x0>; - xlnx,fsync-vstart15 = <0x0>; - xlnx,fsync-vstart2 = <0x0>; - xlnx,fsync-vstart3 = <0x0>; - xlnx,fsync-vstart4 = <0x0>; - xlnx,fsync-vstart5 = <0x0>; - xlnx,fsync-vstart6 = <0x0>; - xlnx,fsync-vstart7 = <0x0>; - xlnx,fsync-vstart8 = <0x0>; - xlnx,fsync-vstart9 = <0x0>; - xlnx,gen-achroma-en = <0x0>; - xlnx,gen-achroma-polarity = <0x1>; - xlnx,gen-auto-switch = <0x0>; - xlnx,gen-avideo-en = <0x1>; - xlnx,gen-avideo-polarity = <0x1>; - xlnx,gen-cparity = <0x0>; - xlnx,gen-f0-vblank-hend = <0x500>; - xlnx,gen-f0-vblank-hstart = <0x500>; - xlnx,gen-f0-vframe-size = <0x2ee>; - xlnx,gen-f0-vsync-hend = <0x500>; - xlnx,gen-f0-vsync-hstart = <0x500>; - xlnx,gen-f0-vsync-vend = <0x2d9>; - xlnx,gen-f0-vsync-vstart = <0x2d4>; - xlnx,gen-f1-vblank-hend = <0x500>; - xlnx,gen-f1-vblank-hstart = <0x500>; - xlnx,gen-f1-vframe-size = <0x2ee>; - xlnx,gen-f1-vsync-hend = <0x500>; - xlnx,gen-f1-vsync-hstart = <0x500>; - xlnx,gen-f1-vsync-vend = <0x2d9>; - xlnx,gen-f1-vsync-vstart = <0x2d4>; - xlnx,gen-fieldid-en = <0x0>; - xlnx,gen-fieldid-polarity = <0x1>; - xlnx,gen-hactive-size = <0x500>; - xlnx,gen-hblank-en = <0x1>; - xlnx,gen-hblank-polarity = <0x1>; - xlnx,gen-hframe-size = <0x672>; - xlnx,gen-hsync-en = <0x1>; - xlnx,gen-hsync-end = <0x596>; - xlnx,gen-hsync-polarity = <0x1>; - xlnx,gen-hsync-start = <0x56e>; - xlnx,gen-interlaced = <0x0>; - xlnx,gen-vactive-size = <0x2d0>; - xlnx,gen-vblank-en = <0x1>; - xlnx,gen-vblank-polarity = <0x1>; - xlnx,gen-video-format = <0x2>; - xlnx,gen-vsync-en = <0x1>; - xlnx,gen-vsync-polarity = <0x1>; - xlnx,generate-en = <0x1>; - xlnx,has-axi4-lite = <0x1>; - xlnx,has-intc-if = <0x0>; - xlnx,interlace-en = <0x0>; - xlnx,max-lines = <0x1000>; - xlnx,max-pixels = <0x1000>; - xlnx,num-fsyncs = <0x1>; - xlnx,sync-en = <0x0>; - }; - }; -}; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts deleted file mode 100644 index 19654392d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts +++ /dev/null @@ -1,184 +0,0 @@ -/dts-v1/; -/include/ "skeleton.dtsi" -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" -/include/ "pcw.dtsi" -/include/ "pl.dtsi" - -/ { - model = "Digilent-Zybo-Linux-BD-v2015.4"; - aliases { - serial0 = &uart1; - ethernet0 = &gem0; - spi0 = &qspi; - }; - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - memory { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - btn4 { - label = "btn4"; - gpios = <&gpio0 50 0>; - linux,code = <108>; /* down */ - gpio-key,wakeup; - autorepeat; - }; - btn5 { - label = "btn5"; - gpios = <&gpio0 51 0>; - linux,code = <103>; /* up */ - gpio-key,wakeup; - autorepeat; - }; - }; - - usb_phy0: usb_phy@0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - reset-gpios = <&gpio0 46 1>; - }; -}; - -&amba { - u-boot,dm-pre-reloc; -}; - -&amba_pl { - encoder_0: digilent_encoder { - compatible = "digilent,drm-encoder"; - dglnt,edid-i2c = <&i2c1>; - }; - - xilinx_drm { - compatible = "xlnx,drm"; - xlnx,vtc = <&v_tc_0>; - xlnx,connector-type = "HDMIA"; - xlnx,encoder-slave = <&encoder_0>; - clocks = <&axi_dynclk_0>; - planes { - xlnx,pixel-format = "xrgb8888"; - plane0 { - dmas = <&axi_vdma_0 0>; - dma-names = "dma0"; - }; - }; - }; - - i2s_clk: i2s_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12288000>; - clock-output-names = "i2s_clk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "ZYBO-Sound-Card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MICIN", "Microphone Jack", - "Headphone Jack", "LHPOUT", - "Headphone Jack", "RHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - dailink0_master: simple-audio-card,cpu { - clocks = <&i2s_clk>; - sound-dai = <&axi_i2s_adi_0>; - }; - simple-audio-card,codec { - clocks = <&i2s_clk>; - sound-dai = <&ssm2603>; - }; - }; -}; - -&axi_dynclk_0 { - compatible = "digilent,axi-dynclk"; - #clock-cells = <0>; - clocks = <&clkc 15>; -}; - -&axi_i2s_adi_0 { - #sound-dai-cells = <0>; - compatible = "adi,axi-i2s-1.00.a"; - clocks = <&clkc 15>, <&i2s_clk>; - clock-names = "axi", "ref"; - dmas = <&dmac_s 0 &dmac_s 1>; - dma-names = "tx", "rx"; -}; - -&gem0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - local-mac-address = []; - phy0: phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -&i2c0 { - eeprom@50 { - /* Microchip 24AA02E48 */ - compatible = "microchip,24c02"; - reg = <0x50>; - }; - - ssm2603: ssm2603@1a{ - #sound-dai-cells = <0>; - compatible = "adi,ssm2603"; - reg = <0x1a>; - }; -}; - -&qspi { - #address-cells = <1>; - #size-cells = <0>; - flash0: flash@0 { - compatible = "micron,m25p80", "s25fl128s"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - partition@0x00000000 { - label = "boot"; - reg = <0x00000000 0x00300000>; - }; - partition@0x00300000 { - label = "bootenv"; - reg = <0x00300000 0x00020000>; - }; - partition@0x00320000 { - label = "kernel"; - reg = <0x00320000 0x00a80000>; - }; - partition@0x00da0000 { - label = "spare"; - reg = <0x00da0000 0x00000000>; - }; - }; -}; - -&usb0 { - usb-phy = <&usb_phy0>; -}; - -&v_tc_0 { - compatible = "xlnx,v-tc-5.01.a"; -}; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi deleted file mode 100644 index d059a2daf..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi +++ /dev/null @@ -1,4 +0,0 @@ -&amba { - /* empty defintion for kernels that don't have qspi node */ - qspi: spi@e000d000 { }; -}; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb deleted file mode 100644 index 32509b078..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb +++ /dev/null @@ -1,38 +0,0 @@ -SUMMARY = "Xilinx Platform Headers" -DESCRPTION = "Xilinx ps*_init_gpl.c/h platform init code, used for building u-boot-spl and fsbl" -HOMEPAGE = "http://www.xilinx.com" -SECTION = "bsp" - -INHIBIT_DEFAULT_DEPS = "1" - -PACKAGE_ARCH = "${MACHINE_ARCH}" - -inherit xilinx-platform-init - -COMPATIBLE_MACHINE = "$^" -COMPATIBLE_MACHINE_picozed-zynq7 = "picozed-zynq7" - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6" - -PROVIDES += "virtual/xilinx-platform-init" - -SRC_URI = "${@" ".join(["file://%s" % f for f in (d.getVar('PLATFORM_INIT_FILES') or "").split()])}" - -S = "${WORKDIR}" - -SYSROOT_DIRS += "${PLATFORM_INIT_DIR}" - -do_compile() { - : -} - -do_install() { - install -d ${D}${PLATFORM_INIT_DIR} - for i in ${PLATFORM_INIT_FILES}; do - install -m 0644 ${S}/$i ${D}${PLATFORM_INIT_DIR}/ - done -} - -FILES_${PN} += "${PLATFORM_INIT_DIR}/*" - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c deleted file mode 100644 index 5587ab25c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c +++ /dev/null @@ -1,13191 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x0 - // .. ==> 0XF8000B6C[11:10] = 0x00000000U - // .. ==> MASK : 0x00000C00U VAL : 0x00000000U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x0 - // .. ==> 0XF8000B6C[11:10] = 0x00000000U - // .. ==> MASK : 0x00000C00U VAL : 0x00000000U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} - - - - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h deleted file mode 100644 index df5205e81..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h +++ /dev/null @@ -1,130 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 100000000 -#define FPGA2_FREQ 33333336 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif - - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb deleted file mode 100644 index 195c63090..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb +++ /dev/null @@ -1,41 +0,0 @@ -SUMMARY = "PMU ROM for QEMU" -DESCRIPTION = "The ZynqMP PMU ROM for QEMU emulation" -HOMEPAGE = "http://www.xilinx.com" -SECTION = "bsp" - -# The BSP package does not include any license information. -LICENSE = "Proprietary" -LICENSE_FLAGS = "xilinx" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" - -COMPATIBLE_MACHINE = "zcu102-zynqmp" - -inherit deploy -inherit xilinx-fetch-restricted - -BSP_NAME = "xilinx-zcu102" -BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" -SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" -SRC_URI[md5sum] = "cea5f11761e7f38cbfcf0a07a19094e0" -SRC_URI[sha256sum] = "7ac0ac3a5fb7dd162c0a922c66edb33b5737955ef6570a1a1d3b15b4344f7cc1" - -INHIBIT_DEFAULT_DEPS = "1" -PACKAGE_ARCH = "${MACHINE_ARCH}" - -do_compile() { - # Extract the rom into workdir - tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-${PV}/pre-built/linux/images/pmu_rom_qemu_sha3.elf -C ${S} - # tar preserves the tree, so use find to get the full path and move to to the root - for i in $(find ${S} -type f -name *.elf); do mv $i ${S}/pmu-rom.elf; done -} - -do_install() { - : -} - -do_deploy () { - install -D ${S}/pmu-rom.elf ${DEPLOYDIR}/pmu-rom.elf -} - -addtask deploy before do_build after do_install - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2020.2.bb deleted file mode 100644 index 6a2ca7cc4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2020.2.bb +++ /dev/null @@ -1,48 +0,0 @@ -SUMMARY = "KC705 Pre-built Bitstream" -DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system." -HOMEPAGE = "http://www.xilinx.com" -SECTION = "bsp" - -# The BSP package does not include any license information. -LICENSE = "Proprietary" -LICENSE_FLAGS = "xilinx" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" - -COMPATIBLE_MACHINE = "kc705-microblazeel" - -inherit deploy -inherit xilinx-fetch-restricted - -BSP_NAME = "xilinx-kc705" -BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" -SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" -SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351" -SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773" - -PROVIDES = "virtual/bitstream" - -FILES_${PN} += "/boot/download.bit" - -INHIBIT_DEFAULT_DEPS = "1" -PACKAGE_ARCH = "${MACHINE_ARCH}" - -# deps needed to extract content from the .bsp file -DEPENDS += "tar-native gzip-native" - -do_compile() { - # Extract the bitstream into workdir - tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S} - # move the bit file to ${S}/ as it is in a subdir in the tar file - for i in $(find -type f -name download.bit); do mv $i ${S}; done -} - -do_install() { - install -D ${S}/download.bit ${D}/boot/download.bit -} - -do_deploy () { - install -D ${S}/download.bit ${DEPLOYDIR}/download.bit -} - -addtask deploy before do_build after do_install - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch deleted file mode 100644 index 7091098ca..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 8127b19aa42ccfb3faae1173a12b3eb0cebf8941 Mon Sep 17 00:00:00 2001 -From: Peter Robinson <pbrobinson@gmail.com> -Date: Thu, 30 Jan 2020 09:37:15 +0000 -Subject: [PATCH] Remove redundant YYLOC global declaration - -Same as the upstream fix for building dtc with gcc 10. - -Signed-off-by: Peter Robinson <pbrobinson@gmail.com> -State: upstream (e33a814e772cdc36436c8c188d8c42d019fda639) ---- - scripts/dtc/dtc-lexer.l | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l -index fd825ebba6..24af549977 100644 ---- a/scripts/dtc/dtc-lexer.l -+++ b/scripts/dtc/dtc-lexer.l -@@ -38,7 +38,6 @@ LINECOMMENT "//".*\n - #include "srcpos.h" - #include "dtc-parser.tab.h" - --YYLTYPE yylloc; - extern bool treesource_error; - - /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ --- -2.29.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc deleted file mode 100644 index 97c449bd3..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc +++ /dev/null @@ -1,70 +0,0 @@ -inherit xilinx-platform-init - -FORCE_PLATFORM_INIT[doc] = "This variable is used to force the overriding of all platform init files in u-boot source." - -PLATFORM_BOARD_DIR ?= "" -PLATFORM_BOARD_DIR_zynq = "board/xilinx/zynq" -PLATFORM_BOARD_DIR_zynqmp = "board/xilinx/zynqmp" - -do_zynq_platform_init() { - for f in ${PLATFORM_INIT_FILES}; do - if [ -d "${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform" ]; then - cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform/ - else - cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/ - fi - # Newer u-boot sources use the init files in a sub directory named - # based on the name of the device tree. This is not straight forward to - # detect. Instead of detecting just overwrite all the platform init - # files so that the correct one is always used. This shotgun approach - # only works due to this recipe being machine arch specific. Do this - # overwrite un-conditionally as there is no guarantees that the chosen - # board config does not have the device tree config set. - for i in ${S}/${PLATFORM_BOARD_DIR}/*/; do - [ -d $i ] && cp ${PLATFORM_INIT_STAGE_DIR}/$f $i - done - done -} - -python () { - # strip the tail _config/_defconfig for better comparison - def strip_config_name(c): - for i in ["_config", "_defconfig"]: - if c.endswith(i): - return c[0:len(c) - len(i)] - return c - - if d.getVar("SOC_FAMILY") not in ["zynq", "zynqmp"]: - # continue on this is not a zynq/zynqmp target - return - - # Determine if target machine needs to provide a custom platform init files - if d.getVar("SPL_BINARY"): - hasconfigs = [strip_config_name(c) for c in (d.getVar("HAS_PLATFORM_INIT") or "").split()] - currentconfig = strip_config_name(d.getVar("UBOOT_MACHINE")) - - # only add the dependency if u-boot doesn't already provide the platform init files - if (currentconfig not in hasconfigs) or (d.getVar("FORCE_PLATFORM_INIT") == "1"): - # force the dependency on a recipe that provides the platform init files - d.appendVar("DEPENDS", " virtual/xilinx-platform-init") - # setup task to modify platform init after unpack and prepare_recipe_sysroot, and before configure - bb.build.addtask("do_zynq_platform_init", "do_configure", "do_unpack do_prepare_recipe_sysroot", d) - - if "boot.bin" not in d.getVar("SPL_BINARY"): - # not deploying the boot.bin, just building SPL - return - - # assume that U-Boot is to provide the boot.bin if no other provides are selected or U-Boot is selected - providesbin = not(d.getVar("PREFERRED_PROVIDER_virtual/boot-bin")) or d.getVar("PREFERRED_PROVIDER_virtual/boot-bin") == d.getVar("PN") - if providesbin: - # add provides, if U-Boot is set to provide boot.bin - d.appendVar("PROVIDES", " virtual/boot-bin") - else: - # prevent U-Boot from deploying the boot.bin - d.setVar("SPL_BINARY", "") - - if providesbin and d.getVar("SOC_FAMILY") in ["zynqmp"]: - # setup PMU Firmware path via MAKEFLAGS - d.appendVar("EXTRA_OEMAKE", " CONFIG_PMUFW_INIT_FILE=\"{0}\"".format("${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}.bin")) -} - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb deleted file mode 100644 index 3e40bfa17..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb +++ /dev/null @@ -1,28 +0,0 @@ -# This recipe allows for a 'bleeding edge' u-boot-xlnx build. -# Since this tree is frequently updated, AUTOREV is used to track its contents. -# -# To enable this recipe, set the following in your machine or local.conf -# PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx-dev" - -UBRANCH ?= "master" - -include u-boot-xlnx.inc -include u-boot-spl-zynq-init.inc - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c" - -SRCREV_DEFAULT = "aebea9d20a5aa32857f320c07ca8f9fd1b3dec1f" -SRCREV ?= "${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/bootloader", "u-boot-xlnx-dev", "${AUTOREV}", "${SRCREV_DEFAULT}", d)}" - -PV = "${UBRANCH}-xilinx-dev+git${SRCPV}" - -# Newer versions of u-boot have support for these -HAS_PLATFORM_INIT ?= " \ - zynq_microzed_config \ - zynq_zed_config \ - zynq_zc702_config \ - zynq_zc706_config \ - zynq_zybo_config \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc deleted file mode 100644 index 4b8c4efee..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc +++ /dev/null @@ -1,20 +0,0 @@ -require recipes-bsp/u-boot/u-boot.inc - -DEPENDS += "bc-native dtc-native bison-native" - -XILINX_RELEASE_VERSION ?= "" -UBOOT_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" -PV = "${UBOOT_VERSION}${UBOOT_VERSION_EXTENSION}+git${SRCPV}" - -UBOOTURI ?= "git://github.com/Xilinx/u-boot-xlnx.git;protocol=https" -UBRANCH ?= "" -UBRANCHARG = "${@['nobranch=1', 'branch=${UBRANCH}'][d.getVar('UBRANCH', True) != '']}" - -SRC_URI = "${UBOOTURI};${UBRANCHARG}" - -S = "${WORKDIR}/git" -B = "${WORKDIR}/build" - -FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot:" - -SYSROOT_DIRS += "/boot" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2020.2.bb deleted file mode 100644 index 95c7254c6..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2020.2.bb +++ /dev/null @@ -1,23 +0,0 @@ -UBOOT_VERSION = "v2020.01" - -UBRANCH ?= "xlnx_rebase_v2020.01" - -SRCREV ?= "bb4660c33aa7ea64f78b2682bf0efd56765197d6" - -include u-boot-xlnx.inc -include u-boot-spl-zynq-init.inc - -# Patch required for latest gcc and 2020.2 version of u-boot-xlnx -# This will be removed once the SRCREV above has been updated to include this change -SRC_URI += " file://0001-Remove-redundant-YYLOC-global-declaration.patch" - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" - -# u-boot-xlnx has support for these -HAS_PLATFORM_INIT ?= " \ - xilinx_zynqmp_virt_config \ - xilinx_zynq_virt_defconfig \ - xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb deleted file mode 100644 index e8b91922b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ /dev/null @@ -1,96 +0,0 @@ -SUMMARY = "U-boot boot scripts for Xilinx devices" -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" - -DEPENDS = "u-boot-mkimage-native" - -inherit deploy nopackages image-wic-utils - -INHIBIT_DEFAULT_DEPS = "1" - -COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" -COMPATIBLE_MACHINE_zynq = "zynq" -COMPATIBLE_MACHINE_versal = "versal" - -KERNELDT = "${@os.path.basename(d.getVar('KERNEL_DEVICETREE').split(' ')[0]) if d.getVar('KERNEL_DEVICETREE') else ''}" -DEVICE_TREE_NAME ?= "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', d.getVar('KERNELDT'), d)}" -#Need to copy a rootfs.cpio.gz.u-boot as uramdisk.image.gz into boot partition -RAMDISK_IMAGE ?= "" -RAMDISK_IMAGE_zynq ?= "uramdisk.image.gz" - -KERNEL_BOOTCMD_zynqmp ?= "booti" -KERNEL_BOOTCMD_zynq ?= "bootm" -KERNEL_BOOTCMD_versal ?= "booti" - -BOOTMODE ?= "sd" - -SRC_URI = " \ - file://boot.cmd.sd.zynq \ - file://boot.cmd.sd.zynqmp \ - file://boot.cmd.sd.versal \ - file://boot.cmd.qspi.versal \ - file://pxeboot.pxe \ - " -PACKAGE_ARCH = "${MACHINE_ARCH}" - -UBOOTSCR_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}${IMAGE_VERSION_SUFFIX}" -UBOOTPXE_CONFIG ?= "pxelinux.cfg" -UBOOTPXE_CONFIG_NAME = "${UBOOTPXE_CONFIG}${IMAGE_VERSION_SUFFIX}" - -DEVICETREE_ADDRESS_zynqmp ?= "0x100000" -DEVICETREE_ADDRESS_zynq ?= "0x2000000" -DEVICETREE_ADDRESS_versal ?= "0x1000" -KERNEL_LOAD_ADDRESS_zynqmp ?= "0x200000" -KERNEL_LOAD_ADDRESS_zynq ?= "0x2080000" -KERNEL_LOAD_ADDRESS_versal ?= "0x80000" - -RAMDISK_IMAGE_ADDRESS_zynq ?= "0x4000000" -RAMDISK_IMAGE_ADDRESS_versal ?= "0x6000000" - - -SDBOOTDEV ?= "0" - -BITSTREAM_LOAD_ADDRESS ?= "0x100000" - -do_configure[noexec] = "1" -do_install[noexec] = "1" - -def get_bitstream_load_type(d): - if boot_files_bitstream(d)[1] : - return "loadb" - else: - return "load" - -do_compile() { - sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \ - -e 's/@@KERNEL_LOAD_ADDRESS@@/${KERNEL_LOAD_ADDRESS}/' \ - -e 's/@@DEVICE_TREE_NAME@@/${DEVICE_TREE_NAME}/' \ - -e 's/@@DEVICETREE_ADDRESS@@/${DEVICETREE_ADDRESS}/' \ - -e 's/@@RAMDISK_IMAGE@@/${RAMDISK_IMAGE}/' \ - -e 's/@@RAMDISK_IMAGE_ADDRESS@@/${RAMDISK_IMAGE_ADDRESS}/' \ - -e 's/@@KERNEL_BOOTCMD@@/${KERNEL_BOOTCMD}/' \ - -e 's/@@SDBOOTDEV@@/${SDBOOTDEV}/' \ - -e 's/@@BITSTREAM@@/${@boot_files_bitstream(d)[0]}/g' \ - -e 's/@@BITSTREAM_LOAD_ADDRESS@@/${BITSTREAM_LOAD_ADDRESS}/g' \ - -e 's/@@BITSTREAM_IMAGE@@/${@boot_files_bitstream(d)[0]}/g' \ - -e 's/@@BITSTREAM_LOAD_TYPE@@/${@get_bitstream_load_type(d)}/g' \ - "${WORKDIR}/boot.cmd.${BOOTMODE}.${SOC_FAMILY}" > "${WORKDIR}/boot.cmd" - mkimage -A arm -T script -C none -n "Boot script" -d "${WORKDIR}/boot.cmd" boot.scr - sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \ - -e 's/@@DEVICE_TREE_NAME@@/${DEVICE_TREE_NAME}/' \ - -e 's/@@RAMDISK_IMAGE@@/${RAMDISK_IMAGE}/' \ - "${WORKDIR}/pxeboot.pxe" > "pxeboot.pxe" -} - - -do_deploy() { - install -d ${DEPLOYDIR} - install -m 0644 boot.scr ${DEPLOYDIR}/${UBOOTSCR_BASE_NAME}.scr - ln -sf ${UBOOTSCR_BASE_NAME}.scr ${DEPLOYDIR}/boot.scr - install -d ${DEPLOYDIR}/pxeboot/${UBOOTPXE_CONFIG_NAME} - install -m 0644 pxeboot.pxe ${DEPLOYDIR}/pxeboot/${UBOOTPXE_CONFIG_NAME}/default - ln -sf pxeboot/${UBOOTPXE_CONFIG_NAME} ${DEPLOYDIR}/${UBOOTPXE_CONFIG} -} - -addtask do_deploy after do_compile before do_build diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal deleted file mode 100644 index d56b7c8cd..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal +++ /dev/null @@ -1 +0,0 @@ -@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal deleted file mode 100644 index 10e83cd09..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal +++ /dev/null @@ -1,3 +0,0 @@ -setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused -fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ -@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq deleted file mode 100644 index bbd2e01e9..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq +++ /dev/null @@ -1,7 +0,0 @@ -if test -n "@@BITSTREAM@@"; then - fatload mmc $sdbootdev @@BITSTREAM_LOAD_ADDRESS@@ @@BITSTREAM_IMAGE@@ && fpga @@BITSTREAM_LOAD_TYPE@@ 0 @@BITSTREAM_LOAD_ADDRESS@@ ${filesize} -fi -fatload mmc 0 @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@ -fatload mmc 0 @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ -fatload mmc 0 @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@ -@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp deleted file mode 100644 index 43062ce8f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp +++ /dev/null @@ -1,9 +0,0 @@ -setenv sdbootdev @@SDBOOTDEV@@ -setenv bootargs $bootargs root=/dev/mmcblk${sdbootdev}p2 rw rootwait earlycon clk_ignore_unused -setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait earlycon clk_ignore_unused -if test -n "@@BITSTREAM@@"; then - fatload mmc $sdbootdev @@BITSTREAM_LOAD_ADDRESS@@ @@BITSTREAM_IMAGE@@ && fpga @@BITSTREAM_LOAD_TYPE@@ 0 @@BITSTREAM_LOAD_ADDRESS@@ ${filesize} -fi -fatload mmc $sdbootdev @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@ -fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ -@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe deleted file mode 100644 index 407965453..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe +++ /dev/null @@ -1,4 +0,0 @@ -LABEL Linux -KERNEL @@KERNEL_IMAGETYPE@@ -FDT @@DEVICE_TREE_NAME@@ -INITRD @@RAMDISK_IMAGE@@ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb deleted file mode 100644 index 6e4c3c0b2..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb +++ /dev/null @@ -1,110 +0,0 @@ -SUMMARY = "U-Boot uEnv.txt SD boot environment generation for Zynq targets" -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" - -INHIBIT_DEFAULT_DEPS = "1" -PACKAGE_ARCH = "${MACHINE_ARCH}" - -python () { - # The device trees must be populated in the deploy directory to correctly - # detect them and their names. This means that this recipe needs to depend - # on those deployables just like the image recipe does. - deploydeps = ["virtual/kernel"] - for i in (d.getVar("MACHINE_ESSENTIAL_EXTRA_RDEPENDS") or "").split(): - if i != d.getVar("BPN"): - deploydeps.append(i) - for i in (d.getVar("EXTRA_IMAGEDEPENDS") or "").split(): - if i != d.getVar("BPN"): - deploydeps.append(i) - - # add as DEPENDS since the targets might not have do_deploy tasks - if len(deploydeps) != 0: - d.appendVar("DEPENDS", " " + " ".join(deploydeps)) -} - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynq = ".*" -COMPATIBLE_MACHINE_zynqmp = ".*" - -inherit deploy image-wic-utils - -def uboot_boot_cmd(d): - if d.getVar("KERNEL_IMAGETYPE") in ["uImage", "fitImage"]: - return "bootm" - if d.getVar("KERNEL_IMAGETYPE") in ["zImage"]: - return "bootz" - if d.getVar("KERNEL_IMAGETYPE") in ["Image"]: - return "booti" - raise bb.parse.SkipRecipe("Unsupport kernel image type") - -def get_sdbootdev(d): - if d.getVar("SOC_FAMILY") in ["zynqmp"]: - return "${sdbootdev}" - else: - return "0" - -def uenv_populate(d): - # populate the environment values - env = {} - - env["machine_name"] = d.getVar("MACHINE") - - env["kernel_image"] = d.getVar("KERNEL_IMAGETYPE") - env["kernel_load_address"] = d.getVar("KERNEL_LOAD_ADDRESS") - - env["devicetree_image"] = boot_files_dtb_filepath(d) - env["devicetree_load_address"] = d.getVar("DEVICETREE_LOAD_ADDRESS") - - env["bootargs"] = d.getVar("KERNEL_BOOTARGS") - - env["loadkernel"] = "fatload mmc " + get_sdbootdev(d) + " ${kernel_load_address} ${kernel_image}" - env["loaddtb"] = "fatload mmc " + get_sdbootdev(d) + " ${devicetree_load_address} ${devicetree_image}" - env["bootkernel"] = "run loadkernel && run loaddtb && " + uboot_boot_cmd(d) + " ${kernel_load_address} - ${devicetree_load_address}" - - if d.getVar("SOC_FAMILY") in ["zynqmp"]: - env["bootkernel"] = "setenv bootargs " + d.getVar("KERNEL_BOOTARGS") + " ; " + env["bootkernel"] - - # default uenvcmd does not load bitstream - env["uenvcmd"] = "run bootkernel" - - bitstream, bitstreamtype = boot_files_bitstream(d) - if bitstream: - env["bitstream_image"] = bitstream - env["bitstream_load_address"] = "0x100000" - - # if bitstream is "bit" format use loadb, otherwise use load - env["bitstream_type"] = "loadb" if bitstreamtype else "load" - - # load bitstream first with loadfpa - env["loadfpga"] = "fatload mmc " + get_sdbootdev(d) + " ${bitstream_load_address} ${bitstream_image} && fpga ${bitstream_type} 0 ${bitstream_load_address} ${filesize}" - env["uenvcmd"] = "run loadfpga && run bootkernel" - - return env - -# bootargs, default to booting with the rootfs device being partition 2 -KERNEL_BOOTARGS_zynq = "earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait" -KERNEL_BOOTARGS_zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk${sdbootdev}p2 rw rootwait" - -KERNEL_LOAD_ADDRESS_zynq = "0x2080000" -KERNEL_LOAD_ADDRESS_zynqmp = "0x80000" -DEVICETREE_LOAD_ADDRESS_zynq = "0x2000000" -DEVICETREE_LOAD_ADDRESS_zynqmp = "0x4000000" - -python do_compile() { - env = uenv_populate(d) - with open(d.expand("${WORKDIR}/uEnv.txt"), "w") as f: - for k, v in env.items(): - f.write("{0}={1}\n".format(k, v)) -} - -FILES_${PN} += "/boot/uEnv.txt" - -do_install() { - install -Dm 0644 ${WORKDIR}/uEnv.txt ${D}/boot/uEnv.txt -} - -do_deploy() { - install -Dm 0644 ${WORKDIR}/uEnv.txt ${DEPLOYDIR}/uEnv.txt -} -addtask do_deploy after do_compile before do_build - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend deleted file mode 100644 index b85223699..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ /dev/null @@ -1,11 +0,0 @@ -include u-boot-spl-zynq-init.inc - -# u-boot 2016.11 has support for these -HAS_PLATFORM_INIT ??= " \ - zynq_microzed_config \ - zynq_zed_config \ - zynq_zc702_config \ - zynq_zc706_config \ - zynq_zybo_config \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-core/glibc/glibc-locale_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-core/glibc/glibc-locale_%.bbappend deleted file mode 100644 index 68ae89b4d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-core/glibc/glibc-locale_%.bbappend +++ /dev/null @@ -1,4 +0,0 @@ -do_install_append() { - # Remove the libdir if it is empty when gconv is not copied - find ${D}${libdir} -type d -empty -delete -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-Add-enable-disable-udev.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-Add-enable-disable-udev.patch deleted file mode 100644 index f38862fac..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-Add-enable-disable-udev.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 96f204df74f7dde5f4c9ad6e6eefc2d46219ccd9 Mon Sep 17 00:00:00 2001 -From: Jeremy Puhlman <jpuhlman@mvista.com> -Date: Thu, 19 Mar 2020 11:54:26 -0700 -Subject: [PATCH] Add enable/disable libudev - -Upstream-Status: Pending -Signed-off-by: Jeremy Puhlman <jpuhlman@mvista.com> - -%% original patch: 0001-Add-enable-disable-udev.patch ---- - configure | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/configure b/configure -index c9a4e73..75f9773 100755 ---- a/configure -+++ b/configure -@@ -1606,6 +1606,10 @@ for opt do - ;; - --gdb=*) gdb_bin="$optarg" - ;; -+ --enable-libudev) libudev="yes" -+ ;; -+ --disable-libudev) libudev="no" -+ ;; - *) - echo "ERROR: unknown option $opt" - echo "Try '$0 --help' for more information" --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch deleted file mode 100644 index a8ab7daa4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 5214dd4461f2090ef0965b4d2518f49927d61cbc Mon Sep 17 00:00:00 2001 -From: He Zhe <zhe.he@windriver.com> -Date: Wed, 28 Aug 2019 19:56:28 +0800 -Subject: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt - -libgcrypt may also be controlled by pkg-config, this patch adds pkg-config -handling for libgcrypt. - -Upstream-Status: Denied [https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg06333.html] - -Signed-off-by: He Zhe <zhe.he@windriver.com> ---- - configure | 48 ++++++++++++++++++++++++++++++++++++++++-------- - 1 file changed, 40 insertions(+), 8 deletions(-) - -diff --git a/configure b/configure -index e44e454..0f362a7 100755 ---- a/configure -+++ b/configure -@@ -2875,6 +2875,30 @@ has_libgcrypt() { - return 0 - } - -+has_libgcrypt_pkgconfig() { -+ if ! has $pkg_config ; then -+ return 1 -+ fi -+ -+ if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then -+ return 1 -+ fi -+ -+ if test -n "$cross_prefix" ; then -+ host=$($pkg_config --variable=host libgcrypt) -+ if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then -+ print_error "host($host) does not match cross_prefix($cross_prefix)" -+ return 1 -+ fi -+ fi -+ -+ if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then -+ print_error "libgcrypt version is $($pkg_config --modversion libgcrypt)" -+ return 1 -+ fi -+ -+ return 0 -+} - - if test "$nettle" != "no"; then - pass="no" -@@ -2902,7 +2926,14 @@ fi - - if test "$gcrypt" != "no"; then - pass="no" -- if has_libgcrypt; then -+ if has_libgcrypt_pkgconfig; then -+ gcrypt_cflags=$($pkg_config --cflags libgcrypt) -+ if test "$static" = "yes" ; then -+ gcrypt_libs=$($pkg_config --libs --static libgcrypt) -+ else -+ gcrypt_libs=$($pkg_config --libs libgcrypt) -+ fi -+ elif has_libgcrypt; then - gcrypt_cflags=$(libgcrypt-config --cflags) - gcrypt_libs=$(libgcrypt-config --libs) - # Debian has removed -lgpg-error from libgcrypt-config -@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then - then - gcrypt_libs="$gcrypt_libs -lgpg-error" - fi -+ fi - -- # Link test to make sure the given libraries work (e.g for static). -- write_c_skeleton -- if compile_prog "" "$gcrypt_libs" ; then -- LIBS="$gcrypt_libs $LIBS" -- QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags" -- pass="yes" -- fi -+ # Link test to make sure the given libraries work (e.g for static). -+ write_c_skeleton -+ if compile_prog "" "$gcrypt_libs" ; then -+ LIBS="$gcrypt_libs $LIBS" -+ QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags" -+ pass="yes" - fi -+ - if test "$pass" = "yes"; then - gcrypt="yes" - cat > $TMPC << EOF --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/flash_stripe.c b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/flash_stripe.c deleted file mode 100644 index a9a6e76a5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/flash_stripe.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Stripe a flash image across multiple files. - * - * Copyright (C) 2019 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include <stdio.h> -#include <stdlib.h> -#include <stdint.h> -#include <stdbool.h> -#include <unistd.h> -#include <sys/types.h> -#include <sys/stat.h> -#include <fcntl.h> -#include <string.h> - -/* N way (num) in place bit striper. Lay out row wise bits column wise - * (from element 0 to N-1). num is the length of x, and dir reverses the - * direction of the transform. be determines the bit endianess scheme. - * false to lay out bits LSB to MSB (little endian) and true for big endian. - * - * Best illustrated by examples: - * Each digit in the below array is a single bit (num == 3, be == false): - * - * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} - * - * Same but with be == true: - * - * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } - * { hgfedcba, } { 630fcHEB, } - * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} - */ - -static inline void stripe8(uint8_t *x, int num, bool dir, bool be) -{ - uint8_t r[num]; - memset(r, 0, sizeof(uint8_t) * num); - int idx[2] = {0, 0}; - int bit[2] = {0, be ? 7 : 0}; - int d = dir; - - for (idx[0] = 0; idx[0] < num; ++idx[0]) { - for (bit[0] = be ? 7 : 0; bit[0] != (be ? -1 : 8); bit[0] += be ? -1 : 1) { - r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; - idx[1] = (idx[1] + 1) % num; - if (!idx[1]) { - bit[1] += be ? -1 : 1; - } - } - } - memcpy(x, r, sizeof(uint8_t) * num); -} - -int main (int argc, char *argv []) { -#ifdef UNSTRIPE - bool unstripe = true; -#else - bool unstripe = false; -#endif - -#ifdef FLASH_STRIPE_BE - bool be = true; -#else - bool be = false; -#endif - - int i; - - const char *exe_name = argv[0]; - argc--; - argv++; - - if (argc < 2) { - fprintf(stderr, "ERROR: %s requires at least two args\n", exe_name); - return 1; - } - - const char *single_f = argv[0]; - int single; - - if (unstripe) { - single = creat(single_f, 0644); - } else { - single = open(single_f, 0); - } - if (single == -1) { - perror(argv[0]); - return 1; - } - - argv++; - argc--; - - int multiple[argc]; - - for (i = 0; i < argc; ++i) { - if (unstripe) { - multiple[i] = open(argv[i], 0); - } else { - multiple[i] = creat(argv[i], 0644); - } - if (multiple[i] == -1) { - perror(argv[i]); - return 1; - } - } - - while (true) { - uint8_t buf[argc]; - for (i = 0; i < argc; ++i) { - switch (read(!unstripe ? single : multiple[ -#if defined(FLASH_STRIPE_BW) && defined (FLASH_STRIPE_BE) - argc - 1 - -#endif - i], &buf[i], 1)) { - case 0: - if (i == 0) { - goto done; - } else if (!unstripe) { - fprintf(stderr, "WARNING:input file %s is not multiple of " - "%d bytes, padding with garbage byte\n", single_f, - argc); - } - break; - case -1: - perror(unstripe ? argv[i] : single_f); - return 1; - } - } - -#ifndef FLASH_STRIPE_BW - stripe8(buf, argc, unstripe, be); -#endif - - for (i = 0; i < argc; ++i) { - switch (write(unstripe ? single : multiple[ -#if defined(FLASH_STRIPE_BW) && defined (FLASH_STRIPE_BE) - argc - 1 - -#endif - i], &buf[i], 1)) { - case -1: - perror(unstripe ? single_f : argv[i]); - return 1; - case 0: - i--; /* try again */ - } - } - } - -done: - close(single); - for (i = 0; i < argc; ++i) { - close(multiple[argc]); - } - return 0; -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch deleted file mode 100644 index 6f7fb5225..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env python3 - -# Xilinx QEMU wrapper to launch both PMU and APU instances (multiarch) -import os -import subprocess -import sys -import tempfile -import shutil - -binpath = os.path.dirname(os.path.abspath(__file__)) -mach_path = tempfile.mkdtemp() - - -# Separate PMU and APU arguments -APU_args = sys.argv[1:] -mbtype='' - -if '-pmu-args' in APU_args: - MB_args = APU_args[APU_args.index('-pmu-args')+1] - APU_args.remove('-pmu-args') - APU_args.remove(MB_args) - MB_args = MB_args.split() - PMU_rom = MB_args[MB_args.index('-kernel')+1] - mbtype='PMU' -elif '-plm-args' in APU_args: - MB_args = APU_args[APU_args.index('-plm-args')+1] - APU_args.remove('-plm-args') - APU_args.remove(MB_args) - MB_args = MB_args.split() - mbtype='PLM' -else: - error_msg = '\nMultiarch not setup properly.' - sys.exit(error_msg) - -error_msg = None -if (mbtype == 'PMU' and os.path.exists(PMU_rom)) or mbtype == 'PLM': - - # We need to switch tcp serial arguments (if they exist, e.g. qemurunner) to get the output correctly - tcp_serial_ports = [i for i, s in enumerate(APU_args) if 'tcp:127.0.0.1:' in s] - - #NEED TO FIX for next yocto release (dont need to switch ports anymore, they will be provided correctly upstream - # We can only switch these if there are exactly two, otherwise we can't assume what is being executed so we leave it as is - if len(tcp_serial_ports) == 2: - APU_args[tcp_serial_ports[0]],APU_args[tcp_serial_ports[1]] = APU_args[tcp_serial_ports[1]],APU_args[tcp_serial_ports[0]] - - mb_cmd = binpath + '/qemu-system-microblazeel ' + ' '.join(MB_args) + ' -machine-path ' + mach_path - apu_cmd = binpath + '/qemu-system-aarch64 ' + ' '.join(APU_args) + ' -machine-path ' + mach_path - - # Debug prints - print('\n%s instance cmd: %s\n' % (mbtype, mb_cmd)) - print('APU instance cmd: %s\n' % apu_cmd) - - - # Invoke QEMU pmu instance - process_pmu = subprocess.Popen(mb_cmd, shell=True, stderr=subprocess.PIPE) - - # Invoke QEMU APU instance - process_apu = subprocess.Popen(apu_cmd, shell=True, stderr=subprocess.PIPE) - if process_apu.wait(): - error_msg = '\nQEMU APU instance failed:\n%s' % process_apu.stderr.read().decode() - -else: - if mbtype == 'PMU': - error_msg = '\nError: Missing PMU ROM: %s' % PMU_rom - error_msg += '\nSee "meta-xilinx/README.qemu.md" for more information on accquiring the PMU ROM.\n' - -shutil.rmtree(mach_path) -sys.exit(error_msg) diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/flashstrip_1.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/flashstrip_1.0.bb deleted file mode 100644 index eec7b2dad..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/flashstrip_1.0.bb +++ /dev/null @@ -1,25 +0,0 @@ -SUMMARY = "Building and installing flash strip utility" -DESCRIPTION = "Building and installing flash strip utility" - -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://../flash_stripe.c;beginline=1;endline=23;md5=abb859d98b7c4eede655e1b71824125a" - -B = "${WORKDIR}/build" - -SRC_URI += "file://flash_stripe.c" - -TARGET_CC_ARCH += "${LDFLAGS}" - -do_compile() { - ${CC} ${WORKDIR}/flash_stripe.c -o flash_strip - ${CC} ${WORKDIR}/flash_stripe.c -o flash_unstrip - ${CC} ${WORKDIR}/flash_stripe.c -o flash_strip_bw -DFLASH_STRIPE_BW - ${CC} ${WORKDIR}/flash_stripe.c -o flash_unstrip_bw -DUNSTRIP -DFLASH_STRIPE_BW -} - -do_install() { - install -d ${D}${bindir} - install -Dm 0755 ${B}/* ${D}${bindir}/ -} - -FILES_${PN} = "${bindir}/*" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees.inc deleted file mode 100644 index 8e752921a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees.inc +++ /dev/null @@ -1,40 +0,0 @@ -SUMMARY = "Xilinx's hardware device trees required for QEMU" -HOMEPAGE = "https://github.com/xilinx/qemu-devicetrees/" -LICENSE = "BSD" -DEPENDS += "dtc-native" - -inherit deploy - -LIC_FILES_CHKSUM = "file://Makefile;beginline=1;endline=27;md5=7348b6cbcae69912cb1dee68d6c68d99" - -PV = "xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" -SRC_URI_append = " file://0001-Makefile-Use-python3-instead-of-python.patch" - -BRANCH ?= "" -REPO ?= "git://github.com/Xilinx/qemu-devicetrees.git;protocol=https" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -S = "${WORKDIR}/git" - -# Don't need to do anything -do_install() { - : -} - -do_deploy() { - # single-arch dtbs - for DTS_FILE in ${S}/LATEST/SINGLE_ARCH/*.dtb; do - install -Dm 0644 $DTS_FILE ${DEPLOYDIR}/qemu-hw-devicetrees/$(basename $DTS_FILE .dtb).dtb - done - - # multi-arch dtbs - for DTS_FILE in ${S}/LATEST/MULTI_ARCH/*.dtb; do - install -Dm 0644 $DTS_FILE ${DEPLOYDIR}/qemu-hw-devicetrees/multiarch/$(basename $DTS_FILE .dtb).dtb - done -} - -addtask deploy after do_install diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch deleted file mode 100644 index afbe31560..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch +++ /dev/null @@ -1,30 +0,0 @@ -From e5af9cc9b167acc5c04d15fea03b34b70ec537c9 Mon Sep 17 00:00:00 2001 -From: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> -Date: Sun, 7 Jun 2020 20:35:59 -0700 -Subject: [PATCH] Makefile:Use python3 instead of python - -Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> ---- - Makefile | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/Makefile b/Makefile -index 36b4937..efaa39a 100644 ---- a/Makefile -+++ b/Makefile -@@ -89,9 +89,9 @@ $(LQSPI_XIP_OUTDIR)/%.dts: %.dts $(DTSI_FILES) $(HEADER_FILES) - # TODO: Add support for auto-generated dependency list - versal-pmc-npi.dtsi: versal-pmc-npi-nxx.dtsi - versal-pmc-npi-nxx.dtsi: Makefile -- @python -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@ -- @python -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@ -- @python -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@ -+ @python3 -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@ -+ @python3 -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@ -+ @python3 -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@ - - clean: - $(RM) versal-pmc-npi-nxx.dtsi --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2020.2.bb deleted file mode 100644 index c7fc70b3e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2020.2.bb +++ /dev/null @@ -1,4 +0,0 @@ -require qemu-devicetrees.inc - -BRANCH ?= "branch/xilinx-v2020.2" -SRCREV ?= "0097f0f651d67b3a8495693e9e17c443948d3c77" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-native.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-native.inc deleted file mode 100644 index aa5c9b9a7..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-native.inc +++ /dev/null @@ -1,11 +0,0 @@ -inherit native - -require qemu.inc - -EXTRA_OEMAKE_append = " LD='${LD}' AR='${AR}' OBJCOPY='${OBJCOPY}' LDFLAGS='${LDFLAGS}'" - -LDFLAGS_append = " -fuse-ld=bfd" - -do_install_append() { - ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)} -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-targets.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-targets.inc deleted file mode 100644 index 24f9a0394..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-targets.inc +++ /dev/null @@ -1,28 +0,0 @@ -# possible arch values are: -# aarch64 arm armeb alpha cris i386 x86_64 m68k microblaze -# mips mipsel mips64 mips64el ppc ppc64 ppc64abi32 ppcemb -# riscv32 riscv64 sparc sparc32 sparc32plus - -def get_qemu_target_list(d): - import bb - archs = d.getVar('QEMU_TARGETS').split() - tos = d.getVar('HOST_OS') - softmmuonly = "" - for arch in ['ppcemb', 'lm32']: - if arch in archs: - softmmuonly += arch + "-softmmu," - archs.remove(arch) - linuxuseronly = "" - for arch in ['armeb', 'alpha', 'ppc64abi32', 'ppc64le', 'sparc32plus', 'aarch64_be']: - if arch in archs: - linuxuseronly += arch + "-linux-user," - archs.remove(arch) - if 'linux' not in tos: - return softmmuonly + ''.join([arch + "-softmmu" + "," for arch in archs]).rstrip(',') - return softmmuonly + linuxuseronly + ''.join([arch + "-linux-user" + "," + arch + "-softmmu" + "," for arch in archs]).rstrip(',') - -def get_qemu_usermode_target_list(d): - return ",".join(filter(lambda i: "-linux-user" in i, get_qemu_target_list(d).split(','))) - -def get_qemu_system_target_list(d): - return ",".join(filter(lambda i: "-linux-user" not in i, get_qemu_target_list(d).split(','))) diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb deleted file mode 100644 index ecc965216..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb +++ /dev/null @@ -1,30 +0,0 @@ - -python () { - if d.getVar("PREFERRED_PROVIDER_qemu-helper-native") != d.getVar("PN"): - raise bb.parse.SkipRecipe("Set qemu-helper-native provider to use this recipe") -} - -def get_filespath_extra(d, subpath): - metaroot = next((p for p in d.getVar('BBPATH').split(':') if os.path.basename(p) == 'meta'), None) - if metaroot: - return os.path.join(metaroot, subpath) + ":" - return "" - -# TODO: improve this, since it is very hacky that this recipe need to build tunctl. -# include the existing qemu-helper-native -require recipes-devtools/qemu/qemu-helper-native_1.0.bb -# get the path to tunctl.c -FILESEXTRAPATHS_prepend := "${@get_filespath_extra(d, 'recipes-devtools/qemu/qemu-helper')}" - -# provide it, to replace the existing -PROVIDES += "qemu-helper-native" - -# replace qemu with qemu-xilinx -DEPENDS_remove = "qemu-system-native" -DEPENDS_append = " \ - qemu-xilinx-system-native \ - qemu-xilinx-multiarch-helper-native \ - " - -RDEPENDS_${PN}_remove = "qemu-system-native" -RDEPENDS_${PN}_append = " qemu-xilinx-system-native" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb deleted file mode 100644 index 55cec776b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb +++ /dev/null @@ -1,20 +0,0 @@ -SUMMARY = "Helper scripts for executing a multi-arch instance of Xilinx QEMU" -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" -RDEPENDS_${PN} = "qemu-xilinx-native" - -inherit native - -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" - -SRC_URI = "file://qemu-system-aarch64-multiarch" - -do_configure[noexec] = "1" -do_compile[noexec] = "1" - -SYSROOT_DIRS += "${bindir}/qemu-xilinx" - -do_install() { - install -Dm 0755 ${WORKDIR}/qemu-system-aarch64-multiarch ${D}${bindir}/qemu-system-aarch64-multiarch -} - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc deleted file mode 100644 index d8f06c772..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc +++ /dev/null @@ -1,11 +0,0 @@ -require qemu-native.inc -require qemu-xilinx.inc - -DEPENDS = "glib-2.0-native zlib-native" - -SRC_URI_remove = "file://0012-fix-libcap-header-issue-on-some-distro.patch" -SRC_URI_remove = "file://0013-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch" - -do_install_append(){ - rm -rf ${D}${datadir}/icons -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2020.2.bb deleted file mode 100644 index 45d474d1e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2020.2.bb +++ /dev/null @@ -1,6 +0,0 @@ -require qemu-xilinx-native.inc -BPN = "qemu-xilinx" - -EXTRA_OECONF_append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent" - -PROVIDES = "qemu-native" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2020.2.bb deleted file mode 100644 index 93afebed2..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2020.2.bb +++ /dev/null @@ -1,17 +0,0 @@ -require qemu-xilinx-native.inc - -EXTRA_OECONF_append = " --target-list=${@get_qemu_system_target_list(d)}" - -PACKAGECONFIG ??= "fdt alsa kvm" - -PACKAGECONFIG_remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}" - -DEPENDS += "pixman-native qemu-xilinx-native" - -do_install_append() { - # The following is also installed by qemu-native - rm -f ${D}${datadir}/${BPN}/trace-events-all - rm -rf ${D}${datadir}/${BPN}/keymaps - rm -rf ${D}${datadir}/icons -} - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc deleted file mode 100644 index c22c43c06..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc +++ /dev/null @@ -1,44 +0,0 @@ -SUMMARY = "Xilinx's fork of a fast open source processor emulator" -HOMEPAGE = "https://github.com/xilinx/qemu/" - -# x86_64 is needed to build nativesdks -QEMU_TARGETS = "aarch64 arm microblaze microblazeel x86_64" - -LIC_FILES_CHKSUM = " \ - file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ - file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f \ - " -DEPENDS = "glib-2.0 zlib pixman" - -XILINX_QEMU_VERSION ?= "v5.1.0" -BRANCH ?= "master" -SRCREV ?= "${AUTOREV}" - -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" - -PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" -REPO ?= "gitsm://github.com/Xilinx/qemu.git;protocol=https" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -SRC_URI_append = " file://0010-configure-Add-pkg-config-handling-for-libgcrypt.patch \ - file://0001-Add-enable-disable-udev.patch \ -" - -S = "${WORKDIR}/git" - -# Disable KVM completely -PACKAGECONFIG_remove = "kvm" -PACKAGECONFIG_append = " fdt gcrypt" - -DISABLE_STATIC_pn-${PN} = "" - -PTEST_ENABLED = "" - -EXTRA_OECONF_append = " --with-git=/bin/false --disable-git-update" - -do_install_append() { - # Prevent QA warnings about installed ${localstatedir}/run - if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2020.2.bb deleted file mode 100644 index fd1904aba..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2020.2.bb +++ /dev/null @@ -1,16 +0,0 @@ -require qemu.inc -require qemu-xilinx.inc - -BBCLASSEXTEND = "nativesdk" - -RDEPENDS_${PN}_class-target += "bash" - -PROVIDES_class-nativesdk = "nativesdk-qemu" -RPROVIDES_${PN}_class-nativesdk = "nativesdk-qemu" - -EXTRA_OECONF_append_class-target = " --target-list=${@get_qemu_target_list(d)}" -EXTRA_OECONF_append_class-nativesdk = " --target-list=${@get_qemu_target_list(d)}" - -do_install_append_class-nativesdk() { - ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)} -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu.inc deleted file mode 100644 index 4864d7e93..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu.inc +++ /dev/null @@ -1,197 +0,0 @@ -SUMMARY = "Fast open source processor emulator" -DESCRIPTION = "QEMU is a hosted virtual machine monitor: it emulates the \ -machine's processor through dynamic binary translation and provides a set \ -of different hardware and device models for the machine, enabling it to run \ -a variety of guest operating systems" -HOMEPAGE = "http://qemu.org" -LICENSE = "GPLv2 & LGPLv2.1" - -RDEPENDS_${PN}-ptest = "bash make" - -require qemu-targets.inc -inherit pkgconfig ptest - -LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ - file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" - -SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ - file://powerpc_rom.bin \ - file://run-ptest \ - file://0001-qemu-Add-missing-wacom-HID-descriptor.patch \ - file://0002-Add-subpackage-ptest-which-runs-all-unit-test-cases-.patch \ - file://0003-qemu-Add-addition-environment-space-to-boot-loader-q.patch \ - file://0004-qemu-disable-Valgrind.patch \ - file://0005-qemu-native-set-ld.bfd-fix-cflags-and-set-some-envir.patch \ - file://0006-chardev-connect-socket-to-a-spawned-command.patch \ - file://0007-apic-fixup-fallthrough-to-PIC.patch \ - file://0008-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch \ - file://0009-Fix-webkitgtk-builds.patch \ - file://0010-configure-Add-pkg-config-handling-for-libgcrypt.patch \ - file://0001-Add-enable-disable-udev.patch \ - file://0001-qemu-Do-not-include-file-if-not-exists.patch \ - file://find_datadir.patch \ - file://usb-fix-setup_len-init.patch \ - file://0001-target-mips-Increase-number-of-TLB-entries-on-the-34.patch \ - file://CVE-2020-24352.patch \ - file://CVE-2020-29129-CVE-2020-29130.patch \ - file://CVE-2020-25624.patch \ - file://CVE-2020-25723.patch \ - file://CVE-2020-28916.patch \ - " -UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar" - -SRC_URI[sha256sum] = "c9174eb5933d9eb5e61f541cd6d1184cd3118dfe4c5c4955bc1bdc4d390fa4e5" - -COMPATIBLE_HOST_mipsarchn32 = "null" -COMPATIBLE_HOST_mipsarchn64 = "null" - -# Per https://lists.nongnu.org/archive/html/qemu-devel/2020-09/msg03873.html -# upstream states qemu doesn't work without optimization -DEBUG_BUILD = "0" - -do_install_append() { - # Prevent QA warnings about installed ${localstatedir}/run - if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi -} - -do_compile_ptest() { - make buildtest-TESTS -} - -do_install_ptest() { - cp -rL ${B}/tests ${D}${PTEST_PATH} - find ${D}${PTEST_PATH}/tests -type f -name "*.[Sshcod]" | xargs -i rm -rf {} - - cp ${S}/tests/Makefile.include ${D}${PTEST_PATH}/tests - # Don't check the file genreated by configure - sed -i -e '/wildcard config-host.mak/d' \ - -e '$ {/endif/d}' ${D}${PTEST_PATH}/tests/Makefile.include - sed -i -e 's,${HOSTTOOLS_DIR}/python3,${bindir}/python3,' \ - ${D}/${PTEST_PATH}/tests/qemu-iotests/common.env - sed -i -e "1s,#!/usr/bin/bash,#!${base_bindir}/bash," ${D}${PTEST_PATH}/tests/data/acpi/disassemle-aml.sh -} - -# QEMU_TARGETS is overridable variable -QEMU_TARGETS ?= "arm aarch64 i386 mips mipsel mips64 mips64el ppc ppc64 ppc64le riscv32 riscv64 sh4 x86_64" - -EXTRA_OECONF = " \ - --prefix=${prefix} \ - --bindir=${bindir} \ - --includedir=${includedir} \ - --libdir=${libdir} \ - --mandir=${mandir} \ - --datadir=${datadir} \ - --docdir=${docdir}/${BPN} \ - --sysconfdir=${sysconfdir} \ - --libexecdir=${libexecdir} \ - --localstatedir=${localstatedir} \ - --with-confsuffix=/${BPN} \ - --disable-strip \ - --disable-werror \ - --extra-cflags='${CFLAGS}' \ - --extra-ldflags='${LDFLAGS}' \ - --with-git=/bin/false \ - --disable-git-update \ - ${PACKAGECONFIG_CONFARGS} \ - " - -export LIBTOOL="${HOST_SYS}-libtool" - -B = "${WORKDIR}/build" - -EXTRA_OECONF_append = " --python=${HOSTTOOLS_DIR}/python3" - -do_configure_prepend_class-native() { - # Append build host pkg-config paths for native target since the host may provide sdl - BHOST_PKGCONFIG_PATH=$(PATH=/usr/bin:/bin pkg-config --variable pc_path pkg-config || echo "") - if [ ! -z "$BHOST_PKGCONFIG_PATH" ]; then - export PKG_CONFIG_PATH=$PKG_CONFIG_PATH:$BHOST_PKGCONFIG_PATH - fi -} - -do_configure() { - ${S}/configure ${EXTRA_OECONF} -} -do_configure[cleandirs] += "${B}" - -do_install () { - export STRIP="" - oe_runmake 'DESTDIR=${D}' install -} - -# The following fragment will create a wrapper for qemu-mips user emulation -# binary in order to work around a segmentation fault issue. Basically, by -# default, the reserved virtual address space for 32-on-64 bit is set to 4GB. -# This will trigger a MMU access fault in the virtual CPU. With this change, -# the qemu-mips works fine. -# IMPORTANT: This piece needs to be removed once the root cause is fixed! -do_install_append() { - if [ -e "${D}/${bindir}/qemu-mips" ]; then - create_wrapper ${D}/${bindir}/qemu-mips \ - QEMU_RESERVED_VA=0x0 - fi -} -# END of qemu-mips workaround - -make_qemu_wrapper() { - gdk_pixbuf_module_file=`pkg-config --variable=gdk_pixbuf_cache_file gdk-pixbuf-2.0` - - for tool in `ls ${D}${bindir}/qemu-system-*`; do - create_wrapper $tool \ - GDK_PIXBUF_MODULE_FILE=$gdk_pixbuf_module_file \ - FONTCONFIG_PATH=/etc/fonts \ - GTK_THEME=Adwaita - done -} - -# Disable kvm/virgl/mesa on targets that do not support it -PACKAGECONFIG_remove_darwin = "kvm virglrenderer glx gtk+" -PACKAGECONFIG_remove_mingw32 = "kvm virglrenderer glx gtk+" - -PACKAGECONFIG[sdl] = "--enable-sdl,--disable-sdl,libsdl2" -PACKAGECONFIG[virtfs] = "--enable-virtfs --enable-attr --enable-cap-ng,--disable-virtfs,libcap-ng attr," -PACKAGECONFIG[aio] = "--enable-linux-aio,--disable-linux-aio,libaio," -PACKAGECONFIG[xfs] = "--enable-xfsctl,--disable-xfsctl,xfsprogs," -PACKAGECONFIG[xen] = "--enable-xen,--disable-xen,xen-tools,xen-tools-libxenstore xen-tools-libxenctrl xen-tools-libxenguest" -PACKAGECONFIG[vnc-sasl] = "--enable-vnc --enable-vnc-sasl,--disable-vnc-sasl,cyrus-sasl," -PACKAGECONFIG[vnc-jpeg] = "--enable-vnc --enable-vnc-jpeg,--disable-vnc-jpeg,jpeg," -PACKAGECONFIG[vnc-png] = "--enable-vnc --enable-vnc-png,--disable-vnc-png,libpng," -PACKAGECONFIG[libcurl] = "--enable-curl,--disable-curl,curl," -PACKAGECONFIG[nss] = "--enable-smartcard,--disable-smartcard,nss," -PACKAGECONFIG[curses] = "--enable-curses,--disable-curses,ncurses," -PACKAGECONFIG[gtk+] = "--enable-gtk,--disable-gtk,gtk+3 gettext-native" -PACKAGECONFIG[vte] = "--enable-vte,--disable-vte,vte gettext-native" -PACKAGECONFIG[libcap-ng] = "--enable-cap-ng,--disable-cap-ng,libcap-ng," -PACKAGECONFIG[ssh] = "--enable-libssh,--disable-libssh,libssh," -PACKAGECONFIG[gcrypt] = "--enable-gcrypt,--disable-gcrypt,libgcrypt," -PACKAGECONFIG[nettle] = "--enable-nettle,--disable-nettle,nettle" -PACKAGECONFIG[libusb] = "--enable-libusb,--disable-libusb,libusb1" -PACKAGECONFIG[fdt] = "--enable-fdt,--disable-fdt,dtc" -PACKAGECONFIG[alsa] = "--audio-drv-list='oss alsa',,alsa-lib" -PACKAGECONFIG[glx] = "--enable-opengl,--disable-opengl,virtual/libgl" -PACKAGECONFIG[lzo] = "--enable-lzo,--disable-lzo,lzo" -PACKAGECONFIG[numa] = "--enable-numa,--disable-numa,numactl" -PACKAGECONFIG[gnutls] = "--enable-gnutls,--disable-gnutls,gnutls" -PACKAGECONFIG[bzip2] = "--enable-bzip2,--disable-bzip2,bzip2" -PACKAGECONFIG[libiscsi] = "--enable-libiscsi,--disable-libiscsi" -PACKAGECONFIG[kvm] = "--enable-kvm,--disable-kvm" -PACKAGECONFIG[virglrenderer] = "--enable-virglrenderer,--disable-virglrenderer,virglrenderer" -# spice will be in meta-networking layer -PACKAGECONFIG[spice] = "--enable-spice,--disable-spice,spice" -# usbredir will be in meta-networking layer -PACKAGECONFIG[usb-redir] = "--enable-usb-redir,--disable-usb-redir,usbredir" -PACKAGECONFIG[snappy] = "--enable-snappy,--disable-snappy,snappy" -PACKAGECONFIG[glusterfs] = "--enable-glusterfs,--disable-glusterfs,glusterfs" -PACKAGECONFIG[xkbcommon] = "--enable-xkbcommon,--disable-xkbcommon,libxkbcommon" -PACKAGECONFIG[libudev] = "--enable-libudev,--disable-libudev,eudev" -PACKAGECONFIG[libxml2] = "--enable-libxml2,--disable-libxml2,libxml2" -PACKAGECONFIG[attr] = "--enable-attr,--disable-attr,attr," -PACKAGECONFIG[rbd] = "--enable-rbd,--disable-rbd,ceph,ceph" -PACKAGECONFIG[vhost] = "--enable-vhost-net,--disable-vhost-net,," -PACKAGECONFIG[ust] = "--enable-trace-backend=ust,--enable-trace-backend=nop,lttng-ust," -PACKAGECONFIG[pie] = "--enable-pie,--disable-pie,," -PACKAGECONFIG[seccomp] = "--enable-seccomp,--disable-seccomp,libseccomp" - -INSANE_SKIP_${PN} = "arch" - -FILES_${PN} += "${datadir}/icons" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-Add-enable-disable-udev.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-Add-enable-disable-udev.patch deleted file mode 100644 index 1304ee3bf..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-Add-enable-disable-udev.patch +++ /dev/null @@ -1,29 +0,0 @@ -From b921e5204030845dc7c9d16d5f66d965e8d05367 Mon Sep 17 00:00:00 2001 -From: Jeremy Puhlman <jpuhlman@mvista.com> -Date: Thu, 19 Mar 2020 11:54:26 -0700 -Subject: [PATCH] Add enable/disable libudev - -Upstream-Status: Pending -Signed-off-by: Jeremy Puhlman <jpuhlman@mvista.com> - -[update patch context] -Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> ---- - configure | 4 ++++ - 1 file changed, 4 insertions(+) - -Index: qemu-5.1.0/configure -=================================================================== ---- qemu-5.1.0.orig/configure -+++ qemu-5.1.0/configure -@@ -1640,6 +1640,10 @@ for opt do - ;; - --disable-libdaxctl) libdaxctl=no - ;; -+ --enable-libudev) libudev="yes" -+ ;; -+ --disable-libudev) libudev="no" -+ ;; - *) - echo "ERROR: unknown option $opt" - echo "Try '$0 --help' for more information" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-qemu-Add-missing-wacom-HID-descriptor.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-qemu-Add-missing-wacom-HID-descriptor.patch deleted file mode 100644 index 46c9da08a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-qemu-Add-missing-wacom-HID-descriptor.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 883feb43129dc39b491e492c7ccfe89aefe53c44 Mon Sep 17 00:00:00 2001 -From: Richard Purdie <richard.purdie@linuxfoundation.org> -Date: Thu, 27 Nov 2014 14:04:29 +0000 -Subject: [PATCH] qemu: Add missing wacom HID descriptor - -The USB wacom device is missing a HID descriptor which causes it -to fail to operate with recent kernels (e.g. 3.17). - -This patch adds a HID desriptor to the device, based upon one from -real wcom device. - -Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> - -Upstream-Status: Submitted -2014/11/27 - -[update patch context] -Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> ---- - hw/usb/dev-wacom.c | 94 +++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 93 insertions(+), 1 deletion(-) - -Index: qemu-5.1.0/hw/usb/dev-wacom.c -=================================================================== ---- qemu-5.1.0.orig/hw/usb/dev-wacom.c -+++ qemu-5.1.0/hw/usb/dev-wacom.c -@@ -74,6 +74,89 @@ static const USBDescStrings desc_strings - [STR_SERIALNUMBER] = "1", - }; - -+static const uint8_t qemu_tablet_hid_report_descriptor[] = { -+ 0x05, 0x01, /* Usage Page (Generic Desktop) */ -+ 0x09, 0x02, /* Usage (Mouse) */ -+ 0xa1, 0x01, /* Collection (Application) */ -+ 0x85, 0x01, /* Report ID (1) */ -+ 0x09, 0x01, /* Usage (Pointer) */ -+ 0xa1, 0x00, /* Collection (Physical) */ -+ 0x05, 0x09, /* Usage Page (Button) */ -+ 0x19, 0x01, /* Usage Minimum (1) */ -+ 0x29, 0x05, /* Usage Maximum (5) */ -+ 0x15, 0x00, /* Logical Minimum (0) */ -+ 0x25, 0x01, /* Logical Maximum (1) */ -+ 0x95, 0x05, /* Report Count (5) */ -+ 0x75, 0x01, /* Report Size (1) */ -+ 0x81, 0x02, /* Input (Data, Variable, Absolute) */ -+ 0x95, 0x01, /* Report Count (1) */ -+ 0x75, 0x03, /* Report Size (3) */ -+ 0x81, 0x01, /* Input (Constant) */ -+ 0x05, 0x01, /* Usage Page (Generic Desktop) */ -+ 0x09, 0x30, /* Usage (X) */ -+ 0x09, 0x31, /* Usage (Y) */ -+ 0x15, 0x81, /* Logical Minimum (-127) */ -+ 0x25, 0x7f, /* Logical Maximum (127) */ -+ 0x75, 0x08, /* Report Size (8) */ -+ 0x95, 0x02, /* Report Count (2) */ -+ 0x81, 0x06, /* Input (Data, Variable, Relative) */ -+ 0xc0, /* End Collection */ -+ 0xc0, /* End Collection */ -+ 0x05, 0x0d, /* Usage Page (Digitizer) */ -+ 0x09, 0x01, /* Usage (Digitizer) */ -+ 0xa1, 0x01, /* Collection (Application) */ -+ 0x85, 0x02, /* Report ID (2) */ -+ 0xa1, 0x00, /* Collection (Physical) */ -+ 0x06, 0x00, 0xff, /* Usage Page (Vendor 0xff00) */ -+ 0x09, 0x01, /* Usage (Digitizer) */ -+ 0x15, 0x00, /* Logical Minimum (0) */ -+ 0x26, 0xff, 0x00, /* Logical Maximum (255) */ -+ 0x75, 0x08, /* Report Size (8) */ -+ 0x95, 0x08, /* Report Count (8) */ -+ 0x81, 0x02, /* Input (Data, Variable, Absolute) */ -+ 0xc0, /* End Collection */ -+ 0x09, 0x01, /* Usage (Digitizer) */ -+ 0x85, 0x02, /* Report ID (2) */ -+ 0x95, 0x01, /* Report Count (1) */ -+ 0xb1, 0x02, /* FEATURE (2) */ -+ 0xc0, /* End Collection */ -+ 0x06, 0x00, 0xff, /* Usage Page (Vendor 0xff00) */ -+ 0x09, 0x01, /* Usage (Digitizer) */ -+ 0xa1, 0x01, /* Collection (Application) */ -+ 0x85, 0x02, /* Report ID (2) */ -+ 0x05, 0x0d, /* Usage Page (Digitizer) */ -+ 0x09, 0x22, /* Usage (Finger) */ -+ 0xa1, 0x00, /* Collection (Physical) */ -+ 0x06, 0x00, 0xff, /* Usage Page (Vendor 0xff00) */ -+ 0x09, 0x01, /* Usage (Digitizer) */ -+ 0x15, 0x00, /* Logical Minimum (0) */ -+ 0x26, 0xff, 0x00, /* Logical Maximum */ -+ 0x75, 0x08, /* Report Size (8) */ -+ 0x95, 0x02, /* Report Count (2) */ -+ 0x81, 0x02, /* Input (Data, Variable, Absolute) */ -+ 0x05, 0x01, /* Usage Page (Generic Desktop) */ -+ 0x09, 0x30, /* Usage (X) */ -+ 0x35, 0x00, /* Physical Minimum */ -+ 0x46, 0xe0, 0x2e, /* Physical Maximum */ -+ 0x26, 0xe0, 0x01, /* Logical Maximum */ -+ 0x75, 0x10, /* Report Size (16) */ -+ 0x95, 0x01, /* Report Count (1) */ -+ 0x81, 0x02, /* Input (Data, Variable, Absolute) */ -+ 0x09, 0x31, /* Usage (Y) */ -+ 0x46, 0x40, 0x1f, /* Physical Maximum */ -+ 0x26, 0x40, 0x01, /* Logical Maximum */ -+ 0x81, 0x02, /* Input (Data, Variable, Absolute) */ -+ 0x06, 0x00, 0xff, /* Usage Page (Vendor 0xff00) */ -+ 0x09, 0x01, /* Usage (Digitizer) */ -+ 0x26, 0xff, 0x00, /* Logical Maximum */ -+ 0x75, 0x08, /* Report Size (8) */ -+ 0x95, 0x0d, /* Report Count (13) */ -+ 0x81, 0x02, /* Input (Data, Variable, Absolute) */ -+ 0xc0, /* End Collection */ -+ 0xc0, /* End Collection */ -+}; -+ -+ - static const USBDescIface desc_iface_wacom = { - .bInterfaceNumber = 0, - .bNumEndpoints = 1, -@@ -91,7 +174,7 @@ static const USBDescIface desc_iface_wac - 0x00, /* u8 country_code */ - 0x01, /* u8 num_descriptors */ - 0x22, /* u8 type: Report */ -- 0x6e, 0, /* u16 len */ -+ sizeof(qemu_tablet_hid_report_descriptor), 0, /* u16 len */ - }, - }, - }, -@@ -271,6 +354,15 @@ static void usb_wacom_handle_control(USB - } - - switch (request) { -+ case InterfaceRequest | USB_REQ_GET_DESCRIPTOR: -+ switch (value >> 8) { -+ case 0x22: -+ memcpy(data, qemu_tablet_hid_report_descriptor, -+ sizeof(qemu_tablet_hid_report_descriptor)); -+ p->actual_length = sizeof(qemu_tablet_hid_report_descriptor); -+ break; -+ } -+ break; - case WACOM_SET_REPORT: - if (s->mouse_grabbed) { - qemu_remove_mouse_event_handler(s->eh_entry); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-qemu-Do-not-include-file-if-not-exists.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-qemu-Do-not-include-file-if-not-exists.patch deleted file mode 100644 index d6c0f9ebe..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-qemu-Do-not-include-file-if-not-exists.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 34247f83095f8cdcdc1f9d7f0c6ffbd46b25d979 Mon Sep 17 00:00:00 2001 -From: Oleksiy Obitotskyy <oobitots@cisco.com> -Date: Wed, 25 Mar 2020 21:21:35 +0200 -Subject: [PATCH] qemu: Do not include file if not exists - -Script configure checks for if_alg.h and check failed but -if_alg.h still included. - -Upstream-Status: Submitted [https://lists.gnu.org/archive/html/qemu-devel/2020-03/msg07188.html] -Signed-off-by: Oleksiy Obitotskyy <oobitots@cisco.com> - -[update patch context] -Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> ---- - linux-user/syscall.c | 2 ++ - 1 file changed, 2 insertions(+) - -Index: qemu-5.1.0/linux-user/syscall.c -=================================================================== ---- qemu-5.1.0.orig/linux-user/syscall.c -+++ qemu-5.1.0/linux-user/syscall.c -@@ -109,7 +109,9 @@ - #include <linux/blkpg.h> - #include <netpacket/packet.h> - #include <linux/netlink.h> -+#if defined(CONFIG_AF_ALG) - #include <linux/if_alg.h> -+#endif - #include <linux/rtc.h> - #include <sound/asound.h> - #ifdef HAVE_DRM_H diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-target-mips-Increase-number-of-TLB-entries-on-the-34.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-target-mips-Increase-number-of-TLB-entries-on-the-34.patch deleted file mode 100644 index 5227b7cbd..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0001-target-mips-Increase-number-of-TLB-entries-on-the-34.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 68fa519a6cb455005317bd61f95214b58b2f1e69 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org> -Date: Fri, 16 Oct 2020 15:20:37 +0200 -Subject: [PATCH] target/mips: Increase number of TLB entries on the 34Kf core - (16 -> 64) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Per "MIPS32 34K Processor Core Family Software User's Manual, -Revision 01.13" page 8 in "Joint TLB (JTLB)" section: - - "The JTLB is a fully associative TLB cache containing 16, 32, - or 64-dual-entries mapping up to 128 virtual pages to their - corresponding physical addresses." - -There is no particular reason to restrict the 34Kf core model to -16 TLB entries, so raise its config to 64. - -This is helpful for other projects, in particular the Yocto Project: - - Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit - MIPS CI loop. It was observed that in this case CI test execution - time was almost twice longer than 64bit MIPS variant that runs - under MIPS64R2-generic model. It was investigated and concluded - that the difference in number of TLBs 16 in 34Kf case vs 64 in - MIPS64R2-generic is responsible for most of CI real time execution - difference. Because with 16 TLBs linux user-land trashes TLB more - and it needs to execute more instructions in TLB refill handler - calls, as result it runs much longer. - -(https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) - -Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 -Reported-by: Victor Kamensky <kamensky@cisco.com> -Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> -Reviewed-by: Richard Henderson <richard.henderson@linaro.org> -Message-Id: <20201016133317.553068-1-f4bug@amsat.org> - -Upstream-Status: Backport [https://github.com/qemu/qemu/commit/68fa519a6cb455005317bd61f95214b58b2f1e69] -Signed-off-by: Victor Kamensky <kamensky@cisco.com> - ---- - target/mips/translate_init.c.inc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -Index: qemu-5.1.0/target/mips/translate_init.inc.c -=================================================================== ---- qemu-5.1.0.orig/target/mips/translate_init.inc.c -+++ qemu-5.1.0/target/mips/translate_init.inc.c -@@ -254,7 +254,7 @@ const mips_def_t mips_defs[] = - .CP0_PRid = 0x00019500, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), -- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | -+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0002-Add-subpackage-ptest-which-runs-all-unit-test-cases-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0002-Add-subpackage-ptest-which-runs-all-unit-test-cases-.patch deleted file mode 100644 index f379948f1..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0002-Add-subpackage-ptest-which-runs-all-unit-test-cases-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5da6cef7761157a003e7ebde74fb3cf90ab396d9 Mon Sep 17 00:00:00 2001 -From: Juro Bystricky <juro.bystricky@intel.com> -Date: Thu, 31 Aug 2017 11:06:56 -0700 -Subject: [PATCH] Add subpackage -ptest which runs all unit test cases for - qemu. - -Upstream-Status: Pending - -Signed-off-by: Kai Kang <kai.kang@windriver.com> - -Signed-off-by: Juro Bystricky <juro.bystricky@intel.com> - -[update patch context] -Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> ---- - tests/Makefile.include | 8 ++++++++ - 1 file changed, 8 insertions(+) - -Index: qemu-5.1.0/tests/Makefile.include -=================================================================== ---- qemu-5.1.0.orig/tests/Makefile.include -+++ qemu-5.1.0/tests/Makefile.include -@@ -982,4 +982,12 @@ all: $(QEMU_IOTESTS_HELPERS-y) - -include $(wildcard tests/qtest/*.d) - -include $(wildcard tests/qtest/libqos/*.d) - -+buildtest-TESTS: $(check-unit-y) -+ -+runtest-TESTS: -+ for f in $(check-unit-y); do \ -+ nf=$$(echo $$f | sed 's/tests\//\.\//g'); \ -+ $$nf; \ -+ done -+ - endif diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0003-qemu-Add-addition-environment-space-to-boot-loader-q.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0003-qemu-Add-addition-environment-space-to-boot-loader-q.patch deleted file mode 100644 index 33cef4221..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0003-qemu-Add-addition-environment-space-to-boot-loader-q.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ce1eceab2350d27960ec254650717085f6a11c9a Mon Sep 17 00:00:00 2001 -From: Jason Wessel <jason.wessel@windriver.com> -Date: Fri, 28 Mar 2014 17:42:43 +0800 -Subject: [PATCH] qemu: Add addition environment space to boot loader - qemu-system-mips - -Upstream-Status: Inappropriate - OE uses deep paths - -If you create a project with very long directory names like 128 characters -deep and use NFS, the kernel arguments will be truncated. The kernel will -accept longer strings such as 1024 bytes, but the qemu boot loader defaulted -to only 256 bytes. This patch expands the limit. - -Signed-off-by: Jason Wessel <jason.wessel@windriver.com> -Signed-off-by: Roy Li <rongqing.li@windriver.com> - ---- - hw/mips/malta.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -Index: qemu-5.1.0/hw/mips/malta.c -=================================================================== ---- qemu-5.1.0.orig/hw/mips/malta.c -+++ qemu-5.1.0/hw/mips/malta.c -@@ -59,7 +59,7 @@ - - #define ENVP_ADDR 0x80002000l - #define ENVP_NB_ENTRIES 16 --#define ENVP_ENTRY_SIZE 256 -+#define ENVP_ENTRY_SIZE 1024 - - /* Hardware addresses */ - #define FLASH_ADDRESS 0x1e000000ULL diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0004-qemu-disable-Valgrind.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0004-qemu-disable-Valgrind.patch deleted file mode 100644 index 71f537f9b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0004-qemu-disable-Valgrind.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 4127296bb1046cdf73994ba69dc913d8c02fd74f Mon Sep 17 00:00:00 2001 -From: Ross Burton <ross.burton@intel.com> -Date: Tue, 20 Oct 2015 22:19:08 +0100 -Subject: [PATCH] qemu: disable Valgrind - -There isn't an option to enable or disable valgrind support, so disable it to avoid non-deterministic builds. - -Upstream-Status: Inappropriate -Signed-off-by: Ross Burton <ross.burton@intel.com> - ---- - configure | 9 --------- - 1 file changed, 9 deletions(-) - -Index: qemu-5.1.0/configure -=================================================================== ---- qemu-5.1.0.orig/configure -+++ qemu-5.1.0/configure -@@ -5751,15 +5751,6 @@ fi - # check if we have valgrind/valgrind.h - - valgrind_h=no --cat > $TMPC << EOF --#include <valgrind/valgrind.h> --int main(void) { -- return 0; --} --EOF --if compile_prog "" "" ; then -- valgrind_h=yes --fi - - ######################################## - # check if environ is declared diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0005-qemu-native-set-ld.bfd-fix-cflags-and-set-some-envir.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0005-qemu-native-set-ld.bfd-fix-cflags-and-set-some-envir.patch deleted file mode 100644 index 02ebbee1a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0005-qemu-native-set-ld.bfd-fix-cflags-and-set-some-envir.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 230fe5804099bdca0c9e4cae7280c9fc513cb7f5 Mon Sep 17 00:00:00 2001 -From: Stephen Arnold <sarnold@vctlabs.com> -Date: Sun, 12 Jun 2016 18:09:56 -0700 -Subject: [PATCH] qemu-native: set ld.bfd, fix cflags, and set some environment - -Upstream-Status: Pending - -[update patch context] -Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> ---- - configure | 4 ---- - 1 file changed, 4 deletions(-) - -Index: qemu-5.1.0/configure -=================================================================== ---- qemu-5.1.0.orig/configure -+++ qemu-5.1.0/configure -@@ -6515,10 +6515,6 @@ write_c_skeleton - if test "$gcov" = "yes" ; then - QEMU_CFLAGS="-fprofile-arcs -ftest-coverage -g $QEMU_CFLAGS" - QEMU_LDFLAGS="-fprofile-arcs -ftest-coverage $QEMU_LDFLAGS" --elif test "$fortify_source" = "yes" ; then -- CFLAGS="-O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $CFLAGS" --elif test "$debug" = "no"; then -- CFLAGS="-O2 $CFLAGS" - fi - - if test "$have_asan" = "yes"; then diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0006-chardev-connect-socket-to-a-spawned-command.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0006-chardev-connect-socket-to-a-spawned-command.patch deleted file mode 100644 index 98fd5e913..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0006-chardev-connect-socket-to-a-spawned-command.patch +++ /dev/null @@ -1,241 +0,0 @@ -From bcc63f775e265df69963a4ad7805b8678ace68f0 Mon Sep 17 00:00:00 2001 -From: Alistair Francis <alistair.francis@xilinx.com> -Date: Thu, 21 Dec 2017 11:35:16 -0800 -Subject: [PATCH] chardev: connect socket to a spawned command - -The command is started in a shell (sh -c) with stdin connect to QEMU -via a Unix domain stream socket. QEMU then exchanges data via its own -end of the socket, just like it normally does. - -"-chardev socket" supports some ways of connecting via protocols like -telnet, but that is only a subset of the functionality supported by -tools socat. To use socat instead, for example to connect via a socks -proxy, use: - - -chardev 'socket,id=socat,cmd=exec socat FD:0 SOCKS4A:socks-proxy.localdomain:example.com:9999,,socksuser=nobody' \ - -device usb-serial,chardev=socat - -Beware that commas in the command must be escaped as double commas. - -Or interactively in the console: - (qemu) chardev-add socket,id=cat,cmd=cat - (qemu) device_add usb-serial,chardev=cat - ^ac - # cat >/dev/ttyUSB0 - hello - hello - -Another usage is starting swtpm from inside QEMU. swtpm will -automatically shut down once it looses the connection to the parent -QEMU, so there is no risk of lingering processes: - - -chardev 'socket,id=chrtpm0,cmd=exec swtpm socket --terminate --ctrl type=unixio,,clientfd=0 --tpmstate dir=... --log file=swtpm.log' \ - -tpmdev emulator,id=tpm0,chardev=chrtpm0 \ - -device tpm-tis,tpmdev=tpm0 - -The patch was discussed upstream, but QEMU developers believe that the -code calling QEMU should be responsible for managing additional -processes. In OE-core, that would imply enhancing runqemu and -oeqa. This patch is a simpler solution. - -Because it is not going upstream, the patch was written so that it is -as simple as possible. - -Upstream-Status: Inappropriate [embedded specific] - -Signed-off-by: Patrick Ohly <patrick.ohly@intel.com> - ---- - chardev/char-socket.c | 101 ++++++++++++++++++++++++++++++++++++++++++ - chardev/char.c | 3 ++ - qapi/char.json | 5 +++ - 3 files changed, 109 insertions(+) - -Index: qemu-5.1.0/chardev/char-socket.c -=================================================================== ---- qemu-5.1.0.orig/chardev/char-socket.c -+++ qemu-5.1.0/chardev/char-socket.c -@@ -1292,6 +1292,67 @@ static bool qmp_chardev_validate_socket( - return true; - } - -+#ifndef _WIN32 -+static void chardev_open_socket_cmd(Chardev *chr, -+ const char *cmd, -+ Error **errp) -+{ -+ int fds[2] = { -1, -1 }; -+ QIOChannelSocket *sioc = NULL; -+ pid_t pid = -1; -+ const char *argv[] = { "/bin/sh", "-c", cmd, NULL }; -+ -+ /* -+ * We need a Unix domain socket for commands like swtpm and a single -+ * connection, therefore we cannot use qio_channel_command_new_spawn() -+ * without patching it first. Duplicating the functionality is easier. -+ */ -+ if (socketpair(AF_UNIX, SOCK_STREAM|SOCK_CLOEXEC, 0, fds)) { -+ error_setg_errno(errp, errno, "Error creating socketpair(AF_UNIX, SOCK_STREAM|SOCK_CLOEXEC)"); -+ goto error; -+ } -+ -+ pid = qemu_fork(errp); -+ if (pid < 0) { -+ goto error; -+ } -+ -+ if (!pid) { -+ /* child */ -+ dup2(fds[1], STDIN_FILENO); -+ execv(argv[0], (char * const *)argv); -+ _exit(1); -+ } -+ -+ /* -+ * Hand over our end of the socket pair to the qio channel. -+ * -+ * We don't reap the child because it is expected to keep -+ * running. We also don't support the "reconnect" option for the -+ * same reason. -+ */ -+ sioc = qio_channel_socket_new_fd(fds[0], errp); -+ if (!sioc) { -+ goto error; -+ } -+ fds[0] = -1; -+ -+ g_free(chr->filename); -+ chr->filename = g_strdup_printf("cmd:%s", cmd); -+ tcp_chr_new_client(chr, sioc); -+ -+ error: -+ if (fds[0] >= 0) { -+ close(fds[0]); -+ } -+ if (fds[1] >= 0) { -+ close(fds[1]); -+ } -+ if (sioc) { -+ object_unref(OBJECT(sioc)); -+ } -+} -+#endif - - static void qmp_chardev_open_socket(Chardev *chr, - ChardevBackend *backend, -@@ -1300,6 +1361,9 @@ static void qmp_chardev_open_socket(Char - { - SocketChardev *s = SOCKET_CHARDEV(chr); - ChardevSocket *sock = backend->u.socket.data; -+#ifndef _WIN32 -+ const char *cmd = sock->cmd; -+#endif - bool do_nodelay = sock->has_nodelay ? sock->nodelay : false; - bool is_listen = sock->has_server ? sock->server : true; - bool is_telnet = sock->has_telnet ? sock->telnet : false; -@@ -1365,6 +1429,14 @@ static void qmp_chardev_open_socket(Char - - update_disconnected_filename(s); - -+#ifndef _WIN32 -+ if (cmd) { -+ chardev_open_socket_cmd(chr, cmd, errp); -+ -+ /* everything ready (or failed permanently) before we return */ -+ *be_opened = true; -+ } else -+#endif - if (s->is_listen) { - if (qmp_chardev_open_socket_server(chr, is_telnet || is_tn3270, - is_waitconnect, errp) < 0) { -@@ -1384,11 +1456,27 @@ static void qemu_chr_parse_socket(QemuOp - const char *host = qemu_opt_get(opts, "host"); - const char *port = qemu_opt_get(opts, "port"); - const char *fd = qemu_opt_get(opts, "fd"); -+#ifndef _WIN32 -+ const char *cmd = qemu_opt_get(opts, "cmd"); -+#endif - bool tight = qemu_opt_get_bool(opts, "tight", true); - bool abstract = qemu_opt_get_bool(opts, "abstract", false); - SocketAddressLegacy *addr; - ChardevSocket *sock; - -+#ifndef _WIN32 -+ if (cmd) { -+ /* -+ * Here we have to ensure that no options are set which are incompatible with -+ * spawning a command, otherwise unmodified code that doesn't know about -+ * command spawning (like socket_reconnect_timeout()) might get called. -+ */ -+ if (path || sock->server || sock->has_telnet || sock->has_tn3270 || sock->reconnect || host || port || sock->tls_creds) { -+ error_setg(errp, "chardev: socket: cmd does not support any additional options"); -+ return; -+ } -+ } else -+#endif - if ((!!path + !!fd + !!host) != 1) { - error_setg(errp, - "Exactly one of 'path', 'fd' or 'host' required"); -@@ -1431,12 +1519,24 @@ static void qemu_chr_parse_socket(QemuOp - sock->has_tls_authz = qemu_opt_get(opts, "tls-authz"); - sock->tls_authz = g_strdup(qemu_opt_get(opts, "tls-authz")); - -- addr = g_new0(SocketAddressLegacy, 1); -+#ifndef _WIN32 -+ sock->cmd = g_strdup(cmd); -+#endif -+ -+ addr = g_new0(SocketAddressLegacy, 1); -+#ifndef _WIN32 -+ if (path || cmd) { -+#else - if (path) { -+#endif - UnixSocketAddress *q_unix; - addr->type = SOCKET_ADDRESS_LEGACY_KIND_UNIX; - q_unix = addr->u.q_unix.data = g_new0(UnixSocketAddress, 1); -+#ifndef _WIN32 -+ q_unix->path = cmd ? g_strdup_printf("cmd:%s", cmd) : g_strdup(path); -+#else - q_unix->path = g_strdup(path); -+#endif - q_unix->tight = tight; - q_unix->abstract = abstract; - } else if (host) { -Index: qemu-5.1.0/chardev/char.c -=================================================================== ---- qemu-5.1.0.orig/chardev/char.c -+++ qemu-5.1.0/chardev/char.c -@@ -826,6 +826,9 @@ QemuOptsList qemu_chardev_opts = { - .name = "path", - .type = QEMU_OPT_STRING, - },{ -+ .name = "cmd", -+ .type = QEMU_OPT_STRING, -+ },{ - .name = "host", - .type = QEMU_OPT_STRING, - },{ -Index: qemu-5.1.0/qapi/char.json -=================================================================== ---- qemu-5.1.0.orig/qapi/char.json -+++ qemu-5.1.0/qapi/char.json -@@ -250,6 +250,10 @@ - # - # @addr: socket address to listen on (server=true) - # or connect to (server=false) -+# @cmd: command to run via "sh -c" with stdin as one end of -+# a AF_UNIX SOCK_DSTREAM socket pair. The other end -+# is used by the chardev. Either an addr or a cmd can -+# be specified, but not both. - # @tls-creds: the ID of the TLS credentials object (since 2.6) - # @tls-authz: the ID of the QAuthZ authorization object against which - # the client's x509 distinguished name will be validated. This -@@ -276,6 +280,7 @@ - ## - { 'struct': 'ChardevSocket', - 'data': { 'addr': 'SocketAddressLegacy', -+ '*cmd': 'str', - '*tls-creds': 'str', - '*tls-authz' : 'str', - '*server': 'bool', diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0007-apic-fixup-fallthrough-to-PIC.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0007-apic-fixup-fallthrough-to-PIC.patch deleted file mode 100644 index 034ac5782..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0007-apic-fixup-fallthrough-to-PIC.patch +++ /dev/null @@ -1,44 +0,0 @@ -From a59a98d100123030a4145e7efe3b8a001920a9f1 Mon Sep 17 00:00:00 2001 -From: Mark Asselstine <mark.asselstine@windriver.com> -Date: Tue, 26 Feb 2013 11:43:28 -0500 -Subject: [PATCH] apic: fixup fallthrough to PIC - -Commit 0e21e12bb311c4c1095d0269dc2ef81196ccb60a [Don't route PIC -interrupts through the local APIC if the local APIC config says so.] -missed a check to ensure the local APIC is enabled. Since if the local -APIC is disabled it doesn't matter what the local APIC config says. - -If this check isn't done and the guest has disabled the local APIC the -guest will receive a general protection fault, similar to what is seen -here: - -https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02304.html - -The GPF is caused by an attempt to service interrupt 0xffffffff. This -comes about since cpu_get_pic_interrupt() calls apic_accept_pic_intr() -(with the local APIC disabled apic_get_interrupt() returns -1). -apic_accept_pic_intr() returns 0 and thus the interrupt number which -is returned from cpu_get_pic_interrupt(), and which is attempted to be -serviced, is -1. - -Signed-off-by: Mark Asselstine <mark.asselstine@windriver.com> -Upstream-Status: Submitted [https://lists.gnu.org/archive/html/qemu-devel/2013-04/msg00878.html] -Signed-off-by: He Zhe <zhe.he@windriver.com> - ---- - hw/intc/apic.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -Index: qemu-5.1.0/hw/intc/apic.c -=================================================================== ---- qemu-5.1.0.orig/hw/intc/apic.c -+++ qemu-5.1.0/hw/intc/apic.c -@@ -603,7 +603,7 @@ int apic_accept_pic_intr(DeviceState *de - APICCommonState *s = APIC(dev); - uint32_t lvt0; - -- if (!s) -+ if (!s || !(s->spurious_vec & APIC_SV_ENABLE)) - return -1; - - lvt0 = s->lvt[APIC_LVT_LINT0]; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0008-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0008-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch deleted file mode 100644 index d20f04ee5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0008-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch +++ /dev/null @@ -1,33 +0,0 @@ -From cf8c9aac5243f506a1a3e8e284414f311cde04f5 Mon Sep 17 00:00:00 2001 -From: Alistair Francis <alistair.francis@xilinx.com> -Date: Wed, 17 Jan 2018 10:51:49 -0800 -Subject: [PATCH] linux-user: Fix webkitgtk hangs on 32-bit x86 target - -Since commit "linux-user: Tidy and enforce reserved_va initialization" -(18e80c55bb6ec17c05ec0ba717ec83933c2bfc07) the Yocto webkitgtk build -hangs when cross compiling for 32-bit x86 on a 64-bit x86 machine using -musl. - -To fix the issue reduce the MAX_RESERVED_VA macro to be a closer match -to what it was before the problematic commit. - -Upstream-Status: Submitted http://lists.gnu.org/archive/html/qemu-devel/2018-01/msg04185.html -Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> - ---- - linux-user/main.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -Index: qemu-5.1.0/linux-user/main.c -=================================================================== ---- qemu-5.1.0.orig/linux-user/main.c -+++ qemu-5.1.0/linux-user/main.c -@@ -92,7 +92,7 @@ static int last_log_mask; - (TARGET_LONG_BITS == 32 || defined(TARGET_ABI32)) - /* There are a number of places where we assign reserved_va to a variable - of type abi_ulong and expect it to fit. Avoid the last page. */ --# define MAX_RESERVED_VA(CPU) (0xfffffffful & TARGET_PAGE_MASK) -+# define MAX_RESERVED_VA(CPU) (0x7ffffffful & TARGET_PAGE_MASK) - # else - # define MAX_RESERVED_VA(CPU) (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - # endif diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0009-Fix-webkitgtk-builds.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0009-Fix-webkitgtk-builds.patch deleted file mode 100644 index f2a44986b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0009-Fix-webkitgtk-builds.patch +++ /dev/null @@ -1,137 +0,0 @@ -From 815c97ba0de02da9dace3fcfcbdf9b20e029f0d7 Mon Sep 17 00:00:00 2001 -From: Martin Jansa <martin.jansa@lge.com> -Date: Fri, 1 Jun 2018 08:41:07 +0000 -Subject: [PATCH] Fix webkitgtk builds - -This is a partial revert of "linux-user: fix mmap/munmap/mprotect/mremap/shmat". - -This patch fixes qemu-i386 hangs during gobject-introspection in webkitgtk build -when musl is used on qemux86. This is the same issue that -0008-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch was -fixing in the 2.11 release. - -This patch also fixes a build failure when building webkitgtk for -qemumips. A QEMU assert is seen while building webkitgtk: -page_check_range: Assertion `start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)' failed. - -This reverts commit ebf9a3630c911d0cfc9c20f7cafe9ba4f88cf583. - -Upstream-Status: Pending -Signed-off-by: Alistair Francis <alistair.francis@wdc.com> - -[update patch context] -Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> ---- - include/exec/cpu-all.h | 6 +----- - include/exec/cpu_ldst.h | 5 ++++- - linux-user/mmap.c | 17 ++++------------- - linux-user/syscall.c | 5 +---- - 4 files changed, 10 insertions(+), 23 deletions(-) - -Index: qemu-5.1.0/include/exec/cpu-all.h -=================================================================== ---- qemu-5.1.0.orig/include/exec/cpu-all.h -+++ qemu-5.1.0/include/exec/cpu-all.h -@@ -176,11 +176,8 @@ extern unsigned long reserved_va; - * avoid setting bits at the top of guest addresses that might need - * to be used for tags. - */ --#define GUEST_ADDR_MAX_ \ -- ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ -- UINT32_MAX : ~0ul) --#define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : GUEST_ADDR_MAX_) -- -+#define GUEST_ADDR_MAX (reserved_va ? reserved_va : \ -+ (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1) - #else - - #include "exec/hwaddr.h" -Index: qemu-5.1.0/include/exec/cpu_ldst.h -=================================================================== ---- qemu-5.1.0.orig/include/exec/cpu_ldst.h -+++ qemu-5.1.0/include/exec/cpu_ldst.h -@@ -75,7 +75,10 @@ typedef uint64_t abi_ptr; - #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS - #define guest_addr_valid(x) (1) - #else --#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) -+#define guest_addr_valid(x) ({ \ -+ ((x) < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \ -+ (!reserved_va || ((x) < reserved_va)); \ -+}) - #endif - #define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) - -Index: qemu-5.1.0/linux-user/mmap.c -=================================================================== ---- qemu-5.1.0.orig/linux-user/mmap.c -+++ qemu-5.1.0/linux-user/mmap.c -@@ -71,7 +71,7 @@ int target_mprotect(abi_ulong start, abi - return -TARGET_EINVAL; - len = TARGET_PAGE_ALIGN(len); - end = start + len; -- if (!guest_range_valid(start, len)) { -+ if (end < start) { - return -TARGET_ENOMEM; - } - prot &= PROT_READ | PROT_WRITE | PROT_EXEC; -@@ -467,8 +467,8 @@ abi_long target_mmap(abi_ulong start, ab - * It can fail only on 64-bit host with 32-bit target. - * On any other target/host host mmap() handles this error correctly. - */ -- if (end < start || !guest_range_valid(start, len)) { -- errno = ENOMEM; -+ if (end < start || ((unsigned long)start + len - 1 > (abi_ulong) -1)) { -+ errno = EINVAL; - goto fail; - } - -@@ -604,10 +604,8 @@ int target_munmap(abi_ulong start, abi_u - if (start & ~TARGET_PAGE_MASK) - return -TARGET_EINVAL; - len = TARGET_PAGE_ALIGN(len); -- if (len == 0 || !guest_range_valid(start, len)) { -+ if (len == 0) - return -TARGET_EINVAL; -- } -- - mmap_lock(); - end = start + len; - real_start = start & qemu_host_page_mask; -@@ -662,13 +660,6 @@ abi_long target_mremap(abi_ulong old_add - int prot; - void *host_addr; - -- if (!guest_range_valid(old_addr, old_size) || -- ((flags & MREMAP_FIXED) && -- !guest_range_valid(new_addr, new_size))) { -- errno = ENOMEM; -- return -1; -- } -- - mmap_lock(); - - if (flags & MREMAP_FIXED) { -Index: qemu-5.1.0/linux-user/syscall.c -=================================================================== ---- qemu-5.1.0.orig/linux-user/syscall.c -+++ qemu-5.1.0/linux-user/syscall.c -@@ -4336,9 +4336,6 @@ static inline abi_ulong do_shmat(CPUArch - return -TARGET_EINVAL; - } - } -- if (!guest_range_valid(shmaddr, shm_info.shm_segsz)) { -- return -TARGET_EINVAL; -- } - - mmap_lock(); - -@@ -7376,7 +7373,7 @@ static int open_self_maps(void *cpu_env, - const char *path; - - max = h2g_valid(max - 1) ? -- max : (uintptr_t) g2h(GUEST_ADDR_MAX) + 1; -+ max : (uintptr_t) g2h(GUEST_ADDR_MAX); - - if (page_check_range(h2g(min), max - min, flags) == -1) { - continue; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch deleted file mode 100644 index d7e3fffdd..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch +++ /dev/null @@ -1,91 +0,0 @@ -From c207607cdf3996ad9783c3bffbcd3d65e74c0158 Mon Sep 17 00:00:00 2001 -From: He Zhe <zhe.he@windriver.com> -Date: Wed, 28 Aug 2019 19:56:28 +0800 -Subject: [PATCH] configure: Add pkg-config handling for libgcrypt - -libgcrypt may also be controlled by pkg-config, this patch adds pkg-config -handling for libgcrypt. - -Upstream-Status: Denied [https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg06333.html] - -Signed-off-by: He Zhe <zhe.he@windriver.com> - ---- - configure | 48 ++++++++++++++++++++++++++++++++++++++++-------- - 1 file changed, 40 insertions(+), 8 deletions(-) - -Index: qemu-5.1.0/configure -=================================================================== ---- qemu-5.1.0.orig/configure -+++ qemu-5.1.0/configure -@@ -3084,6 +3084,30 @@ has_libgcrypt() { - return 0 - } - -+has_libgcrypt_pkgconfig() { -+ if ! has $pkg_config ; then -+ return 1 -+ fi -+ -+ if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then -+ return 1 -+ fi -+ -+ if test -n "$cross_prefix" ; then -+ host=$($pkg_config --variable=host libgcrypt) -+ if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then -+ print_error "host($host) does not match cross_prefix($cross_prefix)" -+ return 1 -+ fi -+ fi -+ -+ if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then -+ print_error "libgcrypt version is $($pkg_config --modversion libgcrypt)" -+ return 1 -+ fi -+ -+ return 0 -+} - - if test "$nettle" != "no"; then - pass="no" -@@ -3124,7 +3148,14 @@ fi - - if test "$gcrypt" != "no"; then - pass="no" -- if has_libgcrypt; then -+ if has_libgcrypt_pkgconfig; then -+ gcrypt_cflags=$($pkg_config --cflags libgcrypt) -+ if test "$static" = "yes" ; then -+ gcrypt_libs=$($pkg_config --libs --static libgcrypt) -+ else -+ gcrypt_libs=$($pkg_config --libs libgcrypt) -+ fi -+ elif has_libgcrypt; then - gcrypt_cflags=$(libgcrypt-config --cflags) - gcrypt_libs=$(libgcrypt-config --libs) - # Debian has removed -lgpg-error from libgcrypt-config -@@ -3134,15 +3165,16 @@ if test "$gcrypt" != "no"; then - then - gcrypt_libs="$gcrypt_libs -lgpg-error" - fi -+ fi - -- # Link test to make sure the given libraries work (e.g for static). -- write_c_skeleton -- if compile_prog "" "$gcrypt_libs" ; then -- LIBS="$gcrypt_libs $LIBS" -- QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags" -- pass="yes" -- fi -+ # Link test to make sure the given libraries work (e.g for static). -+ write_c_skeleton -+ if compile_prog "" "$gcrypt_libs" ; then -+ LIBS="$gcrypt_libs $LIBS" -+ QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags" -+ pass="yes" - fi -+ - if test "$pass" = "yes"; then - gcrypt="yes" - cat > $TMPC << EOF diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-24352.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-24352.patch deleted file mode 100644 index 861ff6c3b..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-24352.patch +++ /dev/null @@ -1,52 +0,0 @@ -From ca1f9cbfdce4d63b10d57de80fef89a89d92a540 Mon Sep 17 00:00:00 2001 -From: Prasad J Pandit <pjp@fedoraproject.org> -Date: Wed, 21 Oct 2020 16:08:18 +0530 -Subject: [PATCH 1/1] ati: check x y display parameter values - -The source and destination x,y display parameters in ati_2d_blt() -may run off the vga limits if either of s->regs.[src|dst]_[xy] is -zero. Check the parameter values to avoid potential crash. - -Reported-by: Gaoning Pan <pgn@zju.edu.cn> -Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> -Message-id: 20201021103818.1704030-1-ppandit@redhat.com -Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> - -Upstream-Status: Backport [ https://git.qemu.org/?p=qemu.git;a=commitdiff;h=ca1f9cbfdce4d63b10d57de80fef89a89d92a540;hp=2ddafce7f797082ad216657c830afd4546f16e37 ] -CVE: CVE-2020-24352 -Signed-off-by: Chee Yang Lee <chee.yang.lee@intel.com> ---- - hw/display/ati_2d.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - -diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c -index 23a8ae0..4dc10ea 100644 ---- a/hw/display/ati_2d.c -+++ b/hw/display/ati_2d.c -@@ -75,8 +75,9 @@ void ati_2d_blt(ATIVGAState *s) - dst_stride *= bpp; - } - uint8_t *end = s->vga.vram_ptr + s->vga.vram_size; -- if (dst_bits >= end || dst_bits + dst_x + (dst_y + s->regs.dst_height) * -- dst_stride >= end) { -+ if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >= end -+ || dst_bits + dst_x -+ + (dst_y + s->regs.dst_height) * dst_stride >= end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } -@@ -107,8 +108,9 @@ void ati_2d_blt(ATIVGAState *s) - src_bits += s->regs.crtc_offset & 0x07ffffff; - src_stride *= bpp; - } -- if (src_bits >= end || src_bits + src_x + -- (src_y + s->regs.dst_height) * src_stride >= end) { -+ if (src_x > 0x3fff || src_y > 0x3fff || src_bits >= end -+ || src_bits + src_x -+ + (src_y + s->regs.dst_height) * src_stride >= end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } --- -1.8.3.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-25624.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-25624.patch deleted file mode 100644 index 7631bab39..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-25624.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 1328fe0c32d5474604105b8105310e944976b058 Mon Sep 17 00:00:00 2001 -From: Prasad J Pandit <pjp@fedoraproject.org> -Date: Tue, 15 Sep 2020 23:52:58 +0530 -Subject: [PATCH] hw: usb: hcd-ohci: check len and frame_number variables - -While servicing the OHCI transfer descriptors(TD), OHCI host -controller derives variables 'start_addr', 'end_addr', 'len' -etc. from values supplied by the host controller driver. -Host controller driver may supply values such that using -above variables leads to out-of-bounds access issues. -Add checks to avoid them. - -AddressSanitizer: stack-buffer-overflow on address 0x7ffd53af76a0 - READ of size 2 at 0x7ffd53af76a0 thread T0 - #0 ohci_service_iso_td ../hw/usb/hcd-ohci.c:734 - #1 ohci_service_ed_list ../hw/usb/hcd-ohci.c:1180 - #2 ohci_process_lists ../hw/usb/hcd-ohci.c:1214 - #3 ohci_frame_boundary ../hw/usb/hcd-ohci.c:1257 - #4 timerlist_run_timers ../util/qemu-timer.c:572 - #5 qemu_clock_run_timers ../util/qemu-timer.c:586 - #6 qemu_clock_run_all_timers ../util/qemu-timer.c:672 - #7 main_loop_wait ../util/main-loop.c:527 - #8 qemu_main_loop ../softmmu/vl.c:1676 - #9 main ../softmmu/main.c:50 - -Reported-by: Gaoning Pan <pgn@zju.edu.cn> -Reported-by: Yongkang Jia <j_kangel@163.com> -Reported-by: Yi Ren <yunye.ry@alibaba-inc.com> -Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> -Message-id: 20200915182259.68522-2-ppandit@redhat.com -Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> - -Upstream-Status: Backport -CVE: CVE-2020-25624 -[https://git.qemu.org/?p=qemu.git;a=commit;h=1328fe0c32d5474604105b8105310e944976b058] -Signed-off-by: Li Wang <li.wang@windriver.com> ---- - hw/usb/hcd-ohci.c | 24 ++++++++++++++++++++++-- - 1 file changed, 22 insertions(+), 2 deletions(-) - -diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c -index 1e6e85e..9dc5910 100644 ---- a/hw/usb/hcd-ohci.c -+++ b/hw/usb/hcd-ohci.c -@@ -731,7 +731,11 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, - } - - start_offset = iso_td.offset[relative_frame_number]; -- next_offset = iso_td.offset[relative_frame_number + 1]; -+ if (relative_frame_number < frame_count) { -+ next_offset = iso_td.offset[relative_frame_number + 1]; -+ } else { -+ next_offset = iso_td.be; -+ } - - if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || - ((relative_frame_number < frame_count) && -@@ -764,7 +768,12 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, - } - } else { - /* Last packet in the ISO TD */ -- end_addr = iso_td.be; -+ end_addr = next_offset; -+ } -+ -+ if (start_addr > end_addr) { -+ trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr); -+ return 1; - } - - if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { -@@ -773,6 +782,9 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, - } else { - len = end_addr - start_addr + 1; - } -+ if (len > sizeof(ohci->usb_buf)) { -+ len = sizeof(ohci->usb_buf); -+ } - - if (len && dir != OHCI_TD_DIR_IN) { - if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, -@@ -975,8 +987,16 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) - if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { - len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); - } else { -+ if (td.cbp > td.be) { -+ trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be); -+ ohci_die(ohci); -+ return 1; -+ } - len = (td.be - td.cbp) + 1; - } -+ if (len > sizeof(ohci->usb_buf)) { -+ len = sizeof(ohci->usb_buf); -+ } - - pktlen = len; - if (len && dir != OHCI_TD_DIR_IN) { --- -2.17.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-25723.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-25723.patch deleted file mode 100644 index 90b3a2f41..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-25723.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 2fdb42d840400d58f2e706ecca82c142b97bcbd6 Mon Sep 17 00:00:00 2001 -From: Li Qiang <liq3ea@163.com> -Date: Wed, 12 Aug 2020 09:17:27 -0700 -Subject: [PATCH] hw: ehci: check return value of 'usb_packet_map' - -If 'usb_packet_map' fails, we should stop to process the usb -request. - -Signed-off-by: Li Qiang <liq3ea@163.com> -Message-Id: <20200812161727.29412-1-liq3ea@163.com> -Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> - -Upstream-Status: Backport -CVE: CVE-2020-25723 -[https://git.qemu.org/?p=qemu.git;a=commit;h=2fdb42d840400d58f2e706ecca82c142b97bcbd6] -Signed-off-by: Li Wang <li.wang@windriver.com> ---- - hw/usb/hcd-ehci.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - -diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c -index 1495e8f..1fbb02a 100644 ---- a/hw/usb/hcd-ehci.c -+++ b/hw/usb/hcd-ehci.c -@@ -1373,7 +1373,10 @@ static int ehci_execute(EHCIPacket *p, const char *action) - spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0); - usb_packet_setup(&p->packet, p->pid, ep, 0, p->qtdaddr, spd, - (p->qtd.token & QTD_TOKEN_IOC) != 0); -- usb_packet_map(&p->packet, &p->sgl); -+ if (usb_packet_map(&p->packet, &p->sgl)) { -+ qemu_sglist_destroy(&p->sgl); -+ return -1; -+ } - p->async = EHCI_ASYNC_INITIALIZED; - } - -@@ -1452,7 +1455,10 @@ static int ehci_process_itd(EHCIState *ehci, - if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { - usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false, - (itd->transact[i] & ITD_XACT_IOC) != 0); -- usb_packet_map(&ehci->ipacket, &ehci->isgl); -+ if (usb_packet_map(&ehci->ipacket, &ehci->isgl)) { -+ qemu_sglist_destroy(&ehci->isgl); -+ return -1; -+ } - usb_handle_packet(dev, &ehci->ipacket); - usb_packet_unmap(&ehci->ipacket, &ehci->isgl); - } else { --- -2.17.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-28916.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-28916.patch deleted file mode 100644 index 521219683..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-28916.patch +++ /dev/null @@ -1,49 +0,0 @@ -From c2cb511634012344e3d0fe49a037a33b12d8a98a Mon Sep 17 00:00:00 2001 -From: Prasad J Pandit <pjp@fedoraproject.org> -Date: Wed, 11 Nov 2020 18:36:36 +0530 -Subject: [PATCH] hw/net/e1000e: advance desc_offset in case of null -descriptor - -While receiving packets via e1000e_write_packet_to_guest() routine, -'desc_offset' is advanced only when RX descriptor is processed. And -RX descriptor is not processed if it has NULL buffer address. -This may lead to an infinite loop condition. Increament 'desc_offset' -to process next descriptor in the ring to avoid infinite loop. - -Reported-by: Cheol-woo Myung <330cjfdn@gmail.com> -Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> -Signed-off-by: Jason Wang <jasowang@redhat.com> - -Upstream-Status: Backport -CVE: CVE-2020-28916 -[https://git.qemu.org/?p=qemu.git;a=commit;h=c2cb511634012344e3d0fe49a037a33b12d8a98a] -Signed-off-by: Li Wang <li.wang@windriver.com> ---- - hw/net/e1000e_core.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c -index bcd186c..d3e3cdc 100644 ---- a/hw/net/e1000e_core.c -+++ b/hw/net/e1000e_core.c -@@ -1596,13 +1596,13 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, - (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); - } - } -- desc_offset += desc_size; -- if (desc_offset >= total_size) { -- is_last = true; -- } - } else { /* as per intel docs; skip descriptors with null buf addr */ - trace_e1000e_rx_null_descriptor(); - } -+ desc_offset += desc_size; -+ if (desc_offset >= total_size) { -+ is_last = true; -+ } - - e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL, - rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); --- -2.17.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-29129-CVE-2020-29130.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-29129-CVE-2020-29130.patch deleted file mode 100644 index e5829f6da..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/CVE-2020-29129-CVE-2020-29130.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 2e1dcbc0c2af64fcb17009eaf2ceedd81be2b27f Mon Sep 17 00:00:00 2001 -From: Prasad J Pandit <pjp@fedoraproject.org> -Date: Thu, 26 Nov 2020 19:27:06 +0530 -Subject: [PATCH] slirp: check pkt_len before reading protocol header -MIME-Version: 1.0 -Content-Type: text/plain; charset=utf8 -Content-Transfer-Encoding: 8bit - -While processing ARP/NCSI packets in 'arp_input' or 'ncsi_input' -routines, ensure that pkt_len is large enough to accommodate the -respective protocol headers, lest it should do an OOB access. -Add check to avoid it. - -CVE-2020-29129 CVE-2020-29130 - QEMU: slirp: out-of-bounds access while processing ARP/NCSI packets - -> https://www.openwall.com/lists/oss-security/2020/11/27/1 - -Reported-by: Qiuhao Li <Qiuhao.Li@outlook.com> -Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> -Message-Id: <20201126135706.273950-1-ppandit@redhat.com> -Reviewed-by: Marc-Andrà Lureau <marcandre.lureau@redhat.com> - -Upstream-Status: Backport -CVE: CVE-2020-29129 CVE-2020-29130 -[https://git.qemu.org/?p=libslirp.git;a=commit;h=2e1dcbc0c2af64fcb17009eaf2ceedd81be2b27f] -Signed-off-by: Li Wang <li.wang@windriver.com> ---- - slirp/src/ncsi.c | 4 ++++ - slirp/src/slirp.c | 4 ++++ - 2 files changed, 8 insertions(+) - -diff --git a/slirp/src/ncsi.c b/slirp/src/ncsi.c -index 3c1dfef..75dcc08 100644 ---- a/slirp/src/ncsi.c -+++ b/slirp/src/ncsi.c -@@ -148,6 +148,10 @@ void ncsi_input(Slirp *slirp, const uint8_t *pkt, int pkt_len) - uint32_t checksum; - uint32_t *pchecksum; - -+ if (pkt_len < ETH_HLEN + sizeof(struct ncsi_pkt_hdr)) { -+ return; /* packet too short */ -+ } -+ - memset(ncsi_reply, 0, sizeof(ncsi_reply)); - - memset(reh->h_dest, 0xff, ETH_ALEN); -diff --git a/slirp/src/slirp.c b/slirp/src/slirp.c -index dba7c98..9be58e2 100644 ---- a/slirp/src/slirp.c -+++ b/slirp/src/slirp.c -@@ -756,6 +756,10 @@ static void arp_input(Slirp *slirp, const uint8_t *pkt, int pkt_len) - return; - } - -+ if (pkt_len < ETH_HLEN + sizeof(struct slirp_arphdr)) { -+ return; /* packet too short */ -+ } -+ - ar_op = ntohs(ah->ar_op); - switch (ar_op) { - case ARPOP_REQUEST: --- -2.17.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/find_datadir.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/find_datadir.patch deleted file mode 100644 index 9a4c11267..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/find_datadir.patch +++ /dev/null @@ -1,39 +0,0 @@ -qemu: search for datadir as in version 4.2 - -os_find_datadir() was changed after the 4.2 release. We need to check for -../share/qemu relative to the executable because that is where the runqemu -configuration assumes it will be. - -Upstream-Status: Submitted [qemu-devel@nongnu.org] - -Signed-off-by: Joe Slater <joe.slater@windriver.com> - - -Index: qemu-5.1.0/os-posix.c -=================================================================== ---- qemu-5.1.0.orig/os-posix.c -+++ qemu-5.1.0/os-posix.c -@@ -82,8 +82,9 @@ void os_setup_signal_handling(void) - - /* - * Find a likely location for support files using the location of the binary. -+ * Typically, this would be "$bindir/../share/qemu". - * When running from the build tree this will be "$bindir/../pc-bios". -- * Otherwise, this is CONFIG_QEMU_DATADIR. -+ * Otherwise, this is CONFIG_QEMU_DATADIR as constructed by configure. - * - * The caller must use g_free() to free the returned data when it is - * no longer required. -@@ -96,6 +97,12 @@ char *os_find_datadir(void) - exec_dir = qemu_get_exec_dir(); - g_return_val_if_fail(exec_dir != NULL, NULL); - -+ dir = g_build_filename(exec_dir, "..", "share", "qemu", NULL); -+ if (g_file_test(dir, G_FILE_TEST_IS_DIR)) { -+ return g_steal_pointer(&dir); -+ } -+ g_free(dir); /* no autofree this time */ -+ - dir = g_build_filename(exec_dir, "..", "pc-bios", NULL); - if (g_file_test(dir, G_FILE_TEST_IS_DIR)) { - return g_steal_pointer(&dir); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/powerpc_rom.bin b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/powerpc_rom.bin Binary files differdeleted file mode 100644 index c4044296c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/powerpc_rom.bin +++ /dev/null diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/run-ptest b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/run-ptest deleted file mode 100644 index b25a792d4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/run-ptest +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh -# -#This script is used to run qemu test suites -# - -ptestdir=$(dirname "$(readlink -f "$0")") -export SRC_PATH=$ptestdir - -cd $ptestdir/tests -make -f Makefile.include -k runtest-TESTS | sed '/^ok /s/ok /PASS: /g' diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/usb-fix-setup_len-init.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/usb-fix-setup_len-init.patch deleted file mode 100644 index 92801da46..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu/usb-fix-setup_len-init.patch +++ /dev/null @@ -1,89 +0,0 @@ -CVE: CVE-2020-14364 -Upstream-Status: Backport -Signed-off-by: Ross Burton <ross.burton@arm.com> - -From b946434f2659a182afc17e155be6791ebfb302eb Mon Sep 17 00:00:00 2001 -From: Gerd Hoffmann <kraxel@redhat.com> -Date: Tue, 25 Aug 2020 07:36:36 +0200 -Subject: [PATCH] usb: fix setup_len init (CVE-2020-14364) - -Store calculated setup_len in a local variable, verify it, and only -write it to the struct (USBDevice->setup_len) in case it passed the -sanity checks. - -This prevents other code (do_token_{in,out} functions specifically) -from working with invalid USBDevice->setup_len values and overrunning -the USBDevice->setup_buf[] buffer. - -Fixes: CVE-2020-14364 -Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> -Tested-by: Gonglei <arei.gonglei@huawei.com> -Reviewed-by: Li Qiang <liq3ea@gmail.com> -Message-id: 20200825053636.29648-1-kraxel@redhat.com ---- - hw/usb/core.c | 16 ++++++++++------ - 1 file changed, 10 insertions(+), 6 deletions(-) - -diff --git a/hw/usb/core.c b/hw/usb/core.c -index 5abd128b6bc..5234dcc73fe 100644 ---- a/hw/usb/core.c -+++ b/hw/usb/core.c -@@ -129,6 +129,7 @@ void usb_wakeup(USBEndpoint *ep, unsigned int stream) - static void do_token_setup(USBDevice *s, USBPacket *p) - { - int request, value, index; -+ unsigned int setup_len; - - if (p->iov.size != 8) { - p->status = USB_RET_STALL; -@@ -138,14 +139,15 @@ static void do_token_setup(USBDevice *s, USBPacket *p) - usb_packet_copy(p, s->setup_buf, p->iov.size); - s->setup_index = 0; - p->actual_length = 0; -- s->setup_len = (s->setup_buf[7] << 8) | s->setup_buf[6]; -- if (s->setup_len > sizeof(s->data_buf)) { -+ setup_len = (s->setup_buf[7] << 8) | s->setup_buf[6]; -+ if (setup_len > sizeof(s->data_buf)) { - fprintf(stderr, - "usb_generic_handle_packet: ctrl buffer too small (%d > %zu)\n", -- s->setup_len, sizeof(s->data_buf)); -+ setup_len, sizeof(s->data_buf)); - p->status = USB_RET_STALL; - return; - } -+ s->setup_len = setup_len; - - request = (s->setup_buf[0] << 8) | s->setup_buf[1]; - value = (s->setup_buf[3] << 8) | s->setup_buf[2]; -@@ -259,26 +261,28 @@ static void do_token_out(USBDevice *s, USBPacket *p) - static void do_parameter(USBDevice *s, USBPacket *p) - { - int i, request, value, index; -+ unsigned int setup_len; - - for (i = 0; i < 8; i++) { - s->setup_buf[i] = p->parameter >> (i*8); - } - - s->setup_state = SETUP_STATE_PARAM; -- s->setup_len = (s->setup_buf[7] << 8) | s->setup_buf[6]; - s->setup_index = 0; - - request = (s->setup_buf[0] << 8) | s->setup_buf[1]; - value = (s->setup_buf[3] << 8) | s->setup_buf[2]; - index = (s->setup_buf[5] << 8) | s->setup_buf[4]; - -- if (s->setup_len > sizeof(s->data_buf)) { -+ setup_len = (s->setup_buf[7] << 8) | s->setup_buf[6]; -+ if (setup_len > sizeof(s->data_buf)) { - fprintf(stderr, - "usb_generic_handle_packet: ctrl buffer too small (%d > %zu)\n", -- s->setup_len, sizeof(s->data_buf)); -+ setup_len, sizeof(s->data_buf)); - p->status = USB_RET_STALL; - return; - } -+ s->setup_len = setup_len; - - if (p->pid == USB_TOKEN_OUT) { - usb_packet_copy(p, s->data_buf, s->setup_len); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/run-postinsts/run-postinsts_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/run-postinsts/run-postinsts_%.bbappend deleted file mode 100644 index 3923fa2d5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/run-postinsts/run-postinsts_%.bbappend +++ /dev/null @@ -1,7 +0,0 @@ -# Update-alternatives is not able to find stdout when using JTAG boot mode on -# our devices, exits ungracefully without performing the required work (symbolic -# linking), pass kmsg to it as output to achieve proper behavior. - -do_install_append(){ - sed -i "s/sh -c \$i \$append_log/sh -c \$i > \/dev\/kmsg/" ${D}${sbindir}/run-postinsts -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/cairo/cairo_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/cairo/cairo_%.bbappend deleted file mode 100644 index c3f12f63a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/cairo/cairo_%.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -PACKAGECONFIG_zynqmp += "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11 xcb', '', d)} \ - egl glesv2" - -# OpenGL comes from libmali on ev/eg -DEPENDS_append_zynqmpev = " libmali-xlnx" -DEPENDS_append_zynqmpeg = " libmali-xlnx" - -PACKAGE_ARCH_zynqmpev = "${SOC_VARIANT_ARCH}" -PACKAGE_ARCH_zynqmpeg = "${SOC_VARIANT_ARCH}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/egl.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/egl.pc deleted file mode 100644 index 65c4c1f3a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/egl.pc +++ /dev/null @@ -1,12 +0,0 @@ -prefix=/usr -exec_prefix=${prefix} -libdir=/usr/lib -includedir=/usr/include - -Name: egl -Description: MALI EGL library -Requires.private: -Version: 17.3 -Libs: -L${libdir} -lEGL -Libs.private: -lm -lpthread -ldl -Cflags: -I${includedir} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/gbm.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/gbm.pc deleted file mode 100644 index c40b5f4fd..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/gbm.pc +++ /dev/null @@ -1,12 +0,0 @@ -prefix=/usr -exec_prefix=${prefix} -libdir=/usr/lib -includedir=/usr/include - -Name: gbm -Description: MALI gbm library -Requires.private: -Version: 17.3 -Libs: -L${libdir} -lgbm -Libs.private: -lm -lpthread -ldl -Cflags: -I${includedir} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1.pc deleted file mode 100644 index 39467f332..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1.pc +++ /dev/null @@ -1,12 +0,0 @@ -prefix=/usr -exec_prefix=${prefix} -libdir=/usr/lib -includedir=/usr/include - -Name: glesv1 -Description: MALI OpenGL ES 1.1 library -Requires.private: -Version: 17.3 -Libs: -L${libdir} -lGLESv1_CM -Libs.private: -lm -lpthread -ldl -Cflags: -I${includedir} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1_cm.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1_cm.pc deleted file mode 100644 index 1547b4c82..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1_cm.pc +++ /dev/null @@ -1,12 +0,0 @@ -prefix=/usr -exec_prefix=${prefix} -libdir=/usr/lib -includedir=/usr/include - -Name: gles_cm -Description: Mali OpenGL ES 1.1 CM library -Requires.private: -Version: 17.3 -Libs: -L${libdir} -lGLESv1_CM -Libs.private: -lm -lpthread -ldl -Cflags: -I${includedir} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv2.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv2.pc deleted file mode 100644 index a0a84f233..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv2.pc +++ /dev/null @@ -1,12 +0,0 @@ -prefix=/usr -exec_prefix=${prefix} -libdir=/usr/lib -includedir=/usr/include - -Name: glesv2 -Description: MALI OpenGL ES 2.0 library -Requires.private: -Version: 17.3 -Libs: -L${libdir} -lGLESv2 -Libs.private: -lm -lpthread -ldl -Cflags: -I${includedir} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb deleted file mode 100644 index 5c45b2baf..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb +++ /dev/null @@ -1,201 +0,0 @@ -DESCRIPTION = "libGLES for ZynqMP with Mali 400" - -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://EULA;md5=82e466d0ed92c5a15f568dbe6b31089c" - -inherit features_check update-alternatives - -ANY_OF_DISTRO_FEATURES = "x11 fbdev wayland" - -PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl virtual/libgbm" - -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" - -REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https" -BRANCH ?= "rel-v2020.2" -SRCREV ?= "da73805e3e011382c4d014ac10037cd193aaa9a0" -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" - -PV = "r9p0-01rel0" -SRC_URI = " \ - ${REPO};${BRANCHARG} \ - file://egl.pc \ - file://glesv1_cm.pc \ - file://glesv1.pc \ - file://glesv2.pc \ - file://gbm.pc \ - " - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmpeg = "zynqmpeg" -COMPATIBLE_MACHINE_zynqmpev = "zynqmpev" - -PACKAGE_ARCH = "${SOC_VARIANT_ARCH}" - - -S = "${WORKDIR}/git" - -# If were switching at runtime, we would need all RDEPENDS needed for all backends available -X11RDEPENDS = "libxdamage libxext libx11 libdrm libxfixes" -X11DEPENDS = "libxdamage libxext virtual/libx11 libdrm libxfixes" - -# Don't install runtime dependencies for other backends unless the DISTRO supports it -RDEPENDS_${PN} = " \ - kernel-module-mali \ - ${@bb.utils.contains('DISTRO_FEATURES', 'x11', '${X11RDEPENDS}', '', d)} \ -" - -# We dont build anything but we want to avoid QA warning build-deps -DEPENDS = "\ - ${@bb.utils.contains('DISTRO_FEATURES', 'x11', '${X11DEPENDS}', '', d)} \ - ${@bb.utils.contains('DISTRO_FEATURES', 'wayland', 'wayland libdrm', '', d)} \ -" - - -# x11 is default, set to "fbdev" , "wayland", or "headless" if required -MALI_BACKEND_DEFAULT ?= "x11" - -USE_X11 = "${@bb.utils.contains("DISTRO_FEATURES", "x11", "yes", "no", d)}" -USE_FB = "${@bb.utils.contains("DISTRO_FEATURES", "fbdev", "yes", "no", d)}" -USE_WL = "${@bb.utils.contains("DISTRO_FEATURES", "wayland", "yes", "no", d)}" - -MONOLITHIC_LIBMALI = "libMali.so.9.0" - -do_install() { - #Identify the ARCH type - ${TARGET_PREFIX}gcc --version > ARCH_PLATFORM - if grep -q aarch64 "ARCH_PLATFORM"; then - ARCH_PLATFORM_DIR=aarch64-linux-gnu - else - ARCH_PLATFORM_DIR=arm-linux-gnueabihf - fi - - # install headers - install -d -m 0655 ${D}${includedir}/EGL - install -m 0644 ${S}/${PV}/glesHeaders/EGL/*.h ${D}${includedir}/EGL/ - install -d -m 0655 ${D}${includedir}/GLES - install -m 0644 ${S}/${PV}/glesHeaders/GLES/*.h ${D}${includedir}/GLES/ - install -d -m 0655 ${D}${includedir}/GLES2 - install -m 0644 ${S}/${PV}/glesHeaders/GLES2/*.h ${D}${includedir}/GLES2/ - install -d -m 0655 ${D}${includedir}/KHR - install -m 0644 ${S}/${PV}/glesHeaders/KHR/*.h ${D}${includedir}/KHR/ - - install -d ${D}${libdir}/pkgconfig - install -m 0644 ${WORKDIR}/egl.pc ${D}${libdir}/pkgconfig/egl.pc - install -m 0644 ${WORKDIR}/glesv2.pc ${D}${libdir}/pkgconfig/glesv2.pc - install -m 0644 ${WORKDIR}/glesv1.pc ${D}${libdir}/pkgconfig/glesv1.pc - install -m 0644 ${WORKDIR}/glesv1_cm.pc ${D}${libdir}/pkgconfig/glesv1_cm.pc - - install -d ${D}${libdir} - install -d ${D}${includedir} - - cp -a --no-preserve=ownership ${S}/${PV}/${ARCH_PLATFORM_DIR}/common/*.so* ${D}${libdir} - - install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/headless/${MONOLITHIC_LIBMALI} ${D}${libdir}/headless/${MONOLITHIC_LIBMALI} - ln -snf headless/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI} - - if [ "${USE_FB}" = "yes" ]; then - install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/fbdev/${MONOLITHIC_LIBMALI} ${D}${libdir}/fbdev/${MONOLITHIC_LIBMALI} - if [ "${MALI_BACKEND_DEFAULT}" = "fbdev" ]; then - ln -snf fbdev/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI} - fi - fi - if [ "${USE_X11}" = "yes" ]; then - install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/x11/${MONOLITHIC_LIBMALI} ${D}${libdir}/x11/${MONOLITHIC_LIBMALI} - if [ "${MALI_BACKEND_DEFAULT}" = "x11" ]; then - ln -snf x11/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI} - fi - else - # We cant rely on the fact that all apps will use pkgconfig correctly - sed -i -e 's/^#if defined(MESA_EGL_NO_X11_HEADERS)$/#if (1)/' ${D}${includedir}/EGL/eglplatform.h - fi - if [ "${USE_WL}" = "yes" ]; then - install -m 0644 ${S}/${PV}/glesHeaders/GBM/gbm.h ${D}${includedir}/ - install -m 0644 ${WORKDIR}/gbm.pc ${D}${libdir}/pkgconfig/gbm.pc - install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/wayland/${MONOLITHIC_LIBMALI} ${D}${libdir}/wayland/${MONOLITHIC_LIBMALI} - if [ "${MALI_BACKEND_DEFAULT}" = "wayland" ]; then - ln -snf wayland/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI} - fi - fi -} - - -# We need separate packages to provide multiple alternatives, at this point we install -# everything on the default one but that can be split if necessary -PACKAGES += "${PN}-x11 ${PN}-fbdev ${PN}-wayland ${PN}-headless" - -# This is default/common for all alternatives -ALTERNATIVE_LINK_NAME[libmali-xlnx] = "${libdir}/${MONOLITHIC_LIBMALI}" - - -# Declare alternatives and corresponding library location -ALTERNATIVE_${PN}-x11 = "libmali-xlnx" -ALTERNATIVE_TARGET_libmali-xlnx-x11[libmali-xlnx] = "${libdir}/x11/${MONOLITHIC_LIBMALI}" - -ALTERNATIVE_${PN}-fbdev = "libmali-xlnx" -ALTERNATIVE_TARGET_libmali-xlnx-fbdev[libmali-xlnx] = "${libdir}/fbdev/${MONOLITHIC_LIBMALI}" - -ALTERNATIVE_${PN}-wayland = "libmali-xlnx" -ALTERNATIVE_TARGET_libmali-xlnx-wayland[libmali-xlnx] = "${libdir}/wayland/${MONOLITHIC_LIBMALI}" - -ALTERNATIVE_${PN}-headless = "libmali-xlnx" -ALTERNATIVE_TARGET_libmali-xlnx-headless[libmali-xlnx] = "${libdir}/headless/${MONOLITHIC_LIBMALI}" - -# Set priorities according to what we prveiously defined -ALTERNATIVE_PRIORITY_libmali-xlnx-x11[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "x11", "20", "10", d)}" -ALTERNATIVE_PRIORITY_libmali-xlnx-fbdev[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "fbdev", "20", "10", d)}" -ALTERNATIVE_PRIORITY_libmali-xlnx-wayland[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "wayland", "20", "10", d)}" - -# If misconfigured, fallback to headless -ALTERNATIVE_PRIORITY_libmali-xlnx-headless[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "headless", "20", "15", d)}" - - -# Package gets renamed on the debian class, but we want to keep -xlnx -DEBIAN_NOAUTONAME_libmali-xlnx = "1" - -# Update alternatives will actually have separate postinst scripts (one for each package) -# This wont work for us, so we create a common postinst script and we pass that as the general -# libmali-xlnx postinst script, but we defer execution to run on first boot (pkg_postinst_ontarget). -# This will avoid ldconfig removing the symbolic links when creating the root filesystem. -python populate_packages_updatealternatives_append () { - # We need to remove the 'fake' libmali-xlnx before creating any links - libdir = d.getVar('libdir') - common_postinst = "#!/bin/sh\nrm " + libdir + "/${MONOLITHIC_LIBMALI}\n" - for pkg in (d.getVar('PACKAGES') or "").split(): - # Not all packages provide an alternative (e.g. ${PN}-lic) - postinst = d.getVar('pkg_postinst_%s' % pkg) - if postinst: - old_postinst = postinst - new_postinst = postinst.replace('#!/bin/sh','') - common_postinst += new_postinst - d.setVar('pkg_postinst_ontarget_%s' % 'libmali-xlnx', common_postinst) -} - - -# Inhibit warnings about files being stripped -INHIBIT_PACKAGE_DEBUG_SPLIT = "1" -INHIBIT_PACKAGE_STRIP = "1" -INHIBIT_SYSROOT_STRIP = "1" - -RREPLACES_${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2 libgbm" -RPROVIDES_${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2 libgbm" -RCONFLICTS_${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2 libgbm" - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. -EXCLUDE_FROM_WORLD = "1" -FILES_${PN} += "${libdir}/*" - -do_package_append() { - - shlibswork_dir = d.getVar('SHLIBSWORKDIR') - pkg_filename = d.getVar('PN') + ".list" - shlibs_file = os.path.join(shlibswork_dir, pkg_filename) - lines = "" - with open(shlibs_file, "r") as f: - lines = f.readlines() - with open(shlibs_file, "w") as f: - for line in lines: - if d.getVar('MALI_BACKEND_DEFAULT') in line.strip("\n"): - f.write(line) -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libglu/libglu_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libglu/libglu_%.bbappend deleted file mode 100644 index 56924658c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libglu/libglu_%.bbappend +++ /dev/null @@ -1 +0,0 @@ -DEPENDS_append_zynqmp = " virtual/libgles2" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb deleted file mode 100644 index 747ec724c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb +++ /dev/null @@ -1,53 +0,0 @@ -SUMMARY = "A Mali 400 Linux Kernel module" -SECTION = "kernel/modules" - -LICENSE = "GPLv2" -LIC_FILES_CHKSUM = " \ - file://linux/license/gpl/mali_kernel_license.h;md5=f5af2d61f4c1eb262cb6a557aaa1070a \ - " - -PV = "r9p0-01rel0" - -SRC_URI = " \ - https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-utgard-gpu/DX910-SW-99002-${PV}.tgz \ - file://0001-Change-Makefile-to-be-compatible-with-Yocto.patch \ - file://0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch \ - file://0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch \ - file://0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch \ - file://0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch \ - file://0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch \ - file://0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch \ - file://0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch\ - file://0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch\ - file://0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch\ - file://0014-linux-mali_-timer-Get-rid-of-init_timer.patch\ - file://0015-fix-driver-failed-to-check-map-error.patch \ - file://0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch \ - file://0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch \ - file://0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch \ - file://0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch \ - " -SRC_URI[md5sum] = "85ea110dd6675c70b7d01af87ec9633c" -SRC_URI[sha256sum] = "7a67127341d17640c1fff5dad80258fb2a37c8a2121b81525fe2327e4532ce2b" - -inherit module - -PARALLEL_MAKE = "-j 1" - -S = "${WORKDIR}/DX910-SW-99002-${PV}/driver/src/devicedrv/mali" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmpeg = "zynqmpeg" -COMPATIBLE_MACHINE_zynqmpev = "zynqmpev" - -PACKAGE_ARCH = "${SOC_VARIANT_ARCH}" - -EXTRA_OEMAKE = 'KDIR="${STAGING_KERNEL_DIR}" \ - ARCH="${ARCH}" \ - BUILD=release \ - MALI_PLATFORM="arm" \ - USING_DT=1 \ - MALI_SHARED_INTERRUPTS=1 \ - CROSS_COMPILE="${TARGET_PREFIX}" \ - MALI_QUIET=1 \ - ' diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch deleted file mode 100644 index 3c82f602a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 6d283b9aa3f7fb761da4cb076b47a62275fc4caa Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Date: Tue, 21 Nov 2017 03:57:25 -0800 -Subject: [PATCH 1/9] Change Makefile to be compatible with Yocto - -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> -Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Upstream Status: Inappropriate [Xilinx specific] ---- - driver/src/devicedrv/mali/Makefile | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - -diff --git a/driver/src/devicedrv/mali/Makefile b/driver/src/devicedrv/mali/Makefile -index 5a259fe..a6dd94c 100644 ---- Makefile -+++ b/Makefile -@@ -89,7 +89,11 @@ endif - # Define host system directory - KDIR-$(shell uname -m):=/lib/modules/$(shell uname -r)/build - --include $(KDIR)/.config -+ifeq ($(O),) -+ -include $(KDIR)/.config -+else -+ -include $(O)/.config -+endif - - ifeq ($(ARCH), arm) - # when compiling for ARM we're cross compiling -@@ -204,9 +208,12 @@ EXTRA_DEFINES += -DMALI_MEM_SWAP_TRACKING=1 - endif - - all: $(UMP_SYMVERS_FILE) -- $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) modules -+ $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) O=$(O) modules - @rm $(FILES_PREFIX)__malidrv_build_info.c $(FILES_PREFIX)__malidrv_build_info.o - -+modules_install: -+ $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) modules_install -+ - clean: - $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) clean - --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch deleted file mode 100644 index 0a7b6736f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch +++ /dev/null @@ -1,52 +0,0 @@ -From f27aab2b0e4d5dea9b5a0e4648c142257940c428 Mon Sep 17 00:00:00 2001 -From: Hyun Kwon <hyun.kwon@xilinx.com> -Date: Thu, 25 Jun 2015 17:14:42 -0700 -Subject: [PATCH 2/9] staging: mali: r8p0-01rel0: Add the ZYNQ/ZYNQMP platform - -Add the number of PP cores that is required for Zynq/ZynqMP configuration. - -Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> -Signed-off-by: Michal Simek <michal.simek@xilinx.com> -Upstream Status: Inappropriate [Xilinx specific] ---- - driver/src/devicedrv/mali/platform/arm/arm.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c -index 4e09aca..fac99bc 100644 ---- platform/arm/arm.c -+++ b/platform/arm/arm.c -@@ -261,6 +261,10 @@ static struct mali_gpu_device_data mali_gpu_data = { - .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */ - .dedicated_mem_size = 0x10000000, /* 256MB */ - #endif -+#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP) -+ .fb_start = 0x00000000, -+ .fb_size = 0xfffff000, -+#else - #if defined(CONFIG_ARM64) - /* Some framebuffer drivers get the framebuffer dynamically, such as through GEM, - * in which the memory resource can't be predicted in advance. -@@ -271,6 +275,7 @@ static struct mali_gpu_device_data mali_gpu_data = { - .fb_start = 0xe0000000, - .fb_size = 0x01000000, - #endif -+#endif /* !defined(CONFIG_ARCH_ZYNQ) && !defined(CONFIG_ARCH_ZYNQMP) */ - .control_interval = 1000, /* 1000ms */ - .utilization_callback = mali_gpu_utilization_callback, - .get_clock_info = NULL, -@@ -505,6 +510,11 @@ int mali_platform_device_init(struct platform_device *device) - mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */ - } - } -+#elif defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP) -+ -+ MALI_DEBUG_PRINT(4, ("Registering Zynq/ZynqMP Mali-400 device\n")); -+ num_pp_cores = 2; -+ - #endif - - /* After kernel 3.15 device tree will default set dev --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch deleted file mode 100644 index 98aa6ac93..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch +++ /dev/null @@ -1,35 +0,0 @@ -From d6e44bbf8d1377f78481f611dec237e8d24baf74 Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Date: Tue, 21 Nov 2017 04:00:27 -0800 -Subject: [PATCH 3/9] staging: mali: r8p0-01rel0: Remove unused trace macros - -TRACE_SYSTEM_STRING is not need in each trace file anymore. - -Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> -Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Upstream Status: Pending ---- - driver/src/devicedrv/mali/linux/mali_linux_trace.h | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/driver/src/devicedrv/mali/linux/mali_linux_trace.h b/driver/src/devicedrv/mali/linux/mali_linux_trace.h -index 7f0b19d..33cb1ca 100644 ---- linux/mali_linux_trace.h -+++ b/linux/mali_linux_trace.h -@@ -13,13 +13,11 @@ - - #include <linux/types.h> - --#include <linux/stringify.h> - #include <linux/tracepoint.h> - - #undef TRACE_SYSTEM - #define TRACE_SYSTEM mali - #ifndef TRACEPOINTS_ENABLED --#define TRACE_SYSTEM_STRING __stringfy(TRACE_SYSTEM) - #endif - #define TRACE_INCLUDE_PATH . - #define TRACE_INCLUDE_FILE mali_linux_trace --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch deleted file mode 100644 index c5c496796..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 2f5e8944357f43fbde4cb642c6ee4a699c88efb5 Mon Sep 17 00:00:00 2001 -From: Hyun Kwon <hyun.kwon@xilinx.com> -Date: Wed, 29 Jun 2016 09:14:37 -0700 -Subject: [PATCH 4/9] staging: mali: r8p0-01rel0: Don't include - mali_read_phys() for zynq/zynqmp - -mali_read_phys() is not used with CONFIG_ARCH_ZYNQ and CONFIG_ARCH_ZYNQMP. - -Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> -Upstream Status: Inappropriate [Xilinx specific] ---- - driver/src/devicedrv/mali/platform/arm/arm.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c -index fac99bc..62f9be6 100644 ---- platform/arm/arm.c -+++ b/platform/arm/arm.c -@@ -38,7 +38,9 @@ - static int mali_core_scaling_enable = 0; - - void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data); -+#if !(defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)) - static u32 mali_read_phys(u32 phys_addr); -+#endif - #if defined(CONFIG_ARCH_REALVIEW) - static void mali_write_phys(u32 phys_addr, u32 value); - #endif -@@ -578,6 +580,7 @@ int mali_platform_device_deinit(struct platform_device *device) - - #endif /* CONFIG_MALI_DT */ - -+#if !(defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)) - static u32 mali_read_phys(u32 phys_addr) - { - u32 phys_addr_page = phys_addr & 0xFFFFE000; -@@ -592,6 +595,7 @@ static u32 mali_read_phys(u32 phys_addr) - - return ret; - } -+#endif - - #if defined(CONFIG_ARCH_REALVIEW) - static void mali_write_phys(u32 phys_addr, u32 value) --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch deleted file mode 100644 index 3d7846042..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch +++ /dev/null @@ -1,90 +0,0 @@ -From e67e20ec6ff0c9720d87844270421453c738066a Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Date: Thu, 16 Feb 2017 12:15:58 -0800 -Subject: [PATCH 5/9] linux/mali_kernel_linux.c: Handle clock when probed and - removed - -This patch will handle the clock through clock -specifier for GPU PP0 and PP1. - -Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Upstream Status: Inappropriate [Xilinx specific] ---- - .../src/devicedrv/mali/linux/mali_kernel_linux.c | 40 +++++++++++++++++++++- - 1 file changed, 39 insertions(+), 1 deletion(-) - -diff --git a/driver/src/devicedrv/mali/linux/mali_kernel_linux.c b/driver/src/devicedrv/mali/linux/mali_kernel_linux.c -index d7893a3..f15fb56 100644 ---- linux/mali_kernel_linux.c -+++ b/linux/mali_kernel_linux.c -@@ -45,6 +45,14 @@ - #if defined(CONFIG_MALI400_INTERNAL_PROFILING) - #include "mali_profiling_internal.h" - #endif -+ -+#if defined(CONFIG_ARCH_ZYNQMP) -+/* Initialize variables for clocks */ -+struct clk *clk_gpu; -+struct clk *clk_gpu_pp0; -+struct clk *clk_gpu_pp1; -+#endif -+ - #if defined(CONFIG_MALI400_PROFILING) && defined(CONFIG_MALI_DVFS) - #include "mali_osk_profiling.h" - #include "mali_dvfs_policy.h" -@@ -580,7 +588,23 @@ static int mali_probe(struct platform_device *pdev) - } - #endif - -- -+#if defined(CONFIG_ARCH_ZYNQMP) -+ /* Initialize clocks for GPU and PP */ -+ clk_gpu = devm_clk_get(&pdev->dev, "gpu"); -+ if (IS_ERR(clk_gpu)) -+ return PTR_ERR(clk_gpu); -+ clk_prepare_enable(clk_gpu); -+ -+ clk_gpu_pp0 = devm_clk_get(&pdev->dev, "gpu_pp0"); -+ if (IS_ERR(clk_gpu_pp0)) -+ return PTR_ERR(clk_gpu_pp0); -+ clk_prepare_enable(clk_gpu_pp0); -+ -+ clk_gpu_pp1 = devm_clk_get(&pdev->dev, "gpu_pp1"); -+ if (IS_ERR(clk_gpu_pp1)) -+ return PTR_ERR(clk_gpu_pp1); -+ clk_prepare_enable(clk_gpu_pp1); -+#endif - if (_MALI_OSK_ERR_OK == _mali_osk_wq_init()) { - /* Initialize the Mali GPU HW specified by pdev */ - if (_MALI_OSK_ERR_OK == mali_initialize_subsystems()) { -@@ -608,6 +632,12 @@ static int mali_probe(struct platform_device *pdev) - _mali_osk_wq_term(); - } - -+#if defined(CONFIG_ARCH_ZYNQMP) -+ clk_disable_unprepare(clk_gpu); -+ clk_disable_unprepare(clk_gpu_pp0); -+ clk_disable_unprepare(clk_gpu_pp1); -+#endif -+ - #ifdef CONFIG_MALI_DEVFREQ - mali_devfreq_term(mdev); - devfreq_init_failed: -@@ -673,6 +703,14 @@ static int mali_remove(struct platform_device *pdev) - mali_platform_device_deinit(mali_platform_device); - #endif - mali_platform_device = NULL; -+ -+#if defined(CONFIG_ARCH_ZYNQMP) -+ /* Remove clock */ -+ clk_disable_unprepare(clk_gpu); -+ clk_disable_unprepare(clk_gpu_pp0); -+ clk_disable_unprepare(clk_gpu_pp1); -+#endif -+ - return 0; - } - --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch deleted file mode 100644 index 3e1745fd5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch +++ /dev/null @@ -1,35 +0,0 @@ -From ed7242238151c12029c566d1974058c579d8ae3d Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Date: Wed, 25 Jan 2017 10:00:33 -0800 -Subject: [PATCH 6/9] arm.c: global variable dma_ops is removed from the kernel - 4.7 - -Refer kernel commit 1dccb598df549d892b6450c261da54cdd7af44b4, the global -dma_ops variable and the special-casing for ACPI is removed , and just -returns the dma ops that got set for the device, or the dummy_dma_ops -if none were present. - -Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Upstream Status: Pending ---- - driver/src/devicedrv/mali/platform/arm/arm.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c -index 62f9be6..57ca989 100644 ---- platform/arm/arm.c -+++ b/platform/arm/arm.c -@@ -529,8 +529,9 @@ int mali_platform_device_init(struct platform_device *device) - */ - if (!device->dev.dma_mask) - device->dev.dma_mask = &device->dev.coherent_dma_mask; -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)) - device->dev.archdata.dma_ops = dma_ops; -- -+#endif - err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data)); - - if (0 == err) { --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch deleted file mode 100644 index 98a86c883..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 58e2c55176f1a146781430b2a570c8ce5f80d426 Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Date: Mon, 28 Aug 2017 09:40:37 -0700 -Subject: [PATCH] common/mali_pm.c: Add PM runtime barrier after removing - suspend - -Runtime PM suspend "put" results in addition of PM suspend -API in work queue. This barrier API will remove it from -the work queue. - -Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Upstream-Status: Pending ---- - driver/src/devicedrv/mali/common/mali_pm.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/driver/src/devicedrv/mali/common/mali_pm.c b/driver/src/devicedrv/mali/common/mali_pm.c -index 858c689..62a1e5f 100644 ---- common/mali_pm.c -+++ b/common/mali_pm.c -@@ -301,6 +301,7 @@ void mali_pm_init_end(void) - } - - _mali_osk_pm_dev_ref_put(); -+ _mali_osk_pm_dev_barrier(); - } - - void mali_pm_update_sync(void) --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch deleted file mode 100644 index 38ab4042d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch +++ /dev/null @@ -1,153 +0,0 @@ -From aeff13ad9e9ef73172a9325f669aefd3c0403dbb Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Date: Wed, 21 Feb 2018 16:52:15 -0800 -Subject: [PATCH] linux/mali_kernel_linux.c: Enable/disable clock for runtime - resume/suspend - -Enable/Disable the clock for GP,PP0 and PP1 during runtime -resume/suspend. - -Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> -Reviewed-by: Hyun Kwon <hyunk@xilinx.com> -Upstream Status: Inappropriate [Xilinx specific] ---- - .../src/devicedrv/mali/linux/mali_kernel_linux.c | 65 ++++++++++++++++++---- - 1 file changed, 54 insertions(+), 11 deletions(-) - -diff --git a/driver/src/devicedrv/mali/linux/mali_kernel_linux.c b/driver/src/devicedrv/mali/linux/mali_kernel_linux.c -index f15fb56..e61f33b 100644 ---- linux/mali_kernel_linux.c -+++ b/linux/mali_kernel_linux.c -@@ -51,6 +51,7 @@ - struct clk *clk_gpu; - struct clk *clk_gpu_pp0; - struct clk *clk_gpu_pp1; -+mali_bool clk_enabled; - #endif - - #if defined(CONFIG_MALI400_PROFILING) && defined(CONFIG_MALI_DVFS) -@@ -281,6 +282,46 @@ struct file_operations mali_fops = { - .mmap = mali_mmap - }; - -+static int mali_enable_clk(void) -+{ -+#if defined(CONFIG_ARCH_ZYNQMP) -+ int err = 0; -+ -+ if (clk_enabled) -+ return 0; -+ -+ clk_enabled = MALI_TRUE; -+ err = clk_prepare_enable(clk_gpu); -+ if (err) { -+ MALI_PRINT_ERROR(("Could not enable clock for GP\n\r")); -+ return err; -+ } -+ err = clk_prepare_enable(clk_gpu_pp0); -+ if (err) { -+ MALI_PRINT_ERROR(("Could not enable clock for PP0\n\r")); -+ return err; -+ } -+ err = clk_prepare_enable(clk_gpu_pp1); -+ if (err) { -+ MALI_PRINT_ERROR(("Could not enable clock for PP1\n\r")); -+ return err; -+ } -+#endif -+ return 0; -+} -+ -+static void mali_disable_clk(void) -+{ -+#if defined(CONFIG_ARCH_ZYNQMP) -+ if (clk_enabled) { -+ clk_enabled = MALI_FALSE; -+ clk_disable_unprepare(clk_gpu); -+ clk_disable_unprepare(clk_gpu_pp0); -+ clk_disable_unprepare(clk_gpu_pp1); -+ } -+#endif -+} -+ - #if MALI_ENABLE_CPU_CYCLES - void mali_init_cpu_time_counters(int reset, int enable_divide_by_64) - { -@@ -593,18 +634,19 @@ static int mali_probe(struct platform_device *pdev) - clk_gpu = devm_clk_get(&pdev->dev, "gpu"); - if (IS_ERR(clk_gpu)) - return PTR_ERR(clk_gpu); -- clk_prepare_enable(clk_gpu); - - clk_gpu_pp0 = devm_clk_get(&pdev->dev, "gpu_pp0"); - if (IS_ERR(clk_gpu_pp0)) - return PTR_ERR(clk_gpu_pp0); -- clk_prepare_enable(clk_gpu_pp0); - - clk_gpu_pp1 = devm_clk_get(&pdev->dev, "gpu_pp1"); - if (IS_ERR(clk_gpu_pp1)) - return PTR_ERR(clk_gpu_pp1); -- clk_prepare_enable(clk_gpu_pp1); - #endif -+ -+ err = mali_enable_clk(); -+ if (err) -+ return err; - if (_MALI_OSK_ERR_OK == _mali_osk_wq_init()) { - /* Initialize the Mali GPU HW specified by pdev */ - if (_MALI_OSK_ERR_OK == mali_initialize_subsystems()) { -@@ -632,11 +674,6 @@ static int mali_probe(struct platform_device *pdev) - _mali_osk_wq_term(); - } - --#if defined(CONFIG_ARCH_ZYNQMP) -- clk_disable_unprepare(clk_gpu); -- clk_disable_unprepare(clk_gpu_pp0); -- clk_disable_unprepare(clk_gpu_pp1); --#endif - - #ifdef CONFIG_MALI_DEVFREQ - mali_devfreq_term(mdev); -@@ -644,6 +681,7 @@ devfreq_init_failed: - mali_pm_metrics_term(mdev); - pm_metrics_init_failed: - clk_disable_unprepare(mdev->clock); -+ mali_disable_clk(); - clock_prepare_failed: - clk_put(mdev->clock); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_OF) \ -@@ -706,9 +744,7 @@ static int mali_remove(struct platform_device *pdev) - - #if defined(CONFIG_ARCH_ZYNQMP) - /* Remove clock */ -- clk_disable_unprepare(clk_gpu); -- clk_disable_unprepare(clk_gpu_pp0); -- clk_disable_unprepare(clk_gpu_pp1); -+ mali_disable_clk(); - #endif - - return 0; -@@ -816,6 +852,8 @@ static int mali_driver_runtime_suspend(struct device *dev) - devfreq_suspend_device(mdev->devfreq); - #endif - -+ mali_disable_clk(); -+ - return 0; - } else { - return -EBUSY; -@@ -824,6 +862,11 @@ static int mali_driver_runtime_suspend(struct device *dev) - - static int mali_driver_runtime_resume(struct device *dev) - { -+ int err ; -+ -+ err = mali_enable_clk(); -+ if (err) -+ return err; - #ifdef CONFIG_MALI_DEVFREQ - struct mali_device *mdev = dev_get_drvdata(dev); - if (!mdev) --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch deleted file mode 100644 index 24f0a22c4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 779b1883d56804ecd08fe7f57d6c01e3db4e893b Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Wed, 5 Dec 2018 18:07:29 -0800 -Subject: [PATCH 1/3] linux: mali_memory_os_alloc: Remove __GFP_COLD - -The support for Cache hot and cold pages are removed from the kernel. -For more information refer kernel commit 453f85d43fa9ee243f0fc3ac4e1be45615301e3f - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> -Upstream Status: Pending ---- - driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c -index 1602371..830e8c6 100644 ---- linux/mali_memory_os_alloc.c -+++ b/linux/mali_memory_os_alloc.c -@@ -202,7 +202,9 @@ int mali_mem_os_alloc_pages(mali_mem_os_mem *os_mem, u32 size) - /* Allocate new pages, if needed. */ - for (i = 0; i < remaining; i++) { - dma_addr_t dma_addr; --#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) -+ gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN; -+#elif LINUX_VERSION_CODE == KERNEL_VERSION(4, 14, 0) - gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN | __GFP_COLD; - #else - gfp_t flags = __GFP_ZERO | __GFP_REPEAT | __GFP_NOWARN | __GFP_COLD; --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch deleted file mode 100644 index c28a83f47..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch +++ /dev/null @@ -1,34 +0,0 @@ -From d20b6eb3e48e56558488dbdda98875b1aed0c29f Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Wed, 5 Dec 2018 18:13:28 -0800 -Subject: [PATCH 2/3] linux: mali_memory_secure: Add header file dma-direct.h - -Add dma-direct.h header, as API dma_to_phys is defined here. -refer kernel commit ea8c64ace86647260ec4255f483e5844d62af2df - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> -Upstream Status: Pending ---- - driver/src/devicedrv/mali/linux/mali_memory_secure.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/driver/src/devicedrv/mali/linux/mali_memory_secure.c b/driver/src/devicedrv/mali/linux/mali_memory_secure.c -index 2836b1b..4f55fa5 100644 ---- linux/mali_memory_secure.c -+++ b/linux/mali_memory_secure.c -@@ -13,7 +13,11 @@ - #include "mali_memory_secure.h" - #include "mali_osk.h" - #include <linux/mutex.h> -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0) -+#include <linux/dma-direct.h> -+#else - #include <linux/dma-mapping.h> -+#endif - #include <linux/dma-buf.h> - - _mali_osk_errcode_t mali_mem_secure_attach_dma_buf(mali_mem_secure *secure_mem, u32 size, int mem_fd) --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch deleted file mode 100644 index a7c1d5cc6..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch +++ /dev/null @@ -1,156 +0,0 @@ -From b6936450484b5aa9dd2438367a907af020341d1d Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Thu, 6 Dec 2018 13:30:44 -0800 -Subject: [PATCH 3/3] linux: mali_*timer: Get rid of init_timer - -kernel 4.19 got rid of ancient init_timer. Hence, replace it with -timer_setup API. For more information refer kernel commit -7eeb6b893bd28c68b6d664de1d3120e49b855cdb - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> -Upstream Status: Pending ---- - driver/src/devicedrv/mali/common/mali_control_timer.c | 6 ++++++ - driver/src/devicedrv/mali/common/mali_group.c | 6 ++++++ - driver/src/devicedrv/mali/common/mali_osk.h | 15 ++++++++++++++- - driver/src/devicedrv/mali/linux/mali_osk_timers.c | 15 ++++++++++++++- - 4 files changed, 40 insertions(+), 2 deletions(-) - -diff --git a/driver/src/devicedrv/mali/common/mali_control_timer.c b/driver/src/devicedrv/mali/common/mali_control_timer.c -index 1296ffe..d24b934 100644 ---- common/mali_control_timer.c -+++ b/common/mali_control_timer.c -@@ -65,11 +65,17 @@ _mali_osk_errcode_t mali_control_timer_init(void) - } - } - -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+ mali_control_timer = _mali_osk_timer_init(mali_control_timer_callback); -+#else - mali_control_timer = _mali_osk_timer_init(); -+#endif - if (NULL == mali_control_timer) { - return _MALI_OSK_ERR_FAULT; - } -+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) - _mali_osk_timer_setcallback(mali_control_timer, mali_control_timer_callback, NULL); -+#endif - - return _MALI_OSK_ERR_OK; - } -diff --git a/driver/src/devicedrv/mali/common/mali_group.c b/driver/src/devicedrv/mali/common/mali_group.c -index 5c7b3f4..1702e9a 100644 ---- common/mali_group.c -+++ b/common/mali_group.c -@@ -65,9 +65,15 @@ struct mali_group *mali_group_create(struct mali_l2_cache_core *core, - - group = _mali_osk_calloc(1, sizeof(struct mali_group)); - if (NULL != group) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+ group->timeout_timer = _mali_osk_timer_init(mali_group_timeout); -+#else - group->timeout_timer = _mali_osk_timer_init(); -+#endif - if (NULL != group->timeout_timer) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) - _mali_osk_timer_setcallback(group->timeout_timer, mali_group_timeout, (void *)group); -+#endif - - group->l2_cache_core[0] = core; - _mali_osk_list_init(&group->group_list); -diff --git a/driver/src/devicedrv/mali/common/mali_osk.h b/driver/src/devicedrv/mali/common/mali_osk.h -index a501778..fe93d79 100644 ---- common/mali_osk.h -+++ b/common/mali_osk.h -@@ -947,7 +947,17 @@ _mali_osk_errcode_t _mali_osk_notification_queue_dequeue(_mali_osk_notification_ - * asked for. - * - * @{ */ -- -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+/** @brief Initialize a timer -+ * -+ * Allocates resources for a new timer, and initializes them. This does not -+ * start the timer. -+ * -+ * @param callback Function to call when timer expires -+ * @return a pointer to the allocated timer object, or NULL on failure. -+ */ -+_mali_osk_timer_t *_mali_osk_timer_init(_mali_osk_timer_callback_t callback); -+#else - /** @brief Initialize a timer - * - * Allocates resources for a new timer, and initializes them. This does not -@@ -956,6 +966,7 @@ _mali_osk_errcode_t _mali_osk_notification_queue_dequeue(_mali_osk_notification_ - * @return a pointer to the allocated timer object, or NULL on failure. - */ - _mali_osk_timer_t *_mali_osk_timer_init(void); -+#endif - - /** @brief Start a timer - * -@@ -1034,6 +1045,7 @@ void _mali_osk_timer_del_async(_mali_osk_timer_t *tim); - */ - mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim); - -+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) - /** @brief Set a timer's callback parameters. - * - * This must be called at least once before a timer is started/modified. -@@ -1047,6 +1059,7 @@ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim); - * @param data Function-specific data to supply to the function on expiry. - */ - void _mali_osk_timer_setcallback(_mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data); -+#endif - - /** @brief Terminate a timer, and deallocate resources. - * -diff --git a/driver/src/devicedrv/mali/linux/mali_osk_timers.c b/driver/src/devicedrv/mali/linux/mali_osk_timers.c -index e5d7238..f9b5a86 100644 ---- linux/mali_osk_timers.c -+++ b/linux/mali_osk_timers.c -@@ -21,13 +21,24 @@ - struct _mali_osk_timer_t_struct { - struct timer_list timer; - }; -- -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+typedef void (*timer_timeout_function_t)(struct timer_list *); -+#else - typedef void (*timer_timeout_function_t)(unsigned long); -+#endif - -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+_mali_osk_timer_t *_mali_osk_timer_init(_mali_osk_timer_callback_t callback) -+#else - _mali_osk_timer_t *_mali_osk_timer_init(void) -+#endif - { - _mali_osk_timer_t *t = (_mali_osk_timer_t *)kmalloc(sizeof(_mali_osk_timer_t), GFP_KERNEL); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) -+ if (NULL != t) timer_setup(&t->timer, (timer_timeout_function_t)callback, 0); -+#else - if (NULL != t) init_timer(&t->timer); -+#endif - return t; - } - -@@ -62,12 +73,14 @@ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim) - return 1 == timer_pending(&(tim->timer)); - } - -+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) - void _mali_osk_timer_setcallback(_mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data) - { - MALI_DEBUG_ASSERT_POINTER(tim); - tim->timer.data = (unsigned long)data; - tim->timer.function = (timer_timeout_function_t)callback; - } -+#endif - - void _mali_osk_timer_term(_mali_osk_timer_t *tim) - { --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0015-fix-driver-failed-to-check-map-error.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0015-fix-driver-failed-to-check-map-error.patch deleted file mode 100644 index 5363c37e8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0015-fix-driver-failed-to-check-map-error.patch +++ /dev/null @@ -1,17 +0,0 @@ -Index: mali/linux/mali_memory_os_alloc.c -=================================================================== ---- mali.orig/linux/mali_memory_os_alloc.c -+++ mali/linux/mali_memory_os_alloc.c -@@ -239,8 +239,10 @@ int mali_mem_os_alloc_pages(mali_mem_os_ - /* Ensure page is flushed from CPU caches. */ - dma_addr = dma_map_page(&mali_platform_device->dev, new_page, - 0, _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL); -- dma_unmap_page(&mali_platform_device->dev, dma_addr, -- _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL); -+ err = dma_mapping_error(&mali_platform_device->dev, dma_addr); -+ if (likely(!err)) -+ dma_unmap_page(&mali_platform_device->dev, dma_addr, -+ _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL); - dma_addr = dma_map_page(&mali_platform_device->dev, new_page, - 0, _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL); - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch deleted file mode 100644 index dc8bbebf4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 8cf1dd43f3f25cb4afb84dfc3b0e7c02bc8f7f0c Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Mon, 24 Feb 2020 18:19:37 -0800 -Subject: [LINUX][rel-v2020.1][PATCH v1 1/3] mali_memory_secure: Kernel 5.0 - onwards 'access_ok' API does not take 'type' as input parameter - -'access_ok' no longer needs 'type' as input paramter from kernel 5.0 -onwards. - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> ---- - driver/src/devicedrv/mali/linux/mali_ukk_mem.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/driver/src/devicedrv/mali/linux/mali_ukk_mem.c b/driver/src/devicedrv/mali/linux/mali_ukk_mem.c -index 4ec57dc..270bb6d 100644 ---- linux/mali_ukk_mem.c -+++ b/linux/mali_ukk_mem.c -@@ -207,8 +207,13 @@ int mem_write_safe_wrapper(struct mali_session_data *session_data, _mali_uk_mem_ - kargs.ctx = (uintptr_t)session_data; - - /* Check if we can access the buffers */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) -+ if (!access_ok((const void __user *)kargs.dest, kargs.size) -+ || !access_ok((const void __user *)kargs.src, kargs.size)) { -+#else - if (!access_ok(VERIFY_WRITE, kargs.dest, kargs.size) - || !access_ok(VERIFY_READ, kargs.src, kargs.size)) { -+#endif - return -EINVAL; - } - -@@ -266,7 +271,11 @@ int mem_dump_mmu_page_table_wrapper(struct mali_session_data *session_data, _mal - goto err_exit; - - user_buffer = (void __user *)(uintptr_t)kargs.buffer; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) -+ if (!access_ok(user_buffer, kargs.size)) -+#else - if (!access_ok(VERIFY_WRITE, user_buffer, kargs.size)) -+#endif - goto err_exit; - - /* allocate temporary buffer (kernel side) to store mmu page table info */ --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch deleted file mode 100644 index 9c4bbee9f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch +++ /dev/null @@ -1,146 +0,0 @@ -From 953cab73b8bc487da330aa454abd7f8c7466737e Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Mon, 24 Feb 2020 18:32:16 -0800 -Subject: [LINUX][rel-v2020.1][PATCH v1 2/3] Support for vm_insert_pfn - deprecated from kernel 4.20 - -From kernel 4.20 onwards, support for vm_insert_pfn is deprecated. -Hence, replace the same with vmf_insert_pfn. - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> ---- - .../devicedrv/mali/linux/mali_memory_block_alloc.c | 6 +++++- - driver/src/devicedrv/mali/linux/mali_memory_cow.c | 14 ++++++++++++-- - .../src/devicedrv/mali/linux/mali_memory_os_alloc.c | 20 +++++++++++++++++--- - driver/src/devicedrv/mali/linux/mali_memory_secure.c | 7 ++++++- - 4 files changed, 40 insertions(+), 7 deletions(-) - -diff --git a/driver/src/devicedrv/mali/linux/mali_memory_block_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_block_alloc.c -index 0c5b6c3..e528699 100644 ---- linux/mali_memory_block_alloc.c -+++ b/linux/mali_memory_block_alloc.c -@@ -309,9 +309,13 @@ int mali_mem_block_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *v - - list_for_each_entry(m_page, &block_mem->pfns, list) { - MALI_DEBUG_ASSERT(m_page->type == MALI_PAGE_NODE_BLOCK); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page)); -+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page)); -- - if (unlikely(0 != ret)) { -+#endif - return -EFAULT; - } - addr += _MALI_OSK_MALI_PAGE_SIZE; -diff --git a/driver/src/devicedrv/mali/linux/mali_memory_cow.c b/driver/src/devicedrv/mali/linux/mali_memory_cow.c -index f1d44fe..1dae1d6 100644 ---- linux/mali_memory_cow.c -+++ b/linux/mali_memory_cow.c -@@ -532,9 +532,14 @@ int mali_mem_cow_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *vma - * flush which makes it way slower than remap_pfn_range or vm_insert_pfn.
- ret = vm_insert_page(vma, addr, page);
- */
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page));
-+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page));
--
- if (unlikely(0 != ret)) {
-+#endif -+
- return ret;
- }
- addr += _MALI_OSK_MALI_PAGE_SIZE;
-@@ -569,9 +574,14 @@ _mali_osk_errcode_t mali_mem_cow_cpu_map_pages_locked(mali_mem_backend *mem_bken -
- list_for_each_entry(m_page, &cow->pages, list) {
- if ((count >= offset) && (count < offset + num)) {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, vaddr, _mali_page_node_get_pfn(m_page));
-+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, vaddr, _mali_page_node_get_pfn(m_page));
--
- if (unlikely(0 != ret)) {
-+#endif -+
- if (count == offset) {
- return _MALI_OSK_ERR_FAULT;
- } else {
-diff --git a/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c -index 3fb6f05..7de3920 100644 ---- linux/mali_memory_os_alloc.c -+++ b/linux/mali_memory_os_alloc.c -@@ -378,9 +378,14 @@ int mali_mem_os_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *vma) - ret = vm_insert_page(vma, addr, page); - */ - page = m_page->page; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, addr, page_to_pfn(page)); -+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, addr, page_to_pfn(page)); -- - if (unlikely(0 != ret)) { -+#endif -+ - return -EFAULT; - } - addr += _MALI_OSK_MALI_PAGE_SIZE; -@@ -416,9 +421,13 @@ _mali_osk_errcode_t mali_mem_os_resize_cpu_map_locked(mali_mem_backend *mem_bken - - vm_end -= _MALI_OSK_MALI_PAGE_SIZE; - if (mapping_page_num > 0) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, vm_end, page_to_pfn(m_page->page)); -+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, vm_end, page_to_pfn(m_page->page)); -- - if (unlikely(0 != ret)) { -+#endif - /*will return -EBUSY If the page has already been mapped into table, but it's OK*/ - if (-EBUSY == ret) { - break; -@@ -439,9 +448,14 @@ _mali_osk_errcode_t mali_mem_os_resize_cpu_map_locked(mali_mem_backend *mem_bken - list_for_each_entry(m_page, &os_mem->pages, list) { - if (count >= offset) { - -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, vstart, page_to_pfn(m_page->page)); -+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, vstart, page_to_pfn(m_page->page)); -- - if (unlikely(0 != ret)) { -+#endif -+ - /*will return -EBUSY If the page has already been mapped into table, but it's OK*/ - if (-EBUSY == ret) { - break; -diff --git a/driver/src/devicedrv/mali/linux/mali_memory_secure.c b/driver/src/devicedrv/mali/linux/mali_memory_secure.c -index 5546304..cebd1c8 100644 ---- linux/mali_memory_secure.c -+++ b/linux/mali_memory_secure.c -@@ -132,9 +132,14 @@ int mali_mem_secure_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct * - MALI_DEBUG_ASSERT(0 == size % _MALI_OSK_MALI_PAGE_SIZE); - - for (j = 0; j < size / _MALI_OSK_MALI_PAGE_SIZE; j++) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ ret = vmf_insert_pfn(vma, addr, PFN_DOWN(phys)); -+ if (unlikely(VM_FAULT_ERROR & ret)) { -+#else - ret = vm_insert_pfn(vma, addr, PFN_DOWN(phys)); -- - if (unlikely(0 != ret)) { -+#endif -+ - return -EFAULT; - } - addr += _MALI_OSK_MALI_PAGE_SIZE; --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch deleted file mode 100644 index 9797db629..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch +++ /dev/null @@ -1,32 +0,0 @@ -From ad5c569f0cc40698699fc2f2c1db3ceb9f8b8f35 Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Tue, 25 Feb 2020 11:36:01 -0800 -Subject: [LINUX][rel-v2020.1][PATCH v1 3/3] Change return type to vm_fault_t - for fault handler - -From kernel 4.17 onwards the return type of fault handler for -vm_operations is of type 'vm_fault_t'. - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> ---- - driver/src/devicedrv/mali/linux/mali_memory.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/driver/src/devicedrv/mali/linux/mali_memory.c b/driver/src/devicedrv/mali/linux/mali_memory.c -index c0f0982..2b2b209 100644 ---- linux/mali_memory.c -+++ b/linux/mali_memory.c -@@ -70,7 +70,9 @@ static void mali_mem_vma_close(struct vm_area_struct *vma) - } - } - --#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0) -+static vm_fault_t mali_mem_vma_fault(struct vm_fault *vmf) -+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) - static int mali_mem_vma_fault(struct vm_fault *vmf) - #else - static int mali_mem_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf) --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch deleted file mode 100644 index 154bb673e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch +++ /dev/null @@ -1,36 +0,0 @@ -From c6a6b39cea3fdfd91cae7f2a4ef6f36d2c55fdd6 Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Tue, 25 Feb 2020 15:17:17 -0800 -Subject: [LINUX][rel-v2020.1][PATCH v1] "get_monotonic_boottime(&ts)" - deprecated from kernel 4.20 onwards - -As "get_monotonic_boottime(&ts)" is deprecated, replace the same with -"ktime_get_boottime_ts64(&ts)". Refer kernel commit ID -976516404ff3fab2a8caa8bd6f5efc1437fed0b8 - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> ---- - driver/src/devicedrv/mali/linux/mali_osk_time.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/driver/src/devicedrv/mali/linux/mali_osk_time.c b/driver/src/devicedrv/mali/linux/mali_osk_time.c -index 03046a5..bfcbf7f 100644 ---- linux/mali_osk_time.c -+++ b/linux/mali_osk_time.c -@@ -53,7 +53,13 @@ u64 _mali_osk_time_get_ns(void) - - u64 _mali_osk_boot_time_get_ns(void) - { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) -+ struct timespec64 tsval; -+ ktime_get_boottime_ts64(&tsval); -+ return (u64)timespec64_to_ns(&tsval); -+#else - struct timespec tsval; - get_monotonic_boottime(&tsval); - return (u64)timespec_to_ns(&tsval); -+#endif - } --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mesa/mesa-demos_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mesa/mesa-demos_%.bbappend deleted file mode 100644 index febf1636d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mesa/mesa-demos_%.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -# OpenGL comes from libmali on ev/eg, when egl is enabled -DEPENDS_MALI_XLNX = "${@bb.utils.contains('PACKAGECONFIG', 'egl', 'libmali-xlnx', '', d)}" -PKG_ARCH_XLNX = "${@bb.utils.contains('PACKAGECONFIG', 'egl', '${SOC_VARIANT_ARCH}', '${TUNE_PKGARCH}', d)}" - -DEPENDS_append_zynqmpev = " ${DEPENDS_MALI_XLNX}" -DEPENDS_append_zynqmpeg = " ${DEPENDS_MALI_XLNX}" - -PACKAGE_ARCH_zynqmpev = "${PKG_ARCH_XLNX}" -PACKAGE_ARCH_zynqmpeg = "${PKG_ARCH_XLNX}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mesa/mesa-gl_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mesa/mesa-gl_%.bbappend deleted file mode 100644 index bcfefa1e1..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mesa/mesa-gl_%.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -do_install_append_zynqmp () { - rm -rf ${D}${includedir}/KHR/* -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/wayland/weston_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/wayland/weston_%.bbappend deleted file mode 100644 index febf1636d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/wayland/weston_%.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -# OpenGL comes from libmali on ev/eg, when egl is enabled -DEPENDS_MALI_XLNX = "${@bb.utils.contains('PACKAGECONFIG', 'egl', 'libmali-xlnx', '', d)}" -PKG_ARCH_XLNX = "${@bb.utils.contains('PACKAGECONFIG', 'egl', '${SOC_VARIANT_ARCH}', '${TUNE_PKGARCH}', d)}" - -DEPENDS_append_zynqmpev = " ${DEPENDS_MALI_XLNX}" -DEPENDS_append_zynqmpeg = " ${DEPENDS_MALI_XLNX}" - -PACKAGE_ARCH_zynqmpev = "${PKG_ARCH_XLNX}" -PACKAGE_ARCH_zynqmpeg = "${PKG_ARCH_XLNX}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/files/0001-libweston-Remove-substitute-format-for-ARGB8888.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/files/0001-libweston-Remove-substitute-format-for-ARGB8888.patch deleted file mode 100644 index 33d33b0f5..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/files/0001-libweston-Remove-substitute-format-for-ARGB8888.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 3fbb596e53524e78703b76c4fdc33cd6ac62f777 Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Fri, 11 Dec 2020 16:21:38 -0800 -Subject: [PATCH] libweston: Remove substitute format for ARGB8888 - -Xilinx DP gfx layer does not support XRGB8888. Hence, remove the same -as opaque substitute. - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Upstream-Status : Inappropriate [Xilinx specific] ---- - libweston/pixel-formats.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/libweston/pixel-formats.c b/libweston/pixel-formats.c -index 79dc709..ec2d3b7 100644 ---- a/libweston/pixel-formats.c -+++ b/libweston/pixel-formats.c -@@ -193,7 +193,6 @@ static const struct pixel_format_info pixel_format_table[] = { - { - DRM_FORMAT(ARGB8888), - BITS_RGBA_FIXED(8, 8, 8, 8), -- .opaque_substitute = DRM_FORMAT_XRGB8888, - .depth = 32, - .bpp = 32, - GL_FORMAT(GL_BGRA_EXT), --- -2.17.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/files/weston.ini b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/files/weston.ini deleted file mode 100644 index 2ff81795c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/files/weston.ini +++ /dev/null @@ -1,6 +0,0 @@ -[core] -idle-time=0 - -gbm-format=rgb565 - -require-input=false diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/weston-init%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/weston-init%.bbappend deleted file mode 100644 index aaee7f5dc..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/weston-init%.bbappend +++ /dev/null @@ -1,7 +0,0 @@ -FILESEXTRAPATHS_prepend_zynqmp := "${THISDIR}/files:" - -SRC_URI_append_zynqmp = " file://weston.ini" - -do_install_append_zynqmp() { - install -Dm 0700 ${WORKDIR}/weston.ini ${D}/${sysconfdir}/xdg/weston/weston.ini -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/weston_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/weston_%.bbappend deleted file mode 100644 index d1912a814..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/weston/weston_%.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -FILESEXTRAPATHS_prepend_zynqmp := "${THISDIR}/files:" - -SRC_URI_append_zynqmp = " file://0001-libweston-Remove-substitute-format-for-ARGB8888.patch" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch deleted file mode 100644 index 2e0247944..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 497de8b16265468cacad880f4a371756924ae0c1 Mon Sep 17 00:00:00 2001 -From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> -Date: Tue, 14 Apr 2020 15:25:13 -0700 -Subject: [xf86-video-armsoc][PATCH v2] armsoc_driver.c: Bypass the exa layer - to free the root pixmap - -Since the root pixmap was allocated through miCreateScreenResources, -the exa layer is not aware of the pixmap resulting in the assertion -to fail. Instead, we can directly invoke fbDestroyPixmap, thereby -freeing the pixmap and avoiding a memory leak. - -Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> ---- - src/armsoc_driver.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/src/armsoc_driver.c b/src/armsoc_driver.c -index 3ace3c7..a4a1ba3 100644 ---- a/src/armsoc_driver.c -+++ b/src/armsoc_driver.c -@@ -1259,7 +1259,8 @@ ARMSOCCloseScreen(CLOSE_SCREEN_ARGS_DECL) - * we do it here, before calling the CloseScreen chain which would just free pScreen->devPrivate in fbCloseScreen() - */ - if (pScreen->devPrivate) { -- (void) (*pScreen->DestroyPixmap)(pScreen->devPrivate); -+ fbDestroyPixmap (pScreen->devPrivate); -+ armsoc_bo_unreference(pARMSOC->scanout); - pScreen->devPrivate = NULL; - } - --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch deleted file mode 100644 index bf2169ee3..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 630a8ea035fe2f075f6ea7f4bad0928f5b541c80 Mon Sep 17 00:00:00 2001 -From: Hyun Kwon <hyun.kwon@xilinx.com> -Date: Wed, 21 Jan 2015 11:53:19 -0800 -Subject: [PATCH] src: drmmode_xilinx: Add the dumb gem support for Xilinx - -Add the dumb gem support for Xilinx - -Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> -Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> -Upstream-Status: Pending ---- - src/Makefile.am | 3 +- - src/armsoc_driver.c | 1 + - src/drmmode_driver.h | 1 + - src/drmmode_xilinx/drmmode_xilinx.c | 76 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 80 insertions(+), 1 deletion(-) - create mode 100644 src/drmmode_xilinx/drmmode_xilinx.c - -diff --git a/src/Makefile.am b/src/Makefile.am -index 3b2601927c..db5f110fb2 100644 ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -43,7 +43,8 @@ armsoc_drv_ladir = @moduledir@/drivers - DRMMODE_SRCS = drmmode_exynos/drmmode_exynos.c \ - drmmode_pl111/drmmode_pl111.c \ - drmmode_kirin/drmmode_kirin.c \ -- drmmode_sti/drmmode_sti.c -+ drmmode_sti/drmmode_sti.c \ -+ drmmode_xilinx/drmmode_xilinx.c - - - armsoc_drv_la_SOURCES = \ -diff --git a/src/armsoc_driver.c b/src/armsoc_driver.c -index 83e74a7ed1..3ace3c7be5 100644 ---- a/src/armsoc_driver.c -+++ b/src/armsoc_driver.c -@@ -737,6 +737,7 @@ static struct drmmode_interface *get_drmmode_implementation(int drm_fd) - &pl111_interface, - &kirin_interface, - &sti_interface, -+ &xilinx_interface, - }; - int i; - -diff --git a/src/drmmode_driver.h b/src/drmmode_driver.h -index 879fc60ddc..18245d591a 100644 ---- a/src/drmmode_driver.h -+++ b/src/drmmode_driver.h -@@ -106,6 +106,7 @@ extern struct drmmode_interface exynos_interface; - extern struct drmmode_interface pl111_interface; - extern struct drmmode_interface kirin_interface; - extern struct drmmode_interface sti_interface; -+extern struct drmmode_interface xilinx_interface; - - - #endif -diff --git a/src/drmmode_xilinx/drmmode_xilinx.c b/src/drmmode_xilinx/drmmode_xilinx.c -new file mode 100644 -index 0000000000..f4faceb0b4 ---- /dev/null -+++ b/src/drmmode_xilinx/drmmode_xilinx.c -@@ -0,0 +1,76 @@ -+/* -+ * Xilinx X11 ARMSOC driver -+ * -+ * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com> -+ * -+ * Copyright (C) 2014 Xilinx, Inc. -+ * -+ * Based on drmmode_exynos.c -+ * -+ * Copyright © 2013 ARM Limited. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -+ * SOFTWARE. -+ * -+ */ -+ -+#include <stdlib.h> -+ -+#include <drm.h> -+#include <xf86drm.h> -+ -+#include "../drmmode_driver.h" -+ -+static int create_custom_gem(int fd, struct armsoc_create_gem *create_gem) -+{ -+ struct drm_mode_create_dumb arg; -+ int ret; -+ -+ memset(&arg, 0, sizeof(arg)); -+ arg.height = create_gem->height; -+ arg.width = create_gem->width; -+ arg.bpp = create_gem->bpp; -+ -+ ret = drmIoctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg); -+ if (ret) -+ return ret; -+ -+ create_gem->height = arg.height; -+ create_gem->width = arg.width; -+ create_gem->bpp = arg.bpp; -+ create_gem->handle = arg.handle; -+ create_gem->pitch = arg.pitch; -+ create_gem->size = arg.size; -+ -+ return 0; -+} -+ -+struct drmmode_interface xilinx_interface = { -+ "xlnx" /* name of drm driver */, -+ 1 /* use_page_flip_events */, -+ 1 /* use_early_display */, -+ 0 /* cursor width */, -+ 0 /* cursor_height */, -+ 0 /* cursor padding */, -+ HWCURSOR_API_NONE /* cursor_api */, -+ NULL /* init_plane_for_cursor */, -+ 0 /* vblank_query_supported */, -+ create_custom_gem /* create_custom_gem */, -+}; -+ --- -2.11.0 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend deleted file mode 100644 index 955398a3f..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend +++ /dev/null @@ -1,5 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/xf86-video-armsoc:" - -SRC_URI_append = " file://0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch \ - file://0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch \ - " diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf deleted file mode 100644 index 9ef39462a..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf +++ /dev/null @@ -1,27 +0,0 @@ -Section "InputDevice" - Identifier "System Mouse" - Driver "mouse" - Option "Device" "/dev/input/mouse0" -EndSection - -Section "InputDevice" - Identifier "System Keyboard" - Driver "kbd" - Option "Device" "/dev/input/event0" -EndSection - -Section "Device" - Identifier "ZynqMP" - Driver "armsoc" - Option "DRI2" "true" - Option "DRI2_PAGE_FLIP" "false" - Option "DRI2_WAIT_VSYNC" "true" - Option "SWcursorLCD" "false" - Option "DEBUG" "false" -EndSection - -Section "Screen" - Identifier "DefaultScreen" - Device "ZynqMP" - DefaultDepth 16 -EndSection diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend deleted file mode 100644 index 72d991c7e..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend +++ /dev/null @@ -1 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/dp/kernel-module-dp_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/dp/kernel-module-dp_git.bb deleted file mode 100755 index e5356d865..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/dp/kernel-module-dp_git.bb +++ /dev/null @@ -1,26 +0,0 @@ -SUMMARY = "Xilinx DisplayPort Linux Kernel module" -DESCRIPTION = "Out-of-tree DisplayPort(DP) kernel modules provider for aarch64 devices" -SECTION = "kernel/modules" -LICENSE = "GPLv2" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" - -XLNX_DP_VERSION = "5.4.0" -PV = "${XLNX_DP_VERSION}" - -S = "${WORKDIR}/git" - -BRANCH ?= "master" -REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https" -SRCREV ?= "a3a7dfe17cf610fd4186b11638e1ce6b78dc958a" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -inherit module - -EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" -COMPATIBLE_MACHINE_versal = "versal" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/dtc/python3-dtc_1.5.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/dtc/python3-dtc_1.5.1.bb deleted file mode 100644 index 08e356d43..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/dtc/python3-dtc_1.5.1.bb +++ /dev/null @@ -1,27 +0,0 @@ -SUMMARY = "Device Tree Compiler" -HOMEPAGE = "https://devicetree.org/" -DESCRIPTION = "The Device Tree Compiler is a tool used to manipulate the Open-Firmware-like device tree used by PowerPC kernels." -SECTION = "bootloader" -LICENSE = "GPLv2 | BSD" -DEPENDS = "flex-native bison-native swig-native" - -SRC_URI = "git://git.kernel.org/pub/scm/utils/dtc/dtc.git" - -UPSTREAM_CHECK_GITTAGREGEX = "v(?P<pver>\d+(\.\d+)+)" - -LIC_FILES_CHKSUM = "file://libfdt.i;beginline=1;endline=6;md5=afda088c974174a29108c8d80b5dce90" - -SRCREV = "60e0db3d65a1218b0d5a29474e769f28a18e3ca6" - -S = "${WORKDIR}/git/pylibfdt" - -DEPENDS += "libyaml dtc" - -inherit distutils3 - -do_configure_prepend() { - (cd ${S}/../ ; make version_gen.h ) -} - -BBCLASSEXTEND = "native nativesdk" - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb deleted file mode 100644 index b26ecd948..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb +++ /dev/null @@ -1,26 +0,0 @@ -SUMMARY = "Xilinx HDMI Linux Kernel module" -DESCRIPTION = "Out-of-tree HDMI kernel modules provider for MPSoC EG/EV devices" -SECTION = "kernel/modules" -LICENSE = "GPLv2" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=570506b747d768e7802376f932dff926" - -XLNX_HDMI_VERSION = "5.4.0" -PV = "${XLNX_HDMI_VERSION}" - -S = "${WORKDIR}/git" - -BRANCH ?= "rel-v2020.2" -REPO ?= "git://github.com/xilinx/hdmi-modules.git;protocol=https" -SRCREV ?= "2cbacc12910bab236e491c5aa44999fa16cbaea9" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -inherit module - -EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" -COMPATIBLE_MACHINE_versal = "versal" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux-firmware/linux-firmware_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux-firmware/linux-firmware_%.bbappend deleted file mode 100644 index eb64045a8..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux-firmware/linux-firmware_%.bbappend +++ /dev/null @@ -1,29 +0,0 @@ -# TIInit_11.8.32.bts is required for bluetooth support but this particular -# version is not available in the linux-firmware repository. -# -SRC_URI_append_ultra96 = "\ - https://git.ti.com/ti-bt/service-packs/blobs/raw/c290f8af9e388f37e509ecb111a1b64572b7c225/initscripts/TIInit_11.8.32.bts;name=TIInit_11.8.32 \ - " - -SRC_URI[TIInit_11.8.32.md5sum] = "b1e142773e8ef0537b93895ebe2fcae3" -SRC_URI[TIInit_11.8.32.sha256sum] = "962322c05857ad6b1fb81467bdfc59c125e04a6a8eaabf7f24b742ddd68c3bfa" - -do_install_append_ultra96() { - cp ${WORKDIR}/TIInit_11.8.32.bts ${D}${nonarch_base_libdir}/firmware/ti-connectivity/ - ( cd ${D}${nonarch_base_libdir}/firmware ; ln -sf ti-connectivity/* . ) - rm -f ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_7* - rm -f ${D}${nonarch_base_libdir}/firmware/TIInit_7* -} - -INSANE_SKIP_${PN} += "installed-vs-shipped" - -PACKAGES_remove_ultra96 = "${PN}-wl12xx" - -FILES_${PN}-wl18xx_ultra96 = " \ - ${nonarch_base_libdir}/firmware/wl18* \ - ${nonarch_base_libdir}/firmware/TI* \ - ${nonarch_base_libdir}/firmware/ti-connectivity/wl18* \ - ${nonarch_base_libdir}/firmware/ti-connectivity/TI* \ - " - -PACKAGE_ARCH_ultra96 = "${BOARD_ARCH}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-microblaze.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-microblaze.inc deleted file mode 100644 index e23a50e8c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-microblaze.inc +++ /dev/null @@ -1,5 +0,0 @@ -# MicroBlaze is a uImage target, but its not called 'uImage' instead it is called 'linux.bin.ub' -python () { - if d.getVar('KERNEL_IMAGETYPE', True).endswith('.ub'): - d.setVar('DEPENDS', "%s u-boot-mkimage-native" % d.getVar('DEPENDS', True)) -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bb deleted file mode 100644 index acb9938ff..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bb +++ /dev/null @@ -1,18 +0,0 @@ -# This recipe tracks the 'bleeding edge' linux-xlnx repository. -# Since this tree is frequently updated, AUTOREV is used to track its contents. -# -# To enable this recipe, set PREFERRED_PROVIDER_virtual/kernel = "linux-xlnx-dev" - -KBRANCH ?= "master" - -# Use the SRCREV for the last tagged revision of linux-xlnx. -SRCREV ?= '${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/kernel", "linux-xlnx-dev", "${AUTOREV}", "84fb0cc65aae5970471cbc54b0c89009b9b904af", d)}' - -# skip version sanity, because the version moves with AUTOREV -KERNEL_VERSION_SANITY_SKIP = "1" - -LINUX_VERSION ?= "4.9+" -LINUX_VERSION_EXTENSION ?= "-xilinx-dev" - -include linux-xlnx.inc - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc deleted file mode 100644 index a98fc8018..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc +++ /dev/null @@ -1,65 +0,0 @@ -# This version extension should match CONFIG_LOCALVERSION in defconfig -XILINX_RELEASE_VERSION ?= "" -LINUX_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" -PV = "${LINUX_VERSION}+git${SRCPV}" - -# Sources, by default allow for the use of SRCREV pointing to orphaned tags/commits -KBRANCH ?= "xlnx_rebase_v5.4" -SRCBRANCHARG = "${@['nobranch=1', 'branch=${KBRANCH}'][d.getVar('KBRANCH', True) != '']}" - -FILESOVERRIDES_append = ":${XILINX_RELEASE_VERSION}" -KERNELURI ?= "git://github.com/Xilinx/linux-xlnx.git;protocol=https;name=machine" -YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.4;destsuffix=yocto-kmeta" -SRC_URI = "${KERNELURI};${SRCBRANCHARG} ${YOCTO_META}" - -SRCREV_machine ?= "${SRCREV}" -SRCREV_meta ?= "33bd5e8ac6fa46d5d7891b6e850603159f095b1a" -SRCREV_FORMAT = "machine" - -require recipes-kernel/linux/linux-yocto.inc -require linux-microblaze.inc - -DESCRIPTION = "Xilinx Kernel" -LIC_FILES_CHKSUM = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814" - -EXTKERNELSRC = "${@'1' if d.getVar('EXTERNALSRC') else ''}" - -# Force the use of the KBUILD_DEFCONFIG even if some other defconfig was generated in the ${WORKDIR} -do_kernel_metadata_prepend () { - [ -n "${KBUILD_DEFCONFIG}" ] && [ -e ${WORKDIR}/defconfig ] && rm ${WORKDIR}/defconfig -} - -do_configure_prepend () { - if [ -n "${KBUILD_DEFCONFIG}" ] && [ -n "${EXTKERNELSRC}" ]; then - cp ${S}/arch/${ARCH}/configs/${KBUILD_DEFCONFIG} ${WORKDIR}/defconfig - fi -} - -inherit kernel-simpleimage - -# Default to be only compatible with specific machines or soc families -COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE_zynq = ".*" -COMPATIBLE_MACHINE_zynqmp = ".*" -COMPATIBLE_MACHINE_microblaze = ".*" -COMPATIBLE_MACHINE_versal = ".*" - -# Use DEFCONFIGs for configuring linux-xlnx kernels -KCONFIG_MODE ?= "alldefconfig" -KBUILD_DEFCONFIG_zynqmp = "xilinx_defconfig" -KBUILD_DEFCONFIG_zynq = "xilinx_zynq_defconfig" -KBUILD_DEFCONFIG_microblaze = "mmu_defconfig" -KBUILD_DEFCONFIG_versal = "xilinx_defconfig" - -# MicroBlaze BSP fragments -KERNEL_FEATURES_append_kc705-microblazeel = " bsp/xilinx/kc705-microblazeel-features/kc705-microblazeel-features.scc" - -KERNEL_FEATURES_append_zynqmp = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)}" - -KERNEL_FEATURES_append_zynqmp = "${@' features/xilinx/overlay_of/overlay_of.scc' if d.getVar('FPGA_MNGR_RECONFIG_ENABLE') == '1' else ''}" - -KERNEL_FEATURES_append_versal = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)} features/xilinx/hdmi-module/hdmi-module.scc" - -KERNEL_FEATURES_append_ultra96 = " bsp/xilinx/ultra96-zynqmp/mipi-config-ultra96.scc" - -KERNEL_FEATURES_append = " ${@bb.utils.contains('DISTRO_FEATURES', 'virtualization', ' features/ocicontainer/ocicontainer.scc', '', d)}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-libtraceevent-Fix-build-with-binutils-2.35.patch b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-libtraceevent-Fix-build-with-binutils-2.35.patch deleted file mode 100644 index 25bc9f5b3..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-libtraceevent-Fix-build-with-binutils-2.35.patch +++ /dev/null @@ -1,39 +0,0 @@ -From c2fd34d4311033120fa502aa8bd4723cdeee0103 Mon Sep 17 00:00:00 2001 -From: Ben Hutchings <ben@decadent.org.uk> -Date: Sat, 25 Jul 2020 02:06:23 +0100 -Subject: [PATCH] libtraceevent: Fix build with binutils 2.35 - -commit 39efdd94e314336f4acbac4c07e0f37bdc3bef71 upstream. - -In binutils 2.35, 'nm -D' changed to show symbol versions along with -symbol names, with the usual @@ separator. When generating -libtraceevent-dynamic-list we need just the names, so strip off the -version suffix if present. - -Signed-off-by: Ben Hutchings <ben@decadent.org.uk> -Tested-by: Salvatore Bonaccorso <carnil@debian.org> -Reviewed-by: Steven Rostedt <rostedt@goodmis.org> -Cc: linux-trace-devel@vger.kernel.org -Cc: stable@vger.kernel.org -Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - tools/lib/traceevent/plugins/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/lib/traceevent/plugins/Makefile b/tools/lib/traceevent/plugins/Makefile -index f440989..23c3535 100644 ---- a/tools/lib/traceevent/plugins/Makefile -+++ b/tools/lib/traceevent/plugins/Makefile -@@ -196,7 +196,7 @@ define do_generate_dynamic_list_file - xargs echo "U w W" | tr 'w ' 'W\n' | sort -u | xargs echo`;\ - if [ "$$symbol_type" = "U W" ];then \ - (echo '{'; \ -- $(NM) -u -D $1 | awk 'NF>1 {print "\t"$$2";"}' | sort -u;\ -+ $(NM) -u -D $1 | awk 'NF>1 {sub("@.*", "", $$2); print "\t"$$2";"}' | sort -u;\ - echo '};'; \ - ) > $2; \ - else \ --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-bench-Share-some-global-variables-to-fix-build-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-bench-Share-some-global-variables-to-fix-build-.patch deleted file mode 100644 index e938ccf3d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-bench-Share-some-global-variables-to-fix-build-.patch +++ /dev/null @@ -1,241 +0,0 @@ -From df35e878d0a51755fb500e2e8e29c7ebb0239756 Mon Sep 17 00:00:00 2001 -From: Arnaldo Carvalho de Melo <acme@redhat.com> -Date: Mon, 2 Mar 2020 12:09:38 -0300 -Subject: [PATCH] perf bench: Share some global variables to fix build with gcc - 10 - -commit e4d9b04b973b2dbce7b42af95ea70d07da1c936d upstream. - -Noticed with gcc 10 (fedora rawhide) that those variables were not being -declared as static, so end up with: - - ld: /tmp/build/perf/bench/epoll-wait.o:/git/perf/tools/perf/bench/epoll-wait.c:93: multiple definition of `end'; /tmp/build/perf/bench/futex-hash.o:/git/perf/tools/perf/bench/futex-hash.c:40: first defined here - ld: /tmp/build/perf/bench/epoll-wait.o:/git/perf/tools/perf/bench/epoll-wait.c:93: multiple definition of `start'; /tmp/build/perf/bench/futex-hash.o:/git/perf/tools/perf/bench/futex-hash.c:40: first defined here - ld: /tmp/build/perf/bench/epoll-wait.o:/git/perf/tools/perf/bench/epoll-wait.c:93: multiple definition of `runtime'; /tmp/build/perf/bench/futex-hash.o:/git/perf/tools/perf/bench/futex-hash.c:40: first defined here - ld: /tmp/build/perf/bench/epoll-ctl.o:/git/perf/tools/perf/bench/epoll-ctl.c:38: multiple definition of `end'; /tmp/build/perf/bench/futex-hash.o:/git/perf/tools/perf/bench/futex-hash.c:40: first defined here - ld: /tmp/build/perf/bench/epoll-ctl.o:/git/perf/tools/perf/bench/epoll-ctl.c:38: multiple definition of `start'; /tmp/build/perf/bench/futex-hash.o:/git/perf/tools/perf/bench/futex-hash.c:40: first defined here - ld: /tmp/build/perf/bench/epoll-ctl.o:/git/perf/tools/perf/bench/epoll-ctl.c:38: multiple definition of `runtime'; /tmp/build/perf/bench/futex-hash.o:/git/perf/tools/perf/bench/futex-hash.c:40: first defined here - make[4]: *** [/git/perf/tools/build/Makefile.build:145: /tmp/build/perf/bench/perf-in.o] Error 1 - -Prefix those with bench__ and add them to bench/bench.h, so that we can -share those on the tools needing to access those variables from signal -handlers. - -Acked-by: Thomas Gleixner <tglx@linutronix.de> -Cc: Adrian Hunter <adrian.hunter@intel.com> -Cc: Davidlohr Bueso <dave@stgolabs.net> -Cc: Jiri Olsa <jolsa@kernel.org> -Cc: Namhyung Kim <namhyung@kernel.org> -Link: http://lore.kernel.org/lkml/20200303155811.GD13702@kernel.org -Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> -Cc: Ben Hutchings <ben@decadent.org.uk> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - tools/perf/bench/bench.h | 4 ++++ - tools/perf/bench/epoll-ctl.c | 7 +++---- - tools/perf/bench/epoll-wait.c | 11 +++++------ - tools/perf/bench/futex-hash.c | 12 ++++++------ - tools/perf/bench/futex-lock-pi.c | 11 +++++------ - 5 files changed, 23 insertions(+), 22 deletions(-) - -diff --git a/tools/perf/bench/bench.h b/tools/perf/bench/bench.h -index fddb3ce..4aa6de1 100644 ---- a/tools/perf/bench/bench.h -+++ b/tools/perf/bench/bench.h -@@ -2,6 +2,10 @@ - #ifndef BENCH_H - #define BENCH_H - -+#include <sys/time.h> -+ -+extern struct timeval bench__start, bench__end, bench__runtime; -+ - /* - * The madvise transparent hugepage constants were added in glibc - * 2.13. For compatibility with older versions of glibc, define these -diff --git a/tools/perf/bench/epoll-ctl.c b/tools/perf/bench/epoll-ctl.c -index bb617e5..a7526c0 100644 ---- a/tools/perf/bench/epoll-ctl.c -+++ b/tools/perf/bench/epoll-ctl.c -@@ -35,7 +35,6 @@ - - static unsigned int nthreads = 0; - static unsigned int nsecs = 8; --struct timeval start, end, runtime; - static bool done, __verbose, randomize; - - /* -@@ -94,8 +93,8 @@ static void toggle_done(int sig __maybe_unused, - { - /* inform all threads that we're done for the day */ - done = true; -- gettimeofday(&end, NULL); -- timersub(&end, &start, &runtime); -+ gettimeofday(&bench__end, NULL); -+ timersub(&bench__end, &bench__start, &bench__runtime); - } - - static void nest_epollfd(void) -@@ -361,7 +360,7 @@ int bench_epoll_ctl(int argc, const char **argv) - - threads_starting = nthreads; - -- gettimeofday(&start, NULL); -+ gettimeofday(&bench__start, NULL); - - do_threads(worker, cpu); - -diff --git a/tools/perf/bench/epoll-wait.c b/tools/perf/bench/epoll-wait.c -index 7af6944..d1c5cb5 100644 ---- a/tools/perf/bench/epoll-wait.c -+++ b/tools/perf/bench/epoll-wait.c -@@ -90,7 +90,6 @@ - - static unsigned int nthreads = 0; - static unsigned int nsecs = 8; --struct timeval start, end, runtime; - static bool wdone, done, __verbose, randomize, nonblocking; - - /* -@@ -276,8 +275,8 @@ static void toggle_done(int sig __maybe_unused, - { - /* inform all threads that we're done for the day */ - done = true; -- gettimeofday(&end, NULL); -- timersub(&end, &start, &runtime); -+ gettimeofday(&bench__end, NULL); -+ timersub(&bench__end, &bench__start, &bench__runtime); - } - - static void print_summary(void) -@@ -287,7 +286,7 @@ static void print_summary(void) - - printf("\nAveraged %ld operations/sec (+- %.2f%%), total secs = %d\n", - avg, rel_stddev_stats(stddev, avg), -- (int) runtime.tv_sec); -+ (int)bench__runtime.tv_sec); - } - - static int do_threads(struct worker *worker, struct perf_cpu_map *cpu) -@@ -479,7 +478,7 @@ int bench_epoll_wait(int argc, const char **argv) - - threads_starting = nthreads; - -- gettimeofday(&start, NULL); -+ gettimeofday(&bench__start, NULL); - - do_threads(worker, cpu); - -@@ -519,7 +518,7 @@ int bench_epoll_wait(int argc, const char **argv) - qsort(worker, nthreads, sizeof(struct worker), cmpworker); - - for (i = 0; i < nthreads; i++) { -- unsigned long t = worker[i].ops/runtime.tv_sec; -+ unsigned long t = worker[i].ops / bench__runtime.tv_sec; - - update_stats(&throughput_stats, t); - -diff --git a/tools/perf/bench/futex-hash.c b/tools/perf/bench/futex-hash.c -index 8ba0c33..2177686 100644 ---- a/tools/perf/bench/futex-hash.c -+++ b/tools/perf/bench/futex-hash.c -@@ -37,7 +37,7 @@ static unsigned int nfutexes = 1024; - static bool fshared = false, done = false, silent = false; - static int futex_flag = 0; - --struct timeval start, end, runtime; -+struct timeval bench__start, bench__end, bench__runtime; - static pthread_mutex_t thread_lock; - static unsigned int threads_starting; - static struct stats throughput_stats; -@@ -103,8 +103,8 @@ static void toggle_done(int sig __maybe_unused, - { - /* inform all threads that we're done for the day */ - done = true; -- gettimeofday(&end, NULL); -- timersub(&end, &start, &runtime); -+ gettimeofday(&bench__end, NULL); -+ timersub(&bench__end, &bench__start, &bench__runtime); - } - - static void print_summary(void) -@@ -114,7 +114,7 @@ static void print_summary(void) - - printf("%sAveraged %ld operations/sec (+- %.2f%%), total secs = %d\n", - !silent ? "\n" : "", avg, rel_stddev_stats(stddev, avg), -- (int) runtime.tv_sec); -+ (int)bench__runtime.tv_sec); - } - - int bench_futex_hash(int argc, const char **argv) -@@ -161,7 +161,7 @@ int bench_futex_hash(int argc, const char **argv) - - threads_starting = nthreads; - pthread_attr_init(&thread_attr); -- gettimeofday(&start, NULL); -+ gettimeofday(&bench__start, NULL); - for (i = 0; i < nthreads; i++) { - worker[i].tid = i; - worker[i].futex = calloc(nfutexes, sizeof(*worker[i].futex)); -@@ -204,7 +204,7 @@ int bench_futex_hash(int argc, const char **argv) - pthread_mutex_destroy(&thread_lock); - - for (i = 0; i < nthreads; i++) { -- unsigned long t = worker[i].ops/runtime.tv_sec; -+ unsigned long t = worker[i].ops / bench__runtime.tv_sec; - update_stats(&throughput_stats, t); - if (!silent) { - if (nfutexes == 1) -diff --git a/tools/perf/bench/futex-lock-pi.c b/tools/perf/bench/futex-lock-pi.c -index d0cae81..30d9712 100644 ---- a/tools/perf/bench/futex-lock-pi.c -+++ b/tools/perf/bench/futex-lock-pi.c -@@ -37,7 +37,6 @@ static bool silent = false, multi = false; - static bool done = false, fshared = false; - static unsigned int nthreads = 0; - static int futex_flag = 0; --struct timeval start, end, runtime; - static pthread_mutex_t thread_lock; - static unsigned int threads_starting; - static struct stats throughput_stats; -@@ -64,7 +63,7 @@ static void print_summary(void) - - printf("%sAveraged %ld operations/sec (+- %.2f%%), total secs = %d\n", - !silent ? "\n" : "", avg, rel_stddev_stats(stddev, avg), -- (int) runtime.tv_sec); -+ (int)bench__runtime.tv_sec); - } - - static void toggle_done(int sig __maybe_unused, -@@ -73,8 +72,8 @@ static void toggle_done(int sig __maybe_unused, - { - /* inform all threads that we're done for the day */ - done = true; -- gettimeofday(&end, NULL); -- timersub(&end, &start, &runtime); -+ gettimeofday(&bench__end, NULL); -+ timersub(&bench__end, &bench__start, &bench__runtime); - } - - static void *workerfn(void *arg) -@@ -185,7 +184,7 @@ int bench_futex_lock_pi(int argc, const char **argv) - - threads_starting = nthreads; - pthread_attr_init(&thread_attr); -- gettimeofday(&start, NULL); -+ gettimeofday(&bench__start, NULL); - - create_threads(worker, thread_attr, cpu); - pthread_attr_destroy(&thread_attr); -@@ -211,7 +210,7 @@ int bench_futex_lock_pi(int argc, const char **argv) - pthread_mutex_destroy(&thread_lock); - - for (i = 0; i < nthreads; i++) { -- unsigned long t = worker[i].ops/runtime.tv_sec; -+ unsigned long t = worker[i].ops / bench__runtime.tv_sec; - - update_stats(&throughput_stats, t); - if (!silent) --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-cs-etm-Move-definition-of-traceid_list-global-v.patch b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-cs-etm-Move-definition-of-traceid_list-global-v.patch deleted file mode 100644 index 28873cdd4..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-cs-etm-Move-definition-of-traceid_list-global-v.patch +++ /dev/null @@ -1,70 +0,0 @@ -From bc79abf4afea97d5ce682aa2bd1095fb74400916 Mon Sep 17 00:00:00 2001 -From: Leo Yan <leo.yan@linaro.org> -Date: Tue, 5 May 2020 21:36:42 +0800 -Subject: [PATCH] perf cs-etm: Move definition of 'traceid_list' global - variable from header file - -commit 168200b6d6ea0cb5765943ec5da5b8149701f36a upstream. - -The variable 'traceid_list' is defined in the header file cs-etm.h, -if multiple C files include cs-etm.h the compiler might complaint for -multiple definition of 'traceid_list'. - -To fix multiple definition error, move the definition of 'traceid_list' -into cs-etm.c. - -Fixes: cd8bfd8c973e ("perf tools: Add processing of coresight metadata") -Reported-by: Thomas Backlund <tmb@mageia.org> -Signed-off-by: Leo Yan <leo.yan@linaro.org> -Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> -Reviewed-by: Mike Leach <mike.leach@linaro.org> -Tested-by: Mike Leach <mike.leach@linaro.org> -Tested-by: Thomas Backlund <tmb@mageia.org> -Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> -Cc: Jiri Olsa <jolsa@redhat.com> -Cc: Mark Rutland <mark.rutland@arm.com> -Cc: Namhyung Kim <namhyung@kernel.org> -Cc: Peter Zijlstra <peterz@infradead.org> -Cc: Suzuki Poulouse <suzuki.poulose@arm.com> -Cc: Tor Jeremiassen <tor@ti.com> -Cc: linux-arm-kernel@lists.infradead.org -Link: http://lore.kernel.org/lkml/20200505133642.4756-1-leo.yan@linaro.org -Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> -Cc: Paul Barker <pbarker@konsulko.com> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - tools/perf/util/cs-etm.c | 3 +++ - tools/perf/util/cs-etm.h | 3 --- - 2 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c -index 451eee2..f5a9cb4 100644 ---- a/tools/perf/util/cs-etm.c -+++ b/tools/perf/util/cs-etm.c -@@ -94,6 +94,9 @@ struct cs_etm_queue { - struct cs_etm_traceid_queue **traceid_queues; - }; - -+/* RB tree for quick conversion between traceID and metadata pointers */ -+static struct intlist *traceid_list; -+ - static int cs_etm__update_queues(struct cs_etm_auxtrace *etm); - static int cs_etm__process_queues(struct cs_etm_auxtrace *etm); - static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm, -diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h -index 650ecc2..4ad925d 100644 ---- a/tools/perf/util/cs-etm.h -+++ b/tools/perf/util/cs-etm.h -@@ -114,9 +114,6 @@ enum cs_etm_isa { - CS_ETM_ISA_T32, - }; - --/* RB tree for quick conversion between traceID and metadata pointers */ --struct intlist *traceid_list; -- - struct cs_etm_queue; - - struct cs_etm_packet { --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-tests-bp_account-Make-global-variable-static.patch b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-tests-bp_account-Make-global-variable-static.patch deleted file mode 100644 index 4239f0855..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-perf-tests-bp_account-Make-global-variable-static.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 73d2d6b421dfdc66b4615452a94efcece27a3c21 Mon Sep 17 00:00:00 2001 -From: Arnaldo Carvalho de Melo <acme@redhat.com> -Date: Mon, 2 Mar 2020 11:13:19 -0300 -Subject: [PATCH] perf tests bp_account: Make global variable static - -commit cff20b3151ccab690715cb6cf0f5da5cccb32adf upstream. - -To fix the build with newer gccs, that without this patch exit with: - - LD /tmp/build/perf/tests/perf-in.o - ld: /tmp/build/perf/tests/bp_account.o:/git/perf/tools/perf/tests/bp_account.c:22: multiple definition of `the_var'; /tmp/build/perf/tests/bp_signal.o:/git/perf/tools/perf/tests/bp_signal.c:38: first defined here - make[4]: *** [/git/perf/tools/build/Makefile.build:145: /tmp/build/perf/tests/perf-in.o] Error 1 - -First noticed in fedora:rawhide/32 with: - - [perfbuilder@a5ff49d6e6e4 ~]$ gcc --version - gcc (GCC) 10.0.1 20200216 (Red Hat 10.0.1-0.8) - -Reported-by: Jiri Olsa <jolsa@kernel.org> -Cc: Adrian Hunter <adrian.hunter@intel.com> -Cc: Namhyung Kim <namhyung@kernel.org> -Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> -Cc: Ben Hutchings <ben@decadent.org.uk> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - tools/perf/tests/bp_account.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/perf/tests/bp_account.c b/tools/perf/tests/bp_account.c -index 016bba2..55a9de3 100644 ---- a/tools/perf/tests/bp_account.c -+++ b/tools/perf/tests/bp_account.c -@@ -23,7 +23,7 @@ - #include "../perf-sys.h" - #include "cloexec.h" - --volatile long the_var; -+static volatile long the_var; - - static noinline int test_function(void) - { --- -2.7.4 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch deleted file mode 100644 index d5b96c2d1..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e33a814e772cdc36436c8c188d8c42d019fda639 Mon Sep 17 00:00:00 2001 -From: Dirk Mueller <dmueller@suse.com> -Date: Tue, 14 Jan 2020 18:53:41 +0100 -Subject: [PATCH] scripts/dtc: Remove redundant YYLOC global declaration - -gcc 10 will default to -fno-common, which causes this error at link -time: - - (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here - -This is because both dtc-lexer as well as dtc-parser define the same -global symbol yyloc. Before with -fcommon those were merged into one -defintion. The proper solution would be to to mark this as "extern", -however that leads to: - - dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls] - 26 | extern YYLTYPE yylloc; - | ^~~~~~ -In file included from dtc-lexer.l:24: -dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here - 127 | extern YYLTYPE yylloc; - | ^~~~~~ -cc1: all warnings being treated as errors - -which means the declaration is completely redundant and can just be -dropped. - -Signed-off-by: Dirk Mueller <dmueller@suse.com> -Signed-off-by: David Gibson <david@gibson.dropbear.id.au> -[robh: cherry-pick from upstream] -Cc: stable@vger.kernel.org -Signed-off-by: Rob Herring <robh@kernel.org> ---- - scripts/dtc/dtc-lexer.l | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l -index 5c6c3fd557d7..b3b7270300de 100644 ---- a/scripts/dtc/dtc-lexer.l -+++ b/scripts/dtc/dtc-lexer.l -@@ -23,7 +23,6 @@ LINECOMMENT "//".*\n - #include "srcpos.h" - #include "dtc-parser.tab.h" - --YYLTYPE yylloc; - extern bool treesource_error; - - /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ --- -2.29.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/perf-fix-build-with-binutils.patch b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/perf-fix-build-with-binutils.patch deleted file mode 100755 index 1470a5d7c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx/perf-fix-build-with-binutils.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 0ada120c883d4f1f6aafd01cf0fbb10d8bbba015 Mon Sep 17 00:00:00 2001 -From: Changbin Du <changbin.du@gmail.com> -Date: Tue, 28 Jan 2020 23:29:38 +0800 -Subject: [PATCH] perf: Make perf able to build with latest libbfd - -libbfd has changed the bfd_section_* macros to inline functions -bfd_section_<field> since 2019-09-18. See below two commits: - o http://www.sourceware.org/ml/gdb-cvs/2019-09/msg00064.html - o https://www.sourceware.org/ml/gdb-cvs/2019-09/msg00072.html - -This fix make perf able to build with both old and new libbfd. - -Signed-off-by: Changbin Du <changbin.du@gmail.com> -Acked-by: Jiri Olsa <jolsa@redhat.com> -Cc: Peter Zijlstra <peterz@infradead.org> -Link: http://lore.kernel.org/lkml/20200128152938.31413-1-changbin.du@gmail.com -Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> - -Upstream-Status: Backport [https://github.com/torvalds/linux/commit/0ada120c883d4f1f6aafd01cf0fbb10d8bbba015] -Signed-off-by: Anuj Mittal <anuj.mittal@intel.com> ---- - tools/perf/util/srcline.c | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c -index 6ccf6f6d09df9..5b7d6c16d33fe 100644 ---- a/tools/perf/util/srcline.c -+++ b/tools/perf/util/srcline.c -@@ -193,16 +193,30 @@ static void find_address_in_section(bfd *abfd, asection *section, void *data) - bfd_vma pc, vma; - bfd_size_type size; - struct a2l_data *a2l = data; -+ flagword flags; - - if (a2l->found) - return; - -- if ((bfd_get_section_flags(abfd, section) & SEC_ALLOC) == 0) -+#ifdef bfd_get_section_flags -+ flags = bfd_get_section_flags(abfd, section); -+#else -+ flags = bfd_section_flags(section); -+#endif -+ if ((flags & SEC_ALLOC) == 0) - return; - - pc = a2l->addr; -+#ifdef bfd_get_section_vma - vma = bfd_get_section_vma(abfd, section); -+#else -+ vma = bfd_section_vma(section); -+#endif -+#ifdef bfd_get_section_size - size = bfd_get_section_size(section); -+#else -+ size = bfd_section_size(section); -+#endif - - if (pc < vma || pc >= vma + size) - return; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb deleted file mode 100644 index 44fa42de1..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb +++ /dev/null @@ -1,15 +0,0 @@ -LINUX_VERSION = "5.4" -SRCREV ?= "62ea514294a0c9a80455e51f1f4de36e66e8c546" - -include linux-xlnx.inc - -FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" -SRC_URI_append = " \ - file://perf-fix-build-with-binutils.patch \ - file://0001-perf-bench-Share-some-global-variables-to-fix-build-.patch \ - file://0001-perf-tests-bp_account-Make-global-variable-static.patch \ - file://0001-perf-cs-etm-Move-definition-of-traceid_list-global-v.patch \ - file://0001-libtraceevent-Fix-build-with-binutils-2.35.patch \ - file://0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch \ -" - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-dev.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-dev.bbappend deleted file mode 100644 index 05c399514..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-dev.bbappend +++ /dev/null @@ -1 +0,0 @@ -require linux-yocto-xilinx.inc diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-tiny_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-tiny_%.bbappend deleted file mode 100644 index 05c399514..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-tiny_%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require linux-yocto-xilinx.inc diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-xilinx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-xilinx.inc deleted file mode 100644 index 3f3efa95c..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-xilinx.inc +++ /dev/null @@ -1,21 +0,0 @@ -require linux-microblaze.inc - -# Zynq default generic KMACHINE -COMPATIBLE_MACHINE_zynq = "zynq" -KMACHINE_zynq = "zynq" - -# ZynqMP default generic KMACHINE -COMPATIBLE_MACHINE_zynqmp = "zynqmp" -KMACHINE_zynqmp = "zynqmp" - -# MicroBlaze KMACHINEs -KMACHINE_ml605-qemu-microblazeel = "qemumicroblazeel" -KMACHINE_s3adsp1800-qemu-microblazeeb = "qemumicroblazeeb" - -# MicroBlaze default generic KMACHINE -KMACHINE_microblaze = "microblaze" -COMPATIBLE_MACHINE_microblaze = "microblaze" - -# Default kernel config fragements for specific machines -KERNEL_FEATURES_append_kc705-microblazeel = " bsp/xilinx/kc705-microblazeel-features/kc705-microblazeel-features.scc" - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto_%.bbappend deleted file mode 100644 index 05c399514..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto_%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require linux-yocto-xilinx.inc diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/lopper/lopper.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/lopper/lopper.bb deleted file mode 100644 index ea3a9a34d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/lopper/lopper.bb +++ /dev/null @@ -1,42 +0,0 @@ -SUMMARY = "Device tree lopper" -DESCRIPTION = "Tool to subset a system device tree" -SECTION = "bootloader" -LICENSE = "BSD-3-Clause" -DEPENDS += "python3-dtc" - -RDEPENDS_${PN} += "python3-core python3-dtc" - -SRC_URI = "git://github.com/devicetree-org/lopper.git" - -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=8e5f5f691f01c9fdfa7a7f2d535be619" - -SRCREV = "f4389167a200c5d41ee276ff9ad67d01ef6f0aec" - -S = "${WORKDIR}/git" - -do_configure() { - : -} - -do_compile() { - sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' lopper.py - sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' lopper_sanity.py -} - -do_install() { - datadirrelpath=${@os.path.relpath(d.getVar('datadir'), d.getVar('bindir'))} - - mkdir -p ${D}/${bindir} - mkdir -p ${D}/${datadir}/lopper - - cp -r ${S}/README* ${D}/${datadir}/lopper/. - cp -r ${S}/assists* ${D}/${datadir}/lopper/. - cp -r ${S}/lop* ${D}/${datadir}/lopper/. - cp -r ${S}/LICENSE* ${D}/${datadir}/lopper/. - cp -r ${S}/device-tree* ${D}/${datadir}/lopper/. - cp -r ${S}/.gitignore ${D}/${datadir}/lopper/. - - ln -s ${datadirrelpath}/lopper/lopper.py ${D}/${bindir}/. -} - -BBCLASSEXTEND = "native nativesdk" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_%.bbappend deleted file mode 100644 index febf1636d..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_%.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -# OpenGL comes from libmali on ev/eg, when egl is enabled -DEPENDS_MALI_XLNX = "${@bb.utils.contains('PACKAGECONFIG', 'egl', 'libmali-xlnx', '', d)}" -PKG_ARCH_XLNX = "${@bb.utils.contains('PACKAGECONFIG', 'egl', '${SOC_VARIANT_ARCH}', '${TUNE_PKGARCH}', d)}" - -DEPENDS_append_zynqmpev = " ${DEPENDS_MALI_XLNX}" -DEPENDS_append_zynqmpeg = " ${DEPENDS_MALI_XLNX}" - -PACKAGE_ARCH_zynqmpev = "${PKG_ARCH_XLNX}" -PACKAGE_ARCH_zynqmpeg = "${PKG_ARCH_XLNX}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb deleted file mode 100644 index 817aa3806..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb +++ /dev/null @@ -1,30 +0,0 @@ -SUMMARY = "Linux kernel module for Video Code Unit" -DESCRIPTION = "Out-of-tree VCU decoder, encoder and common kernel modules provider for MPSoC EV devices" -SECTION = "kernel/modules" -LICENSE = "GPLv2" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -S = "${WORKDIR}/git" - -BRANCH ?= "release-2020.2" -REPO ?= "git://github.com/xilinx/vcu-modules.git;protocol=https" -SRCREV ?= "844d4c4292e08ad8c3f22ac78e9a937395c1db4b" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -inherit module - -EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" - -RDEPENDS_${PN} = "vcu-firmware" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -KERNEL_MODULE_AUTOLOAD += "dmaproxy" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb deleted file mode 100644 index b52bdf042..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb +++ /dev/null @@ -1,50 +0,0 @@ -SUMMARY = "OpenMAX Integration layer for VCU" -DESCRIPTION = "OMX IL Libraries,test applications and headers for VCU" -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -BRANCH ?= "release-2020.2" -REPO ?= "git://github.com/xilinx/vcu-omx-il.git;protocol=https" -SRCREV ?= "4e9daf282a12ecba19fe12f296a31315f6a6bd2d" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -S = "${WORKDIR}/git" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -DEPENDS = "libvcu-xlnx" -RDEPENDS_${PN} = "kernel-module-vcu libvcu-xlnx" - -EXTERNAL_INCLUDE="${STAGING_INCDIR}/vcu-ctrl-sw/include" - -EXTRA_OEMAKE = " \ - CC='${CC}' CXX='${CXX} ${CXXFLAGS}' \ - EXTERNAL_INCLUDE='${EXTERNAL_INCLUDE}' \ - " - -do_install() { - install -d ${D}${libdir} - install -d ${D}${includedir}/vcu-omx-il - - install -m 0644 ${S}/omx_header/*.h ${D}${includedir}/vcu-omx-il - - install -Dm 0755 ${S}/bin/omx_decoder ${D}/${bindir}/omx_decoder - install -Dm 0755 ${S}/bin/omx_encoder ${D}/${bindir}/omx_encoder - - oe_libinstall -C ${S}/bin/ -so libOMX.allegro.core ${D}/${libdir}/ - oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_decoder ${D}/${libdir}/ - oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_encoder ${D}/${libdir}/ -} - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. - -EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb deleted file mode 100644 index 10b9a4d85..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb +++ /dev/null @@ -1,42 +0,0 @@ -SUMMARY = "Control Software for VCU" -DESCRIPTION = "Control software libraries, test applications and headers provider for VCU" -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -BRANCH ?= "release-2020.2" -REPO ?= "git://github.com/xilinx/vcu-ctrl-sw.git;protocol=https" -SRCREV ?= "b82de3783fe66ee72f28b51313e8b42827d3f202" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -S = "${WORKDIR}/git" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -RDEPENDS_${PN} = "kernel-module-vcu" - -EXTRA_OEMAKE = "CC='${CC}' CXX='${CXX} ${CXXFLAGS}'" - -do_install() { - install -d ${D}${libdir} - install -d ${D}${includedir}/vcu-ctrl-sw/include - - install -Dm 0755 ${S}/bin/ctrlsw_encoder ${D}/${bindir}/ctrlsw_encoder - install -Dm 0755 ${S}/bin/ctrlsw_decoder ${D}/${bindir}/ctrlsw_decoder - - oe_runmake install_headers INSTALL_HDR_PATH=${D}${includedir}/vcu-ctrl-sw/include - oe_libinstall -C ${S}/bin/ -so liballegro_decode ${D}/${libdir}/ - oe_libinstall -C ${S}/bin/ -so liballegro_encode ${D}/${libdir}/ -} - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. - -EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb deleted file mode 100644 index 87c0475ac..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb +++ /dev/null @@ -1,39 +0,0 @@ -SUMMARY = "Firmware for VCU" -DESCRIPTION = "Firmware binaries provider for VCU" -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -S = "${WORKDIR}/git" - -BRANCH ?= "release-2020.2" -REPO ?= "git://github.com/xilinx/vcu-firmware.git;protocol=https" -SRCREV ?= "4e0bb53eba9ad84bf113a2efc12a4539e980f2c9" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE_zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -do_install() { - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d_b.fw ${D}/lib/firmware/al5d_b.fw - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d.fw ${D}/lib/firmware/al5d.fw - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e_b.fw ${D}/lib/firmware/al5e_b.fw - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e.fw ${D}/lib/firmware/al5e.fw -} - -# Inhibit warnings about files being stripped -INHIBIT_PACKAGE_DEBUG_SPLIT = "1" -INHIBIT_PACKAGE_STRIP = "1" -FILES_${PN} = "/lib/firmware/*" - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. -EXCLUDE_FROM_WORLD = "1" - -INSANE_SKIP_${PN} = "ldflags" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-support/libgpg-error/files/lock-obj-pub.microblazeel-unknown-linux-gnu.h b/meta-xilinx/meta-xilinx-bsp/recipes-support/libgpg-error/files/lock-obj-pub.microblazeel-unknown-linux-gnu.h deleted file mode 100644 index 9843f4d91..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-support/libgpg-error/files/lock-obj-pub.microblazeel-unknown-linux-gnu.h +++ /dev/null @@ -1,23 +0,0 @@ -## lock-obj-pub.microblazeel-xilinx-linux-gnu.h -## File created by gen-posix-lock-obj - DO NOT EDIT -## To be included by mkheader into gpg-error.h - -typedef struct -{ - long _vers; - union { - volatile char _priv[24]; - long _x_align; - long *_xp_align; - } u; -} gpgrt_lock_t; - -#define GPGRT_LOCK_INITIALIZER {1,{{0,0,0,0,0,0,0,0, \ - 0,0,0,0,0,0,0,0, \ - 0,0,0,0,0,0,0,0}}} -## -## Local Variables: -## mode: c -## buffer-read-only: t -## End: -## diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-support/libgpg-error/libgpg-error_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-support/libgpg-error/libgpg-error_%.bbappend deleted file mode 100644 index 7a4d11429..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-support/libgpg-error/libgpg-error_%.bbappend +++ /dev/null @@ -1,8 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" - -SRC_URI_append_microblaze = " file://lock-obj-pub.microblazeel-unknown-linux-gnu.h" - -do_configure_append_microblaze () { - cp ${WORKDIR}/lock-obj-pub.microblazeel-unknown-linux-gnu.h ${S}/src/syscfg/ -} - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-headers/opencl-headers_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-headers/opencl-headers_%.bbappend deleted file mode 100644 index afe3e9cda..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-headers/opencl-headers_%.bbappend +++ /dev/null @@ -1 +0,0 @@ -ALLOW_EMPTY_${PN} = "1" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb deleted file mode 100644 index 97a7a4012..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb +++ /dev/null @@ -1,56 +0,0 @@ -SUMMARY = "Xilinx Runtime(XRT) libraries" -DESCRIPTION = "Xilinx Runtime User Space Libraries and headers" - -LICENSE = "GPLv2 & Apache-2.0" -LIC_FILES_CHKSUM = "file://../LICENSE;md5=da5408f748bce8a9851dac18e66f4bcf \ - file://runtime_src/core/edge/drm/zocl/LICENSE;md5=7d040f51aae6ac6208de74e88a3795f8 \ - file://runtime_src/core/pcie/driver/linux/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ - file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ - file://runtime_src/core/pcie/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 \ - file://runtime_src/core/edge/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 " - -BRANCH ?= "2020.2" -REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https" -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -PV = "202020.2.8.0" -SRCREV ?= "f19a872233fbfe2eb933f25fa3d9a780ced774e5" - -S = "${WORKDIR}/git/src" - -inherit cmake - -BBCLASSEXTEND = "native nativesdk" - -# util-linux is for libuuid-dev. -DEPENDS = "libdrm opencl-headers ocl-icd opencl-clhpp boost util-linux git-replacement-native protobuf-native protobuf" -RDEPENDS_${PN} = "bash ocl-icd boost-system boost-filesystem" - -EXTRA_OECMAKE += " \ - -DCMAKE_BUILD_TYPE=Release \ - -DCMAKE_EXPORT_COMPILE_COMANDS=ON \ - " - -PACKAGE_ARCH_versal-ai-core = "${SOC_VARIANT_ARCH}" -EXTRA_OECMAKE_append_versal-ai-core += "-DXRT_AIE_BUILD=true" -TARGET_CXXFLAGS_append_versal-ai-core += "-DXRT_ENABLE_AIE" -DEPENDS_append_versal-ai-core += " libmetal libxaiengine" -RDEPENDS_${PN}_append_versal-ai-core += " libxaiengine" - -FILES_SOLIBSDEV = "" -FILES_${PN} += "\ - ${libdir}/lib*.so \ - ${libdir}/lib*.so.* \ - /lib/*.so* " -INSANE_SKIP_${PN} += "dev-so" - -pkg_postinst_ontarget_${PN}() { - #!/bin/sh - if [ ! -e /etc/OpenCL/vendors/xilinx.icd ]; then - echo "INFO: Creating ICD entry for Xilinx Platform" - mkdir -p /etc/OpenCL/vendors - echo "libxilinxopencl.so" > /etc/OpenCL/vendors/xilinx.icd - chmod -R 755 /etc/OpenCL - fi -} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb deleted file mode 100644 index 1479e2010..000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb +++ /dev/null @@ -1,25 +0,0 @@ -SUMMARY = "Xilinx Runtime(XRT) driver module" -DESCRIPTION = "Xilinx Runtime driver module provides memory management and compute unit schedule" - -LICENSE = "GPLv2 & Apache-2.0" -LIC_FILES_CHKSUM = "file://LICENSE;md5=7d040f51aae6ac6208de74e88a3795f8" - -BRANCH ?= "2020.2" -REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https" -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -PV = "202020.2.8.0" -SRCREV ?= "f19a872233fbfe2eb933f25fa3d9a780ced774e5" - -S = "${WORKDIR}/git/src/runtime_src/core/edge/drm/zocl" - -inherit module - -pkg_postinst_ontarget_${PN}() { - #!/bin/sh - echo "Unloading old XRT Linux kernel modules" - ( rmmod zocl || true ) > /dev/null 2>&1 - echo "Loading new XRT Linux kernel modules" - modprobe zocl -} |