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Remove Mt.Jade u-boot patches as we have other approach for them:
1. Patch 0001 is to set FANs to maximum speed in u-boot to avoid
hardware damage in case of Host ON with high CPU usage. This can be
resolved by setting FAN to maximum speed when the FAN service stop.
2. Patch 0002 is to enable I2C4 device access. With commit
0b32c1b40@linux, I2C4 enable is set via gpio-hog
3. Patch 0003 will be resolved later by supporting Aspeed watchdog with
boot status.
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: I247f99ebac7c3ca10a2dc77f1909f5c0c519401d
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Enable phosphor-aspeed-spi-master-mode.inc and remove the u-boot
patch that used for this feature.
Also remove GPIO setting patches which the setting already implemented
in the platform init package.
Tested: on Mt.Jade platform with OCP plugged
1. Bind/unbind Host SPI-NOR and ensure no problem
2. Turn off Host, reboot BMC and check if Host SPI-NOR is probe
successfully.
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: Ie85166edca93b882868e1373696fbf664bee2ee4
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Mt.Jade DVT hardware requires some GPIO setting so that the board can
work well. This commit updates platform init function in u-boot to set
required GPIO pins.
Tested:
1. Verify below GPIOs set as input in Linux:
- S0_I2C9_ALERT_L (GPIOM4)
- S1_I2C9_ALERT_L (GPIOM5)
- GPIO_BMC_VGA_FRONT_PRES_L (GPIOQ7)
- GPIO_BMC_EXT_HIGHTEMP_L
- GPIO_S0_VRHOT_L
- GPIO_S1_VRHOT_L
- GPIO_BMC_PCA9554_INT_L
2. verify below GPIOs set as output high in Linux
- GPIO_BMC_I2C6_RESET_L
- GPIO_BMC_JTAG_SRST_L
- GPIO_BMC_VR_PMBUS_SEL_L
- BMC_GPIOR2_EXT_HIGHTEMP_L
- BMC_VGA_SEL
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Change-Id: I8b76387ec05c546c34c89f6f5881da3b7955a805
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The Mt.Jade board designs pin strap, which is shared with an OCP pin.
This causes the pin strap to have the wrong value if the OCP adapter
is plugged and the system is off which consequently disables the SPI
master mode. This makes OpenBMC fail to probe the Host SPI Flash.
Change to set SPI master mode enabled by default, not base on the
pin strap value, so Host SPI NOR can always be probed.
Tested:
1. Plug Mellanox OCP card into the OCP1 header.
2. Do AC power board and check if SPI Flash driver
can probe without error like
"aspeed-smc 1e630000.spi: Error applying setting, reverse things back"
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Change-Id: Ie36557d8e1580f8a6b59b24ac47557d59af653c5
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This is an initial support for the parallel GPIO pins directly connected
to the AHB on the Aspeed 2400/2500.
This brings the functions and a shell command to manipulate the GPIO
state. The GPIO value reading and writing work in non interrupt mode
only.
This is back ported from the patch file from
meta-yadro/meta-nicole/recipes-bsp/u-boot/files/0003-aspeed-add-gpio-support.patch
to support GPIO configuration
Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
Signed-off-by: Thang Q. Nguyen <thangqn@amperecomputing.com>
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Change-Id: I2d97c0fbb9f80bd6c262f03302775936f732b1f1
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Backport a patch file from meta-yadro/meta-nicole/recipes-bsp/u-boot/ to
add the Aspeed reset reason to bootargs so kernel so kernel application
can query it.
Tested: /proc/cmdline must contain:
- resetreason=power after A/C power
- resetreason=watchdog after bmc reboot
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: I7e75cccfa0fecfa9a66572e02de0f1c8c1d519a1
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Configure SCU8C - Multi-function pin control 4 to disable internal pull
down resistors for GPIOJ, GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as
external resistors are already installed.
Tested: scan I2C4 and check devices on the bus are detected
Signed-off-by: Thinh Pham <thinh.pham@amperecomputing.com>
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: I5a4b682310b5243830bd9c7a66889b0a52c4770c
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When BMC is reseting, FANs do not run at all. This might cause heating
issue in case the Host CPU is in high load.
To protect the hardware, it is safe to set FANs run at full speed when
BMC is booting. After it boots complete, phosphor-fan service will take
control on FANs to make them work at the right speed.
This commit adds patch to configure all PWM function pins to input GPIO mode
to make FANs run at full speed.
Tested:
1. Boot BMC to Linux.
2. Turn on Host by "ipmitool chassis power on" command
3. Reboot BMC and check if FAN speed is maximum at u-boot.
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: I38f1433a576a1700938347dc89eddacf3fb3bf60
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