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From 647cc2538ed6b64054c742b4668386fda9394221 Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Date: Tue, 8 Jan 2019 13:33:15 -0800
Subject: [PATCH] Enable PCIe L1 support
This commit enables PCIe L1 support using magic registers.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
---
arch/arm/mach-aspeed/platform_g5.S | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S
index 66427b6..b404353 100644
--- a/arch/arm/mach-aspeed/platform_g5.S
+++ b/arch/arm/mach-aspeed/platform_g5.S
@@ -2432,6 +2432,18 @@ spi_cbr_end:
bic r1, r1, #0x00400000
str r1, [r0]
+ ldr r0, =0x1e6ed07c @ Enable PCIe L1 support
+ ldr r1, =0xa8
+ str r1, [r0]
+
+ ldr r0, =0x1e6ed068
+ ldr r1, =0xc81f0a
+ str r1, [r0]
+
+ ldr r0, =0x1e6ed07c
+ mov r1, #0
+ str r1, [r0]
+
/******************************************************************************
Configure MAC timing
******************************************************************************/
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