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From 94cecaf3d944ee0b2a24b5628131db92de7cbaf3 Mon Sep 17 00:00:00 2001
From: Vikram Bodireddy <vikram.bodireddy@intel.com>
Date: Wed, 18 Mar 2020 21:47:11 +0530
Subject: [PATCH] PFR- Skip counting WDT2 event when EXTRST# is set
PFR CPLD drives EXTRST# of BMC to reset it during
firmware update and during recovery. On ast2500 the
EXTRST# is also setting WDT2/3 flags which is counted
as boot failures by u-boot and aborts the boot if
boot failures are more than 3. This change will skip
counting WDT2 flag if EXTRST# is also set in SCU3C.
Tested: Verified BMC updates 4 times and checked that
the boot is not aborted at u-boot.
Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
---
board/aspeed/ast-g5/ast-g5-intel.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c
index 511bf32f94ac..66423d9b55a8 100644
--- a/board/aspeed/ast-g5/ast-g5-intel.c
+++ b/board/aspeed/ast-g5/ast-g5-intel.c
@@ -137,6 +137,7 @@ static const GPIOValue gpio_table[] = {
#define HOST_SERIAL_B_HIGH_SPEED (1 << 1)
#define WATCHDOG_RESET_BIT BIT(3)
+#define EXTRST_RESET_BIT BIT(1)
#define POWERON_RESET_BIT BIT(0)
#define BOOT_FAILURE_LIMIT 0x3
@@ -551,7 +552,8 @@ void ast_g5_intel_late_init(void)
boot_failures = get_boot_failures();
- if (reset_reason & WATCHDOG_RESET_BIT)
+ if ((reset_reason & WATCHDOG_RESET_BIT) &&
+ !(reset_reason & EXTRST_RESET_BIT))
set_boot_failures(boot_failures + 1);
else
set_boot_failures(0);
--
2.17.1
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