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From 700d71d2c9ef669583acb6900a913620bbb68ce0 Mon Sep 17 00:00:00 2001
From: sureshv1 <suresh.vijayakumar@intel.com>
Date: Mon, 20 Sep 2021 11:27:46 +0530
Subject: [PATCH] Disable BMC MMIO Decode on VGA SCU register bit
This patch is required to avoid un-necessary logging of
redfish log(P2A Bridge Enabled) as the default value of
SCUC20 has this bit set causing the default/init value
to be taken into consideration and logging the event.
Tested:
Flashed the image and performed AC Power cycle multiple
times also to check whether any critical events related
to P2A Bridge enabled log, this redfish log is not being
logged after this changes.
Change-Id: If24fbea338ce17e3b4f1ba93b4d11c7843ddb952
Signed-off-by: sureshv1 <suresh.vijayakumar@intel.com>
---
board/aspeed/ast2600_intel/intel.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
index 1791045ee8..103bf538b5 100644
--- a/board/aspeed/ast2600_intel/intel.c
+++ b/board/aspeed/ast2600_intel/intel.c
@@ -478,6 +478,23 @@ static void pwm_init(void)
}
}
+/*
+ * Description: Disable BMC MMIO Decode on VGA
+ * which is not being used.
+ */
+void disable_bmc_mmio_decode_vga()
+{
+#define AST_SCU_BASE 0x1E6E2000
+#define AST_PCI_CONFIG_REG 0xC20
+
+ u32 pcie_config_val = readl(AST_SCU_BASE + AST_PCI_CONFIG_REG);
+
+ if (pcie_config_val & BIT(1)) {
+ writel(pcie_config_val & ~BIT(1),
+ AST_SCU_BASE + AST_PCI_CONFIG_REG);
+ }
+}
+
int board_early_init_f(void)
{
/* This is called before relocation; beware! */
@@ -680,6 +697,8 @@ int board_late_init(void)
pwm_init();
+ disable_bmc_mmio_decode_vga();
+
/* Add reset reason to bootargs */
snprintf(value, sizeof(value), "0x%x", gd->reset_reason);
update_bootargs_cmd("resetreason", value);
--
2.17.1
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