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From 4e5ae852c4ab46c684d71d04c30dbfd01fbccae0 Mon Sep 17 00:00:00 2001
From: Steven Lee <steven_lee@aspeedtech.com>
Date: Tue, 14 Dec 2021 12:02:38 +0800
Subject: [PATCH] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
(cherry picked from commit e5a7431f5a2d6dcff7d516ee9d178a3254b17b87)
Signed-off-by: Sujoy Ray <sujoy.ray@intel.com>
---
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 931d5c38d7de..454cefbeecf0 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, ®, 32)
- generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
+ generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
}
chained_irq_exit(ic, desc);
--
2.17.1
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