1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
From 9fc2343bac42db2432f96db1bbfc6979822a7154 Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Date: Thu, 26 Mar 2020 14:20:19 -0700
Subject: [PATCH] Refine clock settings
This commit refines clock settings with cherry picking the latest
code from Aspeed SDK v00.05.05
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
---
drivers/clk/clk-ast2600.c | 60 +++++++++++++++++++++++++++++++++++++++++------
1 file changed, 53 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index fb6b11440b97..e07326544fdc 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -31,6 +31,24 @@
#define ASPEED_G6_CLK_SELECTION1 0x300
#define ASPEED_G6_CLK_SELECTION2 0x304
#define ASPEED_G6_CLK_SELECTION4 0x310
+#define ASPEED_G6_CLK_SELECTION5 0x314
+
+#define ASPEED_G6_MAC12_CLK_CTRL0 0x340
+#define ASPEED_G6_MAC12_CLK_CTRL1 0x348
+#define ASPEED_G6_MAC12_CLK_CTRL2 0x34C
+
+#define ASPEED_G6_MAC34_CLK_CTRL0 0x350
+#define ASPEED_G6_MAC34_CLK_CTRL1 0x358
+#define ASPEED_G6_MAC34_CLK_CTRL2 0x35C
+
+#define ASPEED_G6_MAC34_DRIVING_CTRL 0x458
+
+#define ASPEED_G6_DEF_MAC12_DELAY_1G 0x0041b410
+#define ASPEED_G6_DEF_MAC12_DELAY_100M 0x00417410
+#define ASPEED_G6_DEF_MAC12_DELAY_10M 0x00417410
+#define ASPEED_G6_DEF_MAC34_DELAY_1G 0x00104208
+#define ASPEED_G6_DEF_MAC34_DELAY_100M 0x00104208
+#define ASPEED_G6_DEF_MAC34_DELAY_10M 0x00104208
#define ASPEED_HPLL_PARAM 0x200
#define ASPEED_APLL_PARAM 0x210
@@ -40,9 +58,6 @@
#define ASPEED_G6_STRAP1 0x500
-#define ASPEED_MAC12_CLK_DLY 0x340
-#define ASPEED_MAC34_CLK_DLY 0x350
-
#define ASPEED_G6_GEN_UART_REF 0x338
#define UART_192MHZ_R_N_VALUE 0x3c38e
@@ -515,7 +530,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
/* RMII1 50MHz (RCLK) output enable */
hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
- scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
+ scu_g6_base + ASPEED_G6_MAC12_CLK_CTRL0, 29, 0,
&aspeed_g6_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
@@ -523,7 +538,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
/* RMII2 50MHz (RCLK) output enable */
hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
- scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
+ scu_g6_base + ASPEED_G6_MAC12_CLK_CTRL0, 30, 0,
&aspeed_g6_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
@@ -545,7 +560,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
/* RMII3 50MHz (RCLK) output enable */
hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
- scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
+ scu_g6_base + ASPEED_G6_MAC34_CLK_CTRL0, 29, 0,
&aspeed_g6_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
@@ -553,7 +568,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
/* RMII4 50MHz (RCLK) output enable */
hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
- scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
+ scu_g6_base + ASPEED_G6_MAC34_CLK_CTRL0, 30, 0,
&aspeed_g6_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
@@ -770,6 +785,37 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
return;
}
+ /* fixed settings for RGMII/RMII clock generator */
+ /* MAC1/2 RGMII 125MHz = EPLL / 8 */
+ regmap_update_bits(map, ASPEED_G6_CLK_SELECTION2, GENMASK(23, 20),
+ (0x7 << 20));
+
+ /* MAC3/4 RMII 50MHz = HCLK / 4 */
+ regmap_update_bits(map, ASPEED_G6_CLK_SELECTION4, GENMASK(18, 16),
+ (0x3 << 16));
+
+ /*
+ * BIT[31]: MAC1/2 RGMII 125M source = internal PLL
+ * BIT[28]: RGMIICK pad direction = output
+ */
+ regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL0,
+ BIT(31) | BIT(28) | ASPEED_G6_DEF_MAC12_DELAY_1G);
+ regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL1,
+ ASPEED_G6_DEF_MAC12_DELAY_100M);
+ regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL2,
+ ASPEED_G6_DEF_MAC12_DELAY_10M);
+
+ /* MAC3/4 RGMII 125M source = RGMIICK pad */
+ regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL0,
+ ASPEED_G6_DEF_MAC34_DELAY_1G);
+ regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL1,
+ ASPEED_G6_DEF_MAC34_DELAY_100M);
+ regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL2,
+ ASPEED_G6_DEF_MAC34_DELAY_10M);
+
+ /* MAC3/4 default pad driving strength */
+ regmap_write(map, ASPEED_G6_MAC34_DRIVING_CTRL, 0x0000000a);
+
aspeed_g6_cc(map);
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
--
2.7.4
|
