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authorTim Lee <timlee660101@gmail.com>2024-02-19 12:18:10 +0300
committerTim Lee <chli30@nuvoton.com>2024-03-06 04:01:57 +0300
commit26375f62c6786ce3f14ac18db1b24ee3e3062dfd (patch)
tree1136ba0335af8e198b33778cb8b4d4f24819c070
parentfd7b67d3ddbf72c7d94685103f07e03744a9e42e (diff)
downloadopenbmc-26375f62c6786ce3f14ac18db1b24ee3e3062dfd.tar.xz
meta-nuvoton: npcm8xx-bootblock: update to 0.4.1
Changelog: version 0.4.1 - Feb 5th 2024 ============= - Set PCI and GFX core clock to PLL1. version 0.4.0 - Feb 1st 2024 ============= - Bug fix: GMAC frequency always set to 125MHz. - PCI always 125MHZ, RC always 100MHz. - If ECC enabled, force both CPU and MC to be the same frequency. - Add two optional GPIO set after mtest, declared in the IGPS header. Signed-off-by: Tim Lee <timlee660101@gmail.com> Change-Id: I85e66aae974f5dc8bc403bc8c6863cf48061d385
-rw-r--r--meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.3.9.bb3
-rw-r--r--meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.4.1.bb3
2 files changed, 3 insertions, 3 deletions
diff --git a/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.3.9.bb b/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.3.9.bb
deleted file mode 100644
index 45f79463f8..0000000000
--- a/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.3.9.bb
+++ /dev/null
@@ -1,3 +0,0 @@
-SRCREV = "4a12209ba483f511a7bf5090ca5d3872e82299eb"
-
-require npcm8xx-bootblock.inc
diff --git a/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.4.1.bb b/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.4.1.bb
new file mode 100644
index 0000000000..9726d171e8
--- /dev/null
+++ b/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.4.1.bb
@@ -0,0 +1,3 @@
+SRCREV = "a5763b9b6ec8f4f171f9c4a1c50d662e53037497"
+
+require npcm8xx-bootblock.inc