subtree updates

meta-security: b9bc938785..1856a7cf43:
  Armin Kuster (1):
        scap-security-guide: update to 0.1.69+

  Lei Maohui (2):
        paxctl: Fix do_package QA Issue.
        ccs-tools: Fix do_package QA Issue.

  Martin Jansa (1):
        layer.conf: update LAYERSERIES_COMPAT for nanbield

  Yi Zhao (1):
        scap-security-guide: pass the correct cpe/schemas/xsl paths to oscap

meta-arm: 992c07f7c0..bd0953cc60:
  Abdellatif El Khlifi (1):
        arm-bsp/u-boot: corstone1000: detect the kernel size automatically

  Anusmita Dutta Mazumder (5):
        arm-bsp/u-boot: corstone1000: add unique firmware GUID
        arm-bsp/trusted-firmware-m: corstone1000: add unique firmware GUID
        arm-bsp/scp-firmware: Update N1SDP scp-firmware version
        arm-bsp/n1sdp: Enable tests with pseudo trusted application
        CI: Build custom image for N1SDP optee-xtest

  Delane Brandy (1):
        arm-bsp/corstone1000: mmc2-enablement

  Emekcan Aras (2):
        arm-bsp/trusted-firmware-a: corstone1000: Update TF-A v2.9
        arm-bsp/optee-os: corstone1000: Update optee-os v3.22

  Javier Tia (1):
        optee-client: Add path condition to tee-supplicant.service

  Jon Mason (14):
        arm/trusted-firmware-a: update to 2.9.0
        arm-bsp/juno: update kernel to 6.4
        arm/linux-yocto: change defconfig patch for 6.4
        arm/hafnium: update to v2.8
        arm/linux-yocto: update kernel patches
        arm/trusted-services: add SRCREV_FORMAT
        arm-bsp/tc1: update optee
        arm-bsp/fvp-baser-aemv8r64: update u-boot to 2023.01
        arm-bsp/corstone500: upgrade u-boot to the latest
        arm-bsp/corstone500: removal of support
        arm: patch clean-ups
        arm/edk2: update to 202305 version
        arm/sbsa-acs: update to v7.1.2
        arm-bsp/trusted-firmware-a: remove unneeded patches

  Mariam Elshakfy (2):
        arm-bsp/trusted-firmware-a: Update TF-A version for N1SDP
        arm-bsp/n1sdp: Update edk2-firmware version for N1SDP to 202305

  Ross Burton (3):
        kas/: pass through DISPLAY from environment
        Remove explicit SRCPV
        arm-bsp/external-system: set PACKAGE_ARCH as this is machine-specific

meta-raspberrypi: 5e2f79a6fa..6501ec892c:
  Andrei Gherzan (2):
        ci: Add usrmerge to distro features
        docs: Fix documentation theme

  Sangmo Kang (1):
        omxplayer: fix an error caused by new srcrev fetcher API

Change-Id: Ibfc1e039975c1d20358c861af19fc8538125118e
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>

1 files changed, 197 insertions, 0 deletions

diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch
new file mode 100644
index 0000000000..8e14699585
--- /dev/null
+++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch
@@ -0,0 +1,197 @@
+From 6d274379f584a638c1f2b4b8a19014d4baef1d9f Mon Sep 17 00:00:00 2001
+From: sahil <sahil@arm.com>
+Date: Thu, 11 Aug 2022 11:26:29 +0530
+Subject: [PATCH] Platform/ARM/N1Sdp: manually poll QSPI status bit after
+ erase/write
+
+This patch adds a function to poll Nor flash memory's status register
+bit (WIP bit) to wait for an erase/write operation to complete.
+The polling timeout is set to 1 second.
+
+Upstream-Status: Pending
+Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
+Signed-off-by: sahil <sahil@arm.com>
+Change-Id: Ie678b7586671964ae0f8506a0542d73cbddddfe4
+---
+ .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf |  1 +
+ .../Drivers/CadenceQspiDxe/CadenceQspiReg.h   |  6 +-
+ .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c   | 80 ++++++++++++++++++-
+ .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h   |  5 ++
+ 4 files changed, 88 insertions(+), 4 deletions(-)
+
+diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
+index 4f20c3ba..7a39eb2d 100644
+--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
+@@ -39,6 +39,7 @@
+   MemoryAllocationLib
+   NorFlashInfoLib
+   NorFlashPlatformLib
++  TimerLib
+   UefiBootServicesTableLib
+   UefiDriverEntryPoint
+   UefiLib
+diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
+index fe3b327c..1971631d 100644
+--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
+@@ -16,13 +16,15 @@
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS         19
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS    16
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT           0x02
+-#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B         0x03
+-#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B         0x02
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS       24
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE          0x01
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B         0x02
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS       23
+ #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS     20
++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C             0x8
++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS        7
++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS)
++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS)
+ 
+ #define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET          0xA0
+ 
+diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
+index 188c75e2..6832351a 100644
+--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
+@@ -10,6 +10,7 @@
+ #include <Library/MemoryAllocationLib.h>
+ #include <Library/NorFlashInfoLib.h>
+ #include <Library/PcdLib.h>
++#include <Library/TimerLib.h>
+ #include <Library/UefiBootServicesTableLib.h>
+ #include <Library/UefiLib.h>
+ 
+@@ -184,6 +185,74 @@ FreeInstance:
+   return Status;
+ }
+ 
++/**
++  Converts milliseconds into number of ticks of the performance counter.
++
++  @param[in] Milliseconds  Milliseconds to convert into ticks.
++
++  @retval Milliseconds expressed as number of ticks.
++
++**/
++STATIC
++UINT64
++MilliSecondsToTicks (
++  IN UINTN Milliseconds
++  )
++{
++  CONST UINT64  NanoSecondsPerTick = GetTimeInNanoSecond (1);
++
++  return (Milliseconds * 1000000) / NanoSecondsPerTick;
++}
++
++/**
++  Poll Status register for NOR flash erase/write completion.
++
++  @param[in]      Instance           NOR flash Instance.
++
++  @retval         EFI_SUCCESS        Request is executed successfully.
++  @retval         EFI_TIMEOUT        Operation timed out.
++  @retval         EFI_DEVICE_ERROR   Controller operartion failed.
++
++**/
++STATIC
++EFI_STATUS
++NorFlashPollStatusRegister (
++  IN NOR_FLASH_INSTANCE     *Instance
++  )
++{
++  BOOLEAN     SRegDone;
++  UINT32      val;
++
++  val = SPINOR_OP_RDSR << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
++      CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
++      CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(1) |
++      CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C << CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS;
++
++  CONST UINT64  TickOut =
++    GetPerformanceCounter () + MilliSecondsToTicks (SPINOR_SR_WIP_POLL_TIMEOUT_MS);
++
++  do {
++    if (GetPerformanceCounter () > TickOut) {
++      DEBUG ((
++        DEBUG_ERROR,
++        "NorFlashPollStatusRegister: Timeout waiting for erase/write.\n"
++        ));
++      return EFI_TIMEOUT;
++    }
++
++    if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
++      return EFI_DEVICE_ERROR;
++    }
++
++    SRegDone =
++      (MmioRead8 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET)
++      & SPINOR_SR_WIP) == 0;
++
++  } while (!SRegDone);
++
++  return EFI_SUCCESS;
++}
++
+ /**
+   Check whether NOR flash opertions are Locked.
+ 
+@@ -305,12 +374,16 @@ NorFlashEraseSingleBlock (
+ 
+   DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
+                  CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS |
+-                 CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS;
++                 CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(3);
+ 
+   if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) {
+     return EFI_DEVICE_ERROR;
+   }
+ 
++  if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) {
++      return EFI_DEVICE_ERROR;
++  }
++
+   return EFI_SUCCESS;
+ }
+ 
+@@ -383,6 +456,9 @@ NorFlashWriteSingleWord (
+     return EFI_DEVICE_ERROR;
+   }
+   MmioWrite32 (WordAddress, WriteData);
++  if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) {
++    return EFI_DEVICE_ERROR;
++  }
+   return EFI_SUCCESS;
+ }
+ 
+@@ -907,7 +983,7 @@ NorFlashReadID (
+ 
+   val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
+         CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
+-        CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS;
++        CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(3);
+ 
+   if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
+     return EFI_DEVICE_ERROR;
+diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
+index e720937e..eb0afc60 100644
+--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
+@@ -477,8 +477,13 @@ NorFlashReadID (
+   OUT UINT8               JedecId[3]
+   );
+ 
++#define SPINOR_SR_WIP                 BIT0  // Write in progress
++
+ #define SPINOR_OP_WREN                0x06  // Write enable
+ #define SPINOR_OP_BE_4K               0x20  // Erase 4KiB block
+ #define SPINOR_OP_RDID                0x9f  // Read JEDEC ID
++#define SPINOR_OP_RDSR                0x05  // Read status register
++
++#define SPINOR_SR_WIP_POLL_TIMEOUT_MS  1000u // Status Register read timeout
+ 
+ #endif /* NOR_FLASH_DXE_H_ */