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authorTim Lee <timlee660101@gmail.com>2023-06-28 09:56:09 +0300
committerTim Lee <chli30@nuvoton.com>2023-07-04 06:50:47 +0300
commitc3a21f2f8b8a6202e65c91f45b49a5f9069dbeec (patch)
tree7f32af89aba7e42f0e8d6da2cce12ea4a11c8065 /meta-nuvoton
parent794dbf51f793d79ba5ce0a394bc4e2c4cba53be5 (diff)
downloadopenbmc-c3a21f2f8b8a6202e65c91f45b49a5f9069dbeec.tar.xz
meta-nuvoton: npcm8xx-tip-fw: update to 0.6.0.0.4.9
Changelog: TIP FW 0.6.0 L0 0.4.9 L1 ============== * New memory map. TIP_VIRTUAL_FLASH_BASE_ADDR moved to 0x1000000. * Fix NVIC_TrapHandlerCommon: uart reconfig should be after sampling core registers. * Fix DRAM window handling bug, in order to allow loading images to any address in DRAM. * In recovery mode: add an option to go to halt (print "N" at the start). * Add the support for enforcing recovery image to match active at boot time * Add support for ECC 384 + 521 * Add the support of ecc HW with tip_ecc_hw_ncl.c instead of old implementation using mbedtls code * Wake all 4 cores when jump to DRAM (feature was limited to RAM2 only). * Bug fix SFDP dummy byte. Tested: buid pass and boot up successful with correct TIP FW latest version. Signed-off-by: Tim Lee <timlee660101@gmail.com> Change-Id: I0d848f329a7954ca0b65644d368de93296b6e822
Diffstat (limited to 'meta-nuvoton')
-rw-r--r--meta-nuvoton/recipes-bsp/images/npcm8xx-tip-fw_0.6.0.0.4.9.bb (renamed from meta-nuvoton/recipes-bsp/images/npcm8xx-tip-fw_0.5.9.0.4.8.bb)2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-nuvoton/recipes-bsp/images/npcm8xx-tip-fw_0.5.9.0.4.8.bb b/meta-nuvoton/recipes-bsp/images/npcm8xx-tip-fw_0.6.0.0.4.9.bb
index e5615de7a5..e7fadfd35c 100644
--- a/meta-nuvoton/recipes-bsp/images/npcm8xx-tip-fw_0.5.9.0.4.8.bb
+++ b/meta-nuvoton/recipes-bsp/images/npcm8xx-tip-fw_0.6.0.0.4.9.bb
@@ -1,4 +1,4 @@
-SRCREV = "1429f76f2cb4fb073693cbf9e696d9f61d02c509"
+SRCREV = "26d7677ddf1068f697e570f45bae7f51041cb2f1"
OUTPUT_BIN = "output_binaries_${DEVICE_GEN}_${IGPS_MACHINE}"