poky: subtree update:b23aa6b753..ad30a6d470

Armin Kuster (1):
      timezone: update to 2020b

Bruce Ashfield (7):
      linux-yocto/5.4: fix kprobes build warning
      linux-yocto/5.4: update to v5.4.67
      linux-yocto/5.8: update to v5.8.11
      linux-yocto/5.4: update to v5.4.68
      linux-yocto/5.8: update to v5.8.12
      linux-yocto/5.4: update to v5.4.69
      linux-yocto/5.8: update to v5.8.13

Fabio Berton (1):
      weston-init: Add environment file support for systemd unit file

Jon Mason (5):
      armv8/tunes: Move TUNECONFLICTS
      armv8/tunes: reference parent's TUNE_FEATURES
      armv8/tunes: Add tunes for supported ARMv8a cores
      armv8/tunes: Add tunes for supported ARMv8.2a cores
      tune-cortexa32: fix cortexa32 tune

Joshua Watt (2):
      classes/sanity: Bump minimum python version to 3.5
      classes/waf: Add build and install arguments

Khem Raj (3):
      systemd: Use ROOTPREFIX without suffixed slash in systemd.pc.in
      musl: Update to master
      strace: Fix value of IPPROTO_MAX

Martin Jansa (3):
      base.bbclass: use os.path.normpath instead of just comparing WORKDIR and S as strings
      mtd-utils: don't use trailing slash in S
      base.bbclass: warn when there is trailing slash in S or B variables

Michael Thalmeier (1):
      IMAGE_LOCALES_ARCHIVE: add option to prevent locale archive creation

Naoki Hayama (3):
      uninative: Fix typo in error message
      local.conf.sample: Fix comment typo
      local.conf.sample.extended: Fix comment typo

Naveen Saini (2):
      linux-yocto: update genericx86* SRCREV for 5.4
      linux-yocto: update genericx86* SRCREV for 5.8

Nicolas Dechesne (8):
      bitbake: docs: ref-variables: add links to terms in glossary
      bitbake: docs: sphinx: replace special quotes with double quotes
      bitbake: docs: update README file after migrationg to Sphinx
      bitbake: docs: sphinx: report errors when dependencies are not met
      bitbake: sphinx: remove DocBook files
      bitbake: sphinx: rename Makefile.sphinx
      sphinx: remove DocBook files
      sphinx: rename Makefile.sphinx

Peter Kjellerstedt (1):
      tune-cortexa65.inc: Correct TUNE_FEATURES_tune-cortexa65

Quentin Schulz (4):
      docs: ref-manual: ref-variables: fix one-letter pointer links in glossary
      docs: ref-manual: ref-variables: fix alphabetical order in glossary
      docs: ref-manual: ref-variables: add links to terms in glossary
      bitbake: docs: static: theme_overrides.css: fix responsive design on <640px screens

Richard Purdie (25):
      glibc: do_stash_locale must not delete files from ${D}
      libtools-cross/shadow-sysroot: Use nopackages inherit
      pseudo: Ignore mismatched inodes from the db
      pseudo: Add support for ignoring paths from the pseudo DB
      pseudo: Abort on mismatch patch
      psuedo: Add tracking of linked files for fds
      pseudo: Fix xattr segfault
      pseudo: Add may unlink patch
      pseudo: Add pathfix patch
      base/bitbake.conf: Enable pseudo path filtering
      wic: Handle new PSEUDO_IGNORE_PATHS variable
      pseudo: Fix statx function usage
      bitbake.conf: Extend PSEUDO_IGNORE_PATHS to ${COREBASE}/meta
      docs: Fix license CC-BY-2.0-UK -> CC-BY-SA-2.0-UK
      abi_version,sanity: Tell users TMPDIR must be clean after pseudo changes
      pseudo: Update to account for patches merged on branch
      pseudo: Upgrade to include mkostemp64 wrapper
      poky.conf: Drop OELAYOUT_ABI poking
      bitbake: command: Ensure exceptions inheriting from BBHandledException are visible
      bitbake: tinfoil: When sending commands we need to process events
      scripts/oe-build-perf-report: Allow operation with no buildstats
      oe-build-perf-report: Ensure correct data is shown for multiple branch options
      skeleton/baremetal-helloworld: Fix trailing slash
      oeqa/selftest/runtime_test: Exclude gpg directory from pseudo database
      bitbake: process: Show command exceptions in the server log as well

Ross Burton (10):
      bjam-native: don't do debug builds
      coreutils: improve coreutils-ptest RDEPENDS
      parted: improve ptest
      devtool: remove unused variable
      selftest: skip npm tests if nodejs-native isn't available
      selftest: add test for recipes with patches in overrides
      devtool: fix modify with patches in override directories
      boost: build a standalone boost.build
      boost: don't specify gcc version
      boost: consolidate and update library list

Usama Arif (1):
      kernel-fitimage: generate openssl RSA keys for signing fitimage

Victor Kamensky (2):
      qemu: add 34Kf-64tlb fictitious cpu type
      qemumips: use 34Kf-64tlb CPU emulation

Yann Dirson (1):
      rngd: fix --debug to also filter syslog() calls

Yoann Congal (1):
      bitbake-bblayers/create: Make the example recipe print its message

Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: I7139cb04b43f722a2118df5346a7a22a13c6a240

2 files changed, 119 insertions, 0 deletions

diff --git a/poky/meta/recipes-devtools/qemu/qemu.inc b/poky/meta/recipes-devtools/qemu/qemu.inc
index bbb9038961..6c0edcb706 100644
--- a/poky/meta/recipes-devtools/qemu/qemu.inc
+++ b/poky/meta/recipes-devtools/qemu/qemu.inc
@@ -31,6 +31,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
            file://0001-qemu-Do-not-include-file-if-not-exists.patch \
            file://find_datadir.patch \
            file://usb-fix-setup_len-init.patch \
+           file://0001-mips-add-34Kf-64tlb-fictitious-cpu-type-like-34Kf-bu.patch \
            "
 UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
 
diff --git a/poky/meta/recipes-devtools/qemu/qemu/0001-mips-add-34Kf-64tlb-fictitious-cpu-type-like-34Kf-bu.patch b/poky/meta/recipes-devtools/qemu/qemu/0001-mips-add-34Kf-64tlb-fictitious-cpu-type-like-34Kf-bu.patch
new file mode 100644
index 0000000000..b6312e1543
--- /dev/null
+++ b/poky/meta/recipes-devtools/qemu/qemu/0001-mips-add-34Kf-64tlb-fictitious-cpu-type-like-34Kf-bu.patch
@@ -0,0 +1,118 @@
+From b3fcc7d96523ad8e3ea28c09d495ef08529d01ce Mon Sep 17 00:00:00 2001
+From: Victor Kamensky <kamensky@cisco.com>
+Date: Wed, 7 Oct 2020 10:19:42 -0700
+Subject: [PATCH] mips: add 34Kf-64tlb fictitious cpu type like 34Kf but with
+ 64 TLBs
+
+In Yocto Project CI runs it was observed that test run
+of 32 bit mips image takes almost twice longer than 64 bit
+mips image with the same logical load and CI execution
+hits timeout.
+
+See https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
+
+Yocto project uses 34Kf cpu type to run 32 bit mips image,
+and MIPS64R2-generic cpu type to run 64 bit mips64 image.
+
+Upon qemu behavior differences investigation between mips
+and mips64 two prominent observations came up: under
+logically similar load (same definition and configuration
+of user-land image) in case of mips get_physical_address
+function is called almost twice more often, meaning
+twice more memory accesses involved in this case. Also
+number of tlbwr instruction executed (r4k_helper_tlbwr
+qemu function) almost 16 time bigger in mips case than in
+mips64.
+
+It turns out that 34Kf cpu has 16 TLBs, but in case of
+MIPS64R2-generic it is 64 TLBs. So that explains why
+some many more tlbwr had to be execute by kernel TLB refill
+handler in case of 32 bit misp.
+
+The idea of the fix is to come up with new 34Kf-64tlb fictitious
+cpu type, that would behave exactly as 34Kf but it would
+contain 64 TLBs to reduce TLB trashing. After all, adding
+more TLBs to soft mmu is easy.
+
+Experiment with some significant non-trvial load in Yocto
+environment by running do_testimage load shows that 34Kf-64tlb
+cpu performs 40% or so better than original 34Kf cpu wrt test
+execution real time.
+
+It is not ideal to have cpu type that does not exist in the
+wild but given performance gains it seems to be justified.
+
+Signed-off-by: Victor Kamensky <kamensky@cisco.com>
+---
+ target/mips/translate_init.inc.c | 55 ++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+
+diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
+index 637caccd89..b73ab48231 100644
+--- a/target/mips/translate_init.inc.c
++++ b/target/mips/translate_init.inc.c
+@@ -297,6 +297,61 @@ const mips_def_t mips_defs[] =
+         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
+         .mmu_type = MMU_TYPE_R4000,
+     },
++    /*
++     * Verbatim copy of "34Kf" cpu, only bumped up number of TLB entries
++     * from 16 to 64 (see CP0_Config0 value at CP0C1_MMU bits) to improve
++     * performance by reducing number of TLB refill exceptions and
++     * eliminating need to run all corresponding TLB refill handling
++     * instructions.
++     */
++    {
++        .name = "34Kf-64tlb",
++        .CP0_PRid = 0x00019500,
++        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
++                       (MMU_TYPE_R4000 << CP0C0_MT),
++        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
++                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
++                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
++                       (1 << CP0C1_CA),
++        .CP0_Config2 = MIPS_CONFIG2,
++        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
++                       (1 << CP0C3_DSPP),
++        .CP0_LLAddr_rw_bitmask = 0,
++        .CP0_LLAddr_shift = 0,
++        .SYNCI_Step = 32,
++        .CCRes = 2,
++        .CP0_Status_rw_bitmask = 0x3778FF1F,
++        .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
++                    (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
++                    (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
++                    (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
++                    (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
++                    (0xff << CP0TCSt_TASID),
++        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
++                    (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
++        .CP1_fcr31 = 0,
++        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
++        .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
++        .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
++        .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
++                    (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
++        .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
++        .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
++                    (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
++        .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
++        .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
++                    (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
++        .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
++        .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
++                    (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
++        .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
++        .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
++                    (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
++        .SEGBITS = 32,
++        .PABITS = 32,
++        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
++        .mmu_type = MMU_TYPE_R4000,
++    },
+     {
+         .name = "74Kf",
+         .CP0_PRid = 0x00019700,
+-- 
+2.14.5
+