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2024-05-29meta-nuvoton: npcm8xx-bootblock: update to 0.4.8Tim Lee1-14/+25
Changelog: version 0.4.8 - May 21th 2024 ============= - Set cntfrq_el0 should be after calling serial_printf_init. - Makefile: move object code to independent path. version 0.4.7 - May 7th 2024 ============= - Fix DDP\SDP type print. - Cleanup code for upstream. - Fix print of reset type for TIP reset case. - Bug fix: when using dlls_trim_clk override from header option INCR bit value is set to bit 7 instead of 6. Fixed to 6. - Add mode non-ECC ranges (8 total). - Fix build on Linux (change "Apps" folder to "apps"). - Upgrade compiler and compile by default with dwarf-3 (allow debugging with Lauterbach, for GDB switch to -ggdb). - Compile optimization for speed. - Fix Coverity issues. - Cleanup makefile. - Add bit (over scratchpad bits): INTCR2.HOST_INIT (bit 11). This bit indicates host is initialized by bootblock. After host is set bit is set to prevent re-init. - Bug fix: cntfrq_el0 was set back to 25000000 after warm boot, regardless of CPU frequency. Signed-off-by: Tim Lee <timlee660101@gmail.com> Change-Id: I5e0f51ce8e3ab55ec4caa244ebcd03cb0e1374ed
2023-05-28meta-nuvoton: npcm8xx-igps: update to 03.09.00Tim Lee1-5/+11
Changelog: IGPS 03.09.00 - May 18th 2023 ============== - TIP_FW 0.5.9 L0 0.4.8 L1 - Bootblock version 0.3.2 - skip clearing INTCR2 - SCRPAD 10 is now reset - split CRC file (tip\notip) - Clear SCRPAD10-19 - Add BootBlockAndHeader_A1_EB_NoTip.xml for EB IGPS 03.08.09 - May 14th 2023 ============== - TIP_FW 0.5.9 L0 0.4.8 L1 - Bootblock version 0.3.1 - Added code for A2 - flash: support flash size mix - restore: force main and recovery flashes to the same - Add timestamp compare to combo IGPS 03.08.08 - May 3rd 2023 ============== - TIP_FW 0.5.7 L0 0.4.6 L1 - Bootblock version 0.3.0 - Added support for no TIP mode - No TIP mode is only for A2 users - IGPS still supports TIP mode IGPS 03.08.07 - April 17th 2023 ============== - TIP_FW 0.5.7 L0 0.4.6 L1 - Bootblock version 0.2.9 - Support A2 Signed-off-by: Tim Lee <timlee660101@gmail.com> Change-Id: I2a2902f0ba07ad2ab2002357c8e5a4a228ed311a
2023-02-03meta-nuvoton: npcm8xx-bootblock: update SRC_URI of LICENSETim Lee1-6/+3
Change to use the LICENSE file from git repository to avoid build warning/error when fetch this package at the first time. Signed-off-by: Tim Lee <timlee660101@gmail.com> Change-Id: I84e01df1413308e87c61149225738d54b44b8169
2022-12-19meta-nuvoton: npcm8xx-bootblock: update to 0.2.8Benjamin Fair1-1/+1
Changelog: version 0.2.8 - Nov 22 2022 ============= - Bug fix: disable RECALIB in DDR, after training, before sweep phase. - eSPI: enable auto handshake. Version 0.2.6 - Oct 26 2022 ============= - Bug fix: If DRAM is 2GB and max DRAM size in header is smaller, GMMAP should be set according to header, not according to the physical device. Version 0.2.4 - Oct 18 2022 ============= - MC: Support 2GB DRAM - MC: Updated TRFC default to 2GB DRAM and fixed value for 1600/1G - CLK: always set PLLs by bootblock. Set all dividers in PORST. - SPI-X: upper limit of 33MHz. Signed-off-by: Benjamin Fair <benjaminfair@google.com> Change-Id: Ia82fba195139d245ccb7f62218a900069c575e2c
2022-12-01meta-nuvoton: move npcm8xx-bootblock recipe into inc fileTim Lee1-0/+25
Follow the other npcm8xx recipes to use different versions of this recipe for different platforms. Tested: build pass and boot up successfully with correct bootblock version. Signed-off-by: Tim Lee <timlee660101@gmail.com> Change-Id: Ic97de46876e7e821b65515846d40c939d273bcc1