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| author | Bjorn Andersson <andersson@kernel.org> | 2023-06-13 21:12:02 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-06-13 21:12:02 +0300 |
| commit | 0832b1c9d0145451ba82d0c163092787e87008f1 (patch) | |
| tree | 04a4983d8701dfc5e3f03872989761b1b28b8f6d | |
| parent | 3f01d016cf4b80382f1c1b8ab6bef7aa76dece01 (diff) | |
| parent | 83da70da40c93f3515aebcd5f2b8ff6283f64ee3 (diff) | |
| download | linux-0832b1c9d0145451ba82d0c163092787e87008f1.tar.xz | |
Merge branch '20230608125315.11454-2-srinivas.kandagatla@linaro.org' into arm64-for-6.5
Merge the SC8280XP LPASSCC DeviceTree bindings in order to get access
to the newly added reset defines.
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml | 60 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 17 |
2 files changed, 77 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..3326dcd6766c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpassaudiocc + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + - | + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h new file mode 100644 index 000000000000..d190d57fc81a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif |