diff options
| author | Xi Liu <xi.liu@amd.com> | 2024-03-07 21:16:42 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-03-22 22:49:45 +0300 |
| commit | 4cad092b989e11c66e747f03cd609a9ef74444ac (patch) | |
| tree | b80af84414021b870c7ed2601d4d9fe4ffbc45a6 | |
| parent | 8803bfffb7f81a6e62950ce772bd4d02b02b1adf (diff) | |
| download | linux-4cad092b989e11c66e747f03cd609a9ef74444ac.tar.xz | |
drm/amd/display: Remove unnecessary hard coded DPM states
[Why]
The hard coded DPM states are only used to fix mismatch states numbers from FW.
[How]
Remove when not needed.
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Xi Liu <xi.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c index 17a58f41fc6a..0a4dff45731f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c @@ -30,6 +30,10 @@ #define NUM_DCFCLK_STAS 5 +#if defined(CONFIG_DRM_AMD_DC_DCN3_51) +#define NUM_DCFCLK_STAS_NEW 8 +#endif + void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) { switch (dml2->v20.dml_core_ctx.project) { @@ -254,11 +258,21 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch; struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params; unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS]; +#if defined(CONFIG_DRM_AMD_DC_DCN3_51) + unsigned int dcfclk_stas_mhz_new[NUM_DCFCLK_STAS_NEW]; + unsigned int dml_project = dml2->v20.dml_core_ctx.project; +#endif unsigned int i = 0; unsigned int transactions_per_mem_clock = 16; // project specific, depends on used Memory type p->dcfclk_stas_mhz = dcfclk_stas_mhz; p->num_dcfclk_stas = NUM_DCFCLK_STAS; +#if defined(CONFIG_DRM_AMD_DC_DCN3_51) + if (dml_project == dml_project_dcn351) { + p->dcfclk_stas_mhz = dcfclk_stas_mhz_new; + p->num_dcfclk_stas = NUM_DCFCLK_STAS_NEW; + } +#endif p->in_bbox = in_bbox; p->out_states = out; p->in_states = &dml2->v20.scratch.create_scratch.in_states; @@ -436,8 +450,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, } dml2_policy_build_synthetic_soc_states(s, p); - if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 || - dml2->v20.dml_core_ctx.project == dml_project_dcn351) { + if (dml2->v20.dml_core_ctx.project == dml_project_dcn35) { // Override last out_state with data from last in_state // This will ensure that out_state contains max fclk memcpy(&p->out_states->state_array[p->out_states->num_states - 1], |