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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-06-13 00:20:40 +0300 |
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| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-06-13 00:23:33 +0300 |
| commit | 03c601927b673a243c9595e1ecc9e8adfdd02438 (patch) | |
| tree | 9ef1868a308ed0a30deae355bfb298d7b11d6d73 /Documentation/arch/sh/register-banks.rst | |
| parent | 1b90e8f8879c64d4f77dd1f25134397ac075b7bd (diff) | |
| parent | ba57b9b11f78530146f02b776854b2b6b6d344a4 (diff) | |
| download | linux-03c601927b673a243c9595e1ecc9e8adfdd02438.tar.xz | |
Merge branch 'drm-next' of git://anongit.freedesktop.org/drm/drm into msm-next-lumag-base
Merge the drm-next tree to pick up the DRM DSC helpers (merged via
drm-intel-next tree). MSM DSC v1.2 patches depend on these helpers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'Documentation/arch/sh/register-banks.rst')
| -rw-r--r-- | Documentation/arch/sh/register-banks.rst | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/Documentation/arch/sh/register-banks.rst b/Documentation/arch/sh/register-banks.rst new file mode 100644 index 000000000000..2bef5c8fcbbc --- /dev/null +++ b/Documentation/arch/sh/register-banks.rst @@ -0,0 +1,40 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================== +Notes on register bank usage in the kernel +========================================== + +Introduction +------------ + +The SH-3 and SH-4 CPU families traditionally include a single partial register +bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families +may have more full-featured banking or simply no such capabilities at all. + +SR.RB banking +------------- + +In the case of this type of banking, banked registers are mapped directly to +r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc +can still be used to reference the banked registers (as r0_bank ... r7_bank) +when in the context of another bank. The developer must keep the SR.RB value +in mind when writing code that utilizes these banked registers, for obvious +reasons. Userspace is also not able to poke at the bank1 values, so these can +be used rather effectively as scratch registers by the kernel. + +Presently the kernel uses several of these registers. + + - r0_bank, r1_bank (referenced as k0 and k1, used for scratch + registers when doing exception handling). + + - r2_bank (used to track the EXPEVT/INTEVT code) + + - Used by do_IRQ() and friends for doing irq mapping based off + of the interrupt exception vector jump table offset + + - r6_bank (global interrupt mask) + + - The SR.IMASK interrupt handler makes use of this to set the + interrupt priority level (used by local_irq_enable()) + + - r7_bank (current) |