summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
diff options
context:
space:
mode:
authorAndrew Bresticker <abrestic@chromium.org>2013-09-26 01:12:51 +0400
committerTomasz Figa <t.figa@samsung.com>2014-01-08 21:02:43 +0400
commit3538a2cf0e04ad69840d74f46f7f8af920d913b5 (patch)
treef01c90bdb68d818038b67d06aee0a86e0c4b0247 /Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
parentc08ceea3a9d3276ec464e8b74573b1c58e93db7f (diff)
downloadlinux-3538a2cf0e04ad69840d74f46f7f8af920d913b5.tar.xz
clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/clk-exynos-audss.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/clk-exynos-audss.txt7
1 files changed, 5 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 85b9e28078c8..180e8835569e 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
- - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
-
+ - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+ SoCs.
+ - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+ SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -49,6 +51,7 @@ i2s_bus 6
sclk_i2s 7
pcm_bus 8
sclk_pcm 9
+adma 10 Exynos5420
Example 1: An example of a clock controller node using the default input
clock names is listed below.