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author | Andy Chiu <andy.chiu@sifive.com> | 2022-04-05 12:19:28 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2022-04-06 15:54:51 +0300 |
commit | dc48f04fd6562de6019e9fc7ed9ed539d632babb (patch) | |
tree | dea8cfe08cb3227353a019b591f24ab4009f00e0 /Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml | |
parent | ab3a5d4c6081dbcfd90d19cc9849af89c6985d0f (diff) | |
download | linux-dc48f04fd6562de6019e9fc7ed9ed539d632babb.tar.xz |
dt-bindings: net: add pcs-handle attribute
Document the new pcs-handle attribute to support connecting to an
external PHY. For Xilinx's AXI Ethernet, this is used when the core
operates in SGMII or 1000Base-X modes and links through the internal
PCS/PMA PHY.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml')
0 files changed, 0 insertions, 0 deletions