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| author | Paul Walmsley <paul.walmsley@sifive.com> | 2019-08-09 00:46:58 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-08-09 02:05:38 +0300 |
| commit | 8e5e72e3314021a3d166c1d19a991a0870568856 (patch) | |
| tree | 65ea0b5ee64f16d9e56680de8cca76996358de87 /Documentation/devicetree/bindings/riscv/cpus.yaml | |
| parent | 81a48ee417387bef9cb720ca75980ee11ae9c901 (diff) | |
| download | linux-8e5e72e3314021a3d166c1d19a991a0870568856.tar.xz | |
dt-bindings: riscv: remove obsolete cpus.txt
Remove the now-obsolete riscv/cpus.txt DT binding document, since we
are using YAML binding documentation instead.
While doing so, transfer the explanatory text about 'harts' (with some
edits) into the YAML file, at Rob's request.
Link: https://lore.kernel.org/linux-riscv/CAL_JsqJs6MtvmuyAknsUxQymbmoV=G+=JfS1PQj9kNHV7fjC9g@mail.gmail.com/
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/cpus.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 9d3fe6aada2b..b261a3015f84 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -10,6 +10,18 @@ maintainers: - Paul Walmsley <paul.walmsley@sifive.com> - Palmer Dabbelt <palmer@sifive.com> +description: | + This document uses some terminology common to the RISC-V community + that is not widely used, the definitions of which are listed here: + + hart: A hardware execution context, which contains all the state + mandated by the RISC-V ISA: a PC and some registers. This + terminology is designed to disambiguate software's view of execution + contexts from any particular microarchitectural implementation + strategy. For example, an Intel laptop containing one socket with + two cores, each of which has two hyperthreads, could be described as + having four harts. + properties: compatible: items: |