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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2013-02-08 15:37:31 +0400
committerNishanth Menon <nm@ti.com>2014-09-08 20:38:41 +0400
commit4664d4d86012c4a51b9f40d0d72e27e39205e874 (patch)
tree1f7a7a8e296dc06a22a474409c24c5be6466389c /arch/arm/mach-omap2/omap-secure.h
parentd2136bce9db79f7d983f081c5d1b6e9359714dd6 (diff)
downloadlinux-4664d4d86012c4a51b9f40d0d72e27e39205e874.tar.xz
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
Enables MPUSS ES2 power management mode using ES2_PM_MODE in AMBA_IF_MODE register. 0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together. Broken! Fortunately, we do not support this anymore. 0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode independently. This is one time settings thanks to always ON domain. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor conflict resolutions, consolidation for DRA7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2/omap-secure.h')
-rw-r--r--arch/arm/mach-omap2/omap-secure.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 3e97c6c8ecf1..dec2b05d184b 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -45,6 +45,7 @@
#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
+#define OMAP5_MON_AMBA_IF_INDEX 0x108
/* Secure PPA(Primary Protected Application) APIs */
#define OMAP4_PPA_L2_POR_INDEX 0x23