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authorMike Dunn <mikedunn@newsguy.com>2013-01-08 01:55:14 +0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-01-08 15:30:08 +0400
commit053fe0f166e540a9766548572eccfc18c21ff353 (patch)
treebed09d030aafa8913dbbb4b196b297dc51ff36b8 /arch/arm/mach-pxa/pxa27x.c
parent07afa01813d547570a762034f0dce7fd8baa8b3d (diff)
downloadlinux-053fe0f166e540a9766548572eccfc18c21ff353.tar.xz
ALSA: pxa27x: rename pxa27x_assert_ac97reset()
This patch does nothing functionally, it just gives the function a new name and modifies the prototype slightly in order to clarify what the function is doing (which is not necessarily asserting the reset). Some commentary also added. Tested on a palm treo 680 machine. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'arch/arm/mach-pxa/pxa27x.c')
-rw-r--r--arch/arm/mach-pxa/pxa27x.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 616cb87b6179..69985b06c0da 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -53,17 +53,25 @@ static unsigned long ac97_reset_config[] = {
GPIO95_AC97_nRESET,
};
-void pxa27x_assert_ac97reset(int reset_gpio, int on)
+void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
{
+ /*
+ * This helper function is used to work around a bug in the pxa27x's
+ * ac97 controller during a warm reset. The configuration of the
+ * reset_gpio is changed as follows:
+ * to_gpio == true: configured to generic output gpio and driven high
+ * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
+ */
+
if (reset_gpio == 113)
- pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
- &ac97_reset_config[1], 1);
+ pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
+ &ac97_reset_config[1], 1);
if (reset_gpio == 95)
- pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
- &ac97_reset_config[3], 1);
+ pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
+ &ac97_reset_config[3], 1);
}
-EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
+EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
/* Crystal clock: 13MHz */
#define BASE_CLK 13000000