summaryrefslogtreecommitdiff
path: root/arch/arm/mach-s3c24xx
diff options
context:
space:
mode:
authorHeiko Stuebner <heiko@sntech.de>2014-05-09 00:48:44 +0400
committerKukjin Kim <kgene.kim@samsung.com>2014-05-09 00:48:44 +0400
commitd8b532578f39fdec159105bc415938910351a699 (patch)
tree75627b044235bf5643c7f2a604c23e0c981ff8d3 /arch/arm/mach-s3c24xx
parent3c27f314c676ee31eafd423ce2c640ed129cd5e0 (diff)
downloadlinux-d8b532578f39fdec159105bc415938910351a699.tar.xz
ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccf
The s3c24xx cpufreq driver needs to change the mpll speed and was doing this by writing raw values from a translation table into the MPLLCON register. Change this to use a regular clk_set_rate call when using the common clock framework and only write the raw value in the samsung_clock case. The s3c cpufreq driver does already aquire the mpll, so simply add a reference to struct s3c_cpufreq_config to let set_fvco access it. While struct clk is opaque the differenciation between samsung clock and common clock is kept, as the samsung-clock mpll clk does not implement a real set_rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx')
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 2a0aa5684e72..c1b7508523ad 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -14,6 +14,7 @@
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/io.h>
+#include <linux/clk.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
@@ -60,5 +61,12 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
*/
void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
{
+#ifdef CONFIG_SAMSUNG_CLOCK
__raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
+#endif
+
+#ifdef CONFIG_COMMON_CLK
+ if (!IS_ERR(cfg->mpll))
+ clk_set_rate(cfg->mpll, cfg->pll.frequency);
+#endif
}