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authorJoseph Lo <josephl@nvidia.com>2013-08-12 13:40:00 +0400
committerStephen Warren <swarren@nvidia.com>2013-08-12 22:22:38 +0400
commit5b795d051c61862cebf4f1d55edab6e9b3383b44 (patch)
treec91e4a8aa4d89e65753ae383d9c9b3b99022f268 /arch/arm/mach-tegra/iomap.h
parent20984c44b5a08620778ea14fa5807489170fd5ca (diff)
downloadlinux-5b795d051c61862cebf4f1d55edab6e9b3383b44.tar.xz
ARM: tegra: add common resume handling code for LP1 resuming
Add support to the Tegra CPU reset vector to detect whether the CPU is resuming from LP1 suspend state. If it is, branch to the LP1-specific resume code. When Tegra enters the LP1 suspend state, the SDRAM controller is placed into a self-refresh state. For this reason, we must place the LP1 resume code into IRAM, so that it is accessible before SDRAM access has been re-enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/iomap.h')
-rw-r--r--arch/arm/mach-tegra/iomap.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 399fbca27102..f2bdcb4eac94 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -24,6 +24,8 @@
#define TEGRA_IRAM_BASE 0x40000000
#define TEGRA_IRAM_SIZE SZ_256K
+#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K)
+
#define TEGRA_HOST1X_BASE 0x50000000
#define TEGRA_HOST1X_SIZE 0x24000