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authorJoseph Lo <josephl@nvidia.com>2013-08-12 13:40:03 +0400
committerStephen Warren <swarren@nvidia.com>2013-08-12 23:29:24 +0400
commit95872f427eca73b19ac9466c25afd9bb876dc1aa (patch)
treead27d867f762c37b98d59b892b9840ba38e3016a /arch/arm/mach-tegra/pm-tegra30.c
parent0017f447cc01fa499f1d10dec09702d381f13fe0 (diff)
downloadlinux-95872f427eca73b19ac9466c25afd9bb876dc1aa.tar.xz
ARM: tegra: add common LP1 suspend support
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are clock gated and SDRAM in self-refresh mode. That means the low level LP1 suspending and resuming code couldn't be run on DRAM and the CPU must switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. The LP1 low level handling code need to be moved to IRAM area first. And marking the LP1 mask for indicating the Tegra device is in LP1. The CPU power timer needs to be re-calculated based on 32KHz that was originally based on PCLK. When resuming from LP1, the LP1 reset handler will resume PLLs and then put DRAM to normal mode. Then jumping to the "tegra_resume" that will restore full context before back to kernel. The "tegra_resume" handler was expected to be found in PMC_SCRATCH41 register. This is common LP1 procedures for Tegra, so we do these jobs mainly in this patch: * moving LP1 low level handling code to IRAM * marking LP1 mask * copying the physical address of "tegra_resume" to PMC_SCRATCH41 * re-calculate the CPU power timer based on 32KHz Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm-tegra30.c')
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