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author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2019-01-25 19:42:49 +0300 |
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committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2019-02-09 13:40:13 +0300 |
commit | 3bba4e2fdc2d6865b63d5e9dde2984033236420e (patch) | |
tree | c16a34cd491b293b4b0c4efca97a0fea2f3e2cb5 /arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts | |
parent | c8ec3743385213375232239b524fb6cde595fedd (diff) | |
download | linux-3bba4e2fdc2d6865b63d5e9dde2984033236420e.tar.xz |
arm64: dts: bitmain: Add Sophon Egde board support
Add devicetree support for Sophon Edge board from Bitmain based on
BM1880 SoC. This board is one of the 96Boards Consumer and AI platform.
More information about this board can be found in 96Boards product page:
https://www.96boards.org/documentation/consumer/sophon-edge/
Only UART peripheral support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts')
-rw-r--r-- | arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts new file mode 100644 index 000000000000..6a3255597138 --- /dev/null +++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Linaro Ltd. + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + */ + +/dts-v1/; + +#include "bm1880.dtsi" + +/ { + compatible = "bitmain,sophon-edge", "bitmain,bm1880"; + model = "Sophon Edge"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <500000000>; + #clock-cells = <0>; + }; +}; + +&uart0 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart_clk>; +}; |