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| author | Rob Herring <robh@kernel.org> | 2024-04-17 23:38:47 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-04-29 11:27:52 +0300 |
| commit | 8b40a46966d294bc64bad0feb13d3304fde738f2 (patch) | |
| tree | 66139e6f49eaecc3852a4260e7aea605abd8a1a6 /arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | |
| parent | f45083c3435ee755cf53cab5f3a8b18b6d43735b (diff) | |
| download | linux-8b40a46966d294bc64bad0feb13d3304fde738f2.tar.xz | |
arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily,
it doesn't provide any detail on uarch specific events.
There's still remaining cases for CPUs without any corresponding PMU
definition and for big.LITTLE systems which only have a single PMU node
(there should be one per core type).
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 8581ea55d254..245bbd615c81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -12,6 +12,13 @@ #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; |