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| author | Frank Li <Frank.Li@nxp.com> | 2023-12-14 22:46:55 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2024-02-01 13:04:25 +0300 |
| commit | 5136ea6b109de66b1327a3069f88ad8f5efb37b2 (patch) | |
| tree | 8e717e630eb30e0d09ce15d0489f1e963c33e27f /arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi | |
| parent | 7edee2b297e5a4f805e5b945c0c0e6f4f8f719b5 (diff) | |
| download | linux-5136ea6b109de66b1327a3069f88ad8f5efb37b2.tar.xz | |
arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers
It is eDMA1 at QM, which have the same register with eDMA3 at qxp.
The below commit fix panic problem.
commit b37e75bddc35 ("arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup")
This fixes the IRQ and DMA channel numbers. While QM eDMA1 technically has
32 channels, only 10 channels are likely used for I2C. The exact IRQ
numbers for the remaining channels were unclear in the reference manual.
Fixes: e4d7a330fb7a ("arm64: dts: imx8: add edma[0..3]")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi')
0 files changed, 0 insertions, 0 deletions