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authorMarek Vasut <marex@denx.de>2023-09-21 22:29:33 +0300
committerShawn Guo <shawnguo@kernel.org>2023-10-12 13:18:55 +0300
commit2651723668870357ab2786985004235a74fdccad (patch)
treeb2273be0e6a8ea66e50b41fb3f2c860ae25e7fd5 /arch/arm64/boot/dts/freescale
parent320371562fae19b513668974fc58ffff91673435 (diff)
downloadlinux-2651723668870357ab2786985004235a74fdccad.tar.xz
arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT
In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3 carrier board, the on-SoM PHY PHYAD1 signal has been pulled high by the carrier board and changed the PHY MDIO address from 5 to 7. This has been fixed on production rev.200 SoM by additional buffer on the SoM PHYAD/LED signals, remove the workaround. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
index d4e95d640388..b749e28e5ede 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
@@ -212,10 +212,6 @@
};
};
-&ethphy0g {
- reg = <7>;
-};
-
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <&ethphypdk>;