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author | Kathiravan T <quic_kathirav@quicinc.com> | 2022-02-08 18:35:24 +0300 |
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committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-02-11 03:12:04 +0300 |
commit | 59892de947f0ca1d65426f7a6c6e258863fa65d7 (patch) | |
tree | 76a9dff7eda901227bd7ef7ee8119254f513a085 /arch/arm64/boot/dts/qcom/ipq8074.dtsi | |
parent | ff899133fdae9c4d63a59e544c821b1ee438dbd6 (diff) | |
download | linux-59892de947f0ca1d65426f7a6c6e258863fa65d7.tar.xz |
arm64: dts: qcom: ipq8074: enable the GICv2m support
GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq8074.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 27624f5a56ba..642f9e71dbcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -634,9 +634,18 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <1>; + #size-cells = <1>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + ranges = <0 0xb00a000 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xffd>; + }; }; timer { |