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| author | Pierre Gondois <pierre.gondois@arm.com> | 2022-11-07 18:57:09 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-12-29 19:22:11 +0300 |
| commit | 9435294c6517dc70bb608505b79097a58ea7c6a3 (patch) | |
| tree | 8bb586c79667c0b42efe50d283fb1934645bf398 /arch/arm64/boot/dts/qcom/sm6350.dtsi | |
| parent | dcc7cd5c46ca5e7bb8e4910ed8259597439c7246 (diff) | |
| download | linux-9435294c6517dc70bb608505b79097a58ea7c6a3.tar.xz | |
arm64: dts: qcom: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).
To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6350.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 00e43a0d2dd6..dcf2e7ccaea7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -50,9 +50,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -69,6 +71,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -85,6 +88,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -101,6 +105,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -117,6 +122,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -133,6 +139,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -150,6 +157,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -166,6 +174,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; |