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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 14:16:23 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-21 20:31:41 +0300 |
| commit | 8e0a95add7e3f3838d5b494ce645c48759ba4168 (patch) | |
| tree | e7d71514efca81f76ec4909d4425346dfae2cae5 /arch/arm64/boot/dts/qcom/sm8150.dtsi | |
| parent | b8347ba382ef334aeff256892229c0d6f818fd53 (diff) | |
| download | linux-8e0a95add7e3f3838d5b494ce645c48759ba4168.tar.xz | |
arm64: dts: qcom: sm8150: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-3-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8150.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a35c0852b5a1..ff22e4346660 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1901,6 +1901,16 @@ pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2011,6 +2021,16 @@ pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { |