summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
diff options
context:
space:
mode:
authorAdam Ford <aford173@gmail.com>2020-12-24 20:04:54 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-01-11 12:01:29 +0300
commitfe82bb4db5339ebe8175b0ff2d45757472c0415e (patch)
tree71b46a873f314f9e318fff9c04c33a94c863fa0b /arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
parentd207dc500bbcf8c6e1cbad375b08904f984f9602 (diff)
downloadlinux-fe82bb4db5339ebe8175b0ff2d45757472c0415e.tar.xz
arm64: dts: renesas: beacon: Configure programmable clocks
When the board was added, clock drivers were being updated done at the same time to allow the versaclock driver to properly configure the modes. Unfortunately, the updates were not applied to the board files at the time they should have been, so do it now. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20201224170502.2254683-1-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi27
1 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
index 9db120ccb58d..c788f294cb09 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/clk/versaclock.h>
/ {
backlight_lvds: backlight-lvds {
@@ -370,12 +371,36 @@
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
- /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
+
assigned-clocks = <&versaclock6_bb 1>,
<&versaclock6_bb 2>,
<&versaclock6_bb 3>,
<&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
+
+ OUT1 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT2 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <1800000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT3 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <3300000>;
+ idt,slew-percent = <100>;
+ };
+
+ OUT4 {
+ idt,mode = <VC5_CMOS>;
+ idt,voltage-microvolt = <3300000>;
+ idt,slew-percent = <100>;
+ };
};
};