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authorFabrizio Castro <fabrizio.castro@bp.renesas.com>2019-10-04 11:35:33 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2019-10-10 17:22:07 +0300
commit133e6c78c4937ea7449cf8542b14f7b37bf470ac (patch)
treeeb23544e7b45f4317ff957614e0c8bc5098f7c6c /arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
parentb3ddadfa28315c6417866eac35a3aee67fc06aa3 (diff)
downloadlinux-133e6c78c4937ea7449cf8542b14f7b37bf470ac.tar.xz
arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1
The plan for the HiHope RZ/G2N board is to enable pciec0 by default, and use pciec1 physical interface for SATA (as SATA and PCIE1 share the same physical interface), therefore move pciec1 enabling away from hihope-rzg2-ex. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Link: https://lore.kernel.org/r/1570178133-21532-8-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index f9e7cf68a739..28fe17e3bc4e 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -84,10 +84,6 @@
status = "okay";
};
-&pciec1 {
- status = "okay";
-};
-
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";