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authorAdam Ford <aford173@gmail.com>2020-12-24 20:04:55 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-01-11 12:01:29 +0300
commitb29120d6cfa978ae0721af855afbae3137c8e66d (patch)
tree14801ea737e0d6a59dbdaa24522661341a953d25 /arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
parentfe82bb4db5339ebe8175b0ff2d45757472c0415e (diff)
downloadlinux-b29120d6cfa978ae0721af855afbae3137c8e66d.tar.xz
arm64: dts: renesas: beacon kit: Fix Audio Clock sources
The SoC was expecting two clock sources with different frequencies. One to support 44.1KHz and one to support 48KHz. With the newly added ability to configure the programmable clock, configure both clocks. Assign the rcar-sound clocks to reference the versaclock instead of the fixed clock. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20201224170502.2254683-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
index 2c5b057c30c6..25eeac411f12 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
@@ -27,3 +27,24 @@
stdout-path = "serial0:115200n8";
};
};
+
+/* Reference versaclock instead of audio_clk_a */
+&rcar_sound {
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&versaclock6_bb 4>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
+};