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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-06-24 16:12:01 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-06-26 12:40:37 +0300 |
| commit | 59d8eee863ab5936e8fbb9b9b6a26e21d5078229 (patch) | |
| tree | a0d32e07aa5181a9bb0784c9c5edb6833ef8990b /arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts | |
| parent | a80f301ea69e76f10099626986b4674c6f990a15 (diff) | |
| download | linux-59d8eee863ab5936e8fbb9b9b6a26e21d5078229.tar.xz | |
arm64: dts: renesas: r8a774b1-hihope-rzg2n[-ex]: Rename HiHope RZ/G2N boards
The existing DTS files for HiHope RZ/G2N boards are for Rev.2.0 version
so reflect the same for the DTS file names so that the existing naming
convention can be used for Rev.3.0/4.0 boards.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1593004330-5039-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts new file mode 100644 index 000000000000..eb1206b2d97a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2N Rev.2.0 main board + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774b1.dtsi" +#include "hihope-common.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2N main board (Rev.2.0) based on r8a774b1"; + compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&sdhi3 { + mmc-hs400-1_8v; +}; |