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authorBiju Das <biju.das@bp.renesas.com>2019-02-07 11:31:49 +0300
committerSimon Horman <horms+renesas@verge.net.au>2019-02-08 13:49:09 +0300
commitaaf6c75c0458122600a20db9d41a0350f0a8dff8 (patch)
tree13ecc07a33a18d4ff43a0aa66818aae8442def72 /arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
parent2262798c002f9d106d7903a067c59474c59850d1 (diff)
downloadlinux-aaf6c75c0458122600a20db9d41a0350f0a8dff8.tar.xz
arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges mapping for pciec0 node. Also declare pcie bus clock, since it is generated on the CAT874 main board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 477a56b3273c..96ee0d2c6357 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -56,6 +56,15 @@
clock-frequency = <48000000>;
};
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
+
&pfc {
scif2_pins: scif2 {
groups = "scif2_data_a";