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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-02-18 16:30:19 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2020-02-21 16:41:36 +0300
commit721b76195b31467e56851fbab3855e700f281270 (patch)
tree892fdec875ad18f826fe9e0e879f6108bd3431ab /arch/arm64/boot/dts/renesas/r8a774c0.dtsi
parentd745c72da921acdf38d68681d5fc2ff113b78f55 (diff)
downloadlinux-721b76195b31467e56851fbab3855e700f281270.tar.xz
arm64: dts: renesas: rzg2: Add reset control properties for display
Add reset control properties to the device nodes for the Display Units on all supported RZ/G2 SoCs. Note that on these SoCs, there is only a single reset for each pair of DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200218133019.22299-5-geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774c0.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a774c0.dtsi5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index d4eee8fef35d..22785cbddff5 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1810,9 +1810,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
status = "disabled";