diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2019-01-15 15:02:42 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-02-08 13:49:07 +0300 |
| commit | dd7188eb4ed128dccc16b1d7dc1d639ddbd8882a (patch) | |
| tree | 35693a37f31c9233f68d386eb377993d1b851299 /arch/arm64/boot/dts/renesas/r8a77990.dtsi | |
| parent | e536d27e923c090e492b7e83e3f1267f7b74ebb7 (diff) | |
| download | linux-dd7188eb4ed128dccc16b1d7dc1d639ddbd8882a.tar.xz | |
arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices
This patch define OOP tables for all CPUs.
This allows CPUFreq to function.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a77990.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 786178cf1ffd..b42b9c760908 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -55,6 +55,27 @@ clock-frequency = <0>; }; + cluster1_opp: opp_table10 { + compatible = "operating-points-v2"; + opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -66,6 +87,8 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@1 { @@ -75,6 +98,8 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA53: cache-controller-0 { |